ATMEL ATV2500, ATV2500B User Manual
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Using the ATV2500 and ATV2500B
Introduction
This application note des cribes ho w to
use the features of the ATV2500 and
ATV2500B in the ABEL (and AtmelABEL) and CUPL (and Atmel-CUPL)
high level de scription lang uages. The
ATV2500 and ATV2500B are the most
powerful programmable logic devices
available in a 40/44-pin package. They
combine high dens ity and globa l rout ing,
making them easy to use and understand. Both devi ces h ave 24 macr ocells ,
each with three sum terms, two registers, and 17 product terms. Each register
has individual cl ock and AR product
terms. Each I/O pin has a programmable
polarity contro l and an individ ual output
enable product term. Independent feedback paths from each register allow all of
the registers to be buried without wasting
the I/O pins. A universal bus routes all
input and feedbac k si gnals to a ll pr oduct
terms on all macrocells. The ATV2500B
has the additional features of D- or
T-type configurable registers, three different clock options, and buried
combinatorial nodes. The ATV2500 and
ATV2500B macrocell is shown in
Figure 1.
Device Names and Pin and Node Assignments
The device names for the ATV2500 and
ATV2500B for each language are shown
in Table 1.
The buried nodes (Q1 and Q2/F2 in
each macrocell) are identified by node
numbers, as shown in Table 2.
The following exampl es show t he devi ce
type specification and the pin and node
assignments:
ABEL and Atmel-ABEL
device_id device ‘P2500B’;
“device_id will be used for
“JEDEC filename
I1,I2,I3,I17,I18 pin 1,2,3,17,18;
O4,O5 pin 4,5 istype ‘reg_d,buffer’;
O6,O7 pin 6,7 istype ‘com’;
O4Q2,O7Q2 node 41,44 istype ‘reg_d’;
O6F2 node 43 istype ‘com’;
O7Q1 node 220 istype ‘reg_d’;
CUPL and Atmel-CUPL
device V2500B;
pin [1,2,3,17,18] =
[I1,I2,I3,I17,I18];
pin [7,6,5,4] = [O7,O6,O5,O4];
pinnode [41,65,44] =
[O4Q2,O4Q1,O7Q2];
pinnode [43,68] = [O6Q2,O7Q1];
Erasable
Programmable
Logic Device
Application
Note
Table 1. Device Names
Device Type ABEL Device Name CUPL Device Name
ATV2500 DIP P2500 V2500
ATV2500 PLCC P2500C V2500LCC
ATV2500B DIP P2500B V2500B
ATV2500B PLCC P2500BC V2500BLCC
Rev. 0458C–09/99
1
Figure 1. The ATV2500 and ATV2500B
Macrocell Output Logic, Registered Output Logic, Combinatorial
Pin and Node Feedbacks
Each macrocell has three feedback paths into the array,
one from each of the registers and one from the pin. For a
buried node, the node name is used to refer to the feedback path. For a comb in ator i al outp ut, t he feedback comes
from the pin, so the pin name is used to refer to the feedback. For a registered output, the feedback can come
either from the register or from the pin. The feedback paths
are labeled (1), (2), and (3) on Figure 1. The following
examples show how the different feedback paths are
identified:
ABEL and Atmel-ABEL
O4.d = I1 # I2;
O4Q2.d = I1 & !I2;
O6 = O4 “(1)feedback from pin
# O4.fb “(2)feedback from Q1 register
# O4Q2; “(3)feedback from buried register
2
CMOS PLD
(1)
Note: 1. For ABEL, either “.q” or “.fb” can be used to indicate
the buried register feedback path. When “.q” extension is used, the software will select the Q outp ut of
the register, regardless of the output buffer polarity.
When the “.fb” extension is used, the software will
match the polarity of the register feedback with the
output polarity by selecting either the Q or !Q output
of the register.
CUPL and Atmel-CUPL
O4.d = I1 # I2;
O4Q2.d = I1 & !I2;
O6 = O4.io /*(1)feedback from pin */
# O4 /*(2)feedback from Q1 register */
# O4Q2; /*(3)feedback from buried register */
Table 2. Node Numbers
CMOS PLD
ABEL CUPL
Pin #
4(5) 217(221) 41(45) 65(69) 41(45)
5(6) 218(222) 42(46) 66(70) 42(46)
6(7) 219(223) 43(47) 67(71) 43(47)
7(8) 220(224) 44(48) 68(72) 44(48)
8(9) 221(225) 45(49) 69(73) 45(49)
9(10) 222(226) 46(50) 70(74) 46(50)
11(13) 223(227) 47(51) 71(75) 47(51)
12(14) 224(228) 48(52) 72(76) 48(52)
13(15) 225(229) 49(53) 73(77) 49(53)
14(16) 226(230) 50(54) 74(78) 50(54)
15(17) 227(231) 51(55) 75(79) 51(55)
16(18) 228(232) 52(56) 76(80) 52(56)
24(27) 229(233) 53(57) 77(81) 53(57)
25(28) 230(234) 54(58) 78(82) 54(58)
26(29) 231(235) 55(59) 79(83) 55(59)
27(30) 232(236) 56(60) 80(84) 56(60)
28(31) 233(237) 57(61) 81(85) 57(61)
Q1 Q2/F2 Q1 Q2/F2
29(32) 234(238) 58(62) 82(86) 58(62)
31(35) 235(239) 59(63) 83(87) 59(63)
32(36) 236(240) 60(64) 84(88) 60(64)
33(37) 237(241) 61(65) 85(89) 61(65)
34(38) 238(242) 62(66) 86(90) 62(66)
35(39) 239(243) 63(67) 87(91) 63(67)
36(40) 240(244) 64(68) 88(92) 64(68)
Note: Pin/node numbers: DIP(PLCC)
3
Macrocell Configurations
The basic m acroc ell co nfig ura tions are sh own i n Fi gur es 2
through 9. Each ma crocel l has thre e sum terms , each w ith
four product terms. The sum terms can b e combined for
wider fan-in functions or separated and used for buried
logic. The output ca n be conf igure d as eit her co mbinat orial
or registered. For a combinatorial output, the other two sum
terms can be connecte d to buried regi sters. For a r egis-
Figure 2. Combinatorial Output (12 product terms)
tered output, two of the sum ter ms are combin ed for the
output and the third can be connected to a buried register.
The multiple feedbac k path s als o a ll ow b oth reg is ter s to b e
buried, with the I/O pin used as an input pin. For the
ATV2500B, the Q2 node can also be configured as a buried combinatorial node, F2, as shown in Figu re 9.
ABEL and Atmel-ABEL
O6 = I1 # !I2 # I3 # !I17 # I18;
CUPL and Atmel-CUPL
O6 = I1 # !I2 # I3 # !I17 # I18;
Figure 3. Combinatorial Output (8 product terms) plus Buri ed Regi ste r (4 prod uct terms )
ABEL and Atmel-ABEL
O7 = I1 # !I2 # I3 # !I17 # I18;
O7Q2.d = I2 # I3 # I17;
CUPL and Atmel-CUPL
O7 = I1 # !I2 # I3 # !I17 # I18;
O7Q2.d = I2 # I3 # I17;
4
CMOS PLD
CMOS PLD
Figure 4. Combinatorial Output (4 product terms) plus 2 Buried Registers (4 product terms each)
ABEL and Atmel-ABEL
O7 = I3 & !I17;
O7Q1.d = I1 & I2
O7Q2.d = I2 # I3 # I17;
CUPL and Atmel-CUPL
O7 = I3 & !I17;
O7Q1.d = I1 & I2
O7Q2.d = I2 # I3 # I17;
Figure 5. Registered Output (12 product terms)
ABEL and Atmel-ABEL
O4.d = I1 # I2 # I3 # I17 # I18;
CUPL and Atmel-CUPL
O4.d = I1 # I2 # I3 # I17 # I18;
5
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