– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• High Endurance, Non-Volatile Memory Segments
– 2K/4K Bytes of In-System, Self-Programmable Flash Program Memory
• Endurance: 10,000 Write/Erase Cycles
– 128/256 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256 Bytes of Internal SRAM
– Data retention: 20 years at 85°C / 100 years at 25°C
– Programming Lock for Self-Programming Flash & EEPROM Data Security
• Peripheral Features
– One 8-Bit and One 16-Bit Timer/Counter with Two PWM Channels, Each
– 10-bit ADC
• 8 Single-Ended Channels
• 12 Differential ADC Channel Pairs with Programmable Gain (1x / 20x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-Chip Analog Comparator
– Universal Serial Interface
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– Internal and External Interrupt Sources
• Pin Change Interrupt on 12 Pins
– Low Power Idle, ADC Noise Reduction, Standby and Power-Down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-Out Detection Circuit with Software Disable Function
– Internal Calibrated Oscillator
– On-Chip Temperature Sensor
• I/O and Packages
– Available in 20-Pin QFN/MLF/VQFN, 14-Pin SOIC, 14-pin PDIP and 15-ball UFBGA
– Twelve Programmable I/O Lines
8-bit
Microcontroller
with 2K/4K
Bytes In-System
Programmable
Flash
ATtiny24A
(Preliminary)
ATtiny44A
Summary
Rev. 8183BS–AVR–03/10
1.Pin Configurations
Figure 1-1.Pinout of ATtiny24A/44A
PDIP/SOIC
VCC
(PCINT8/XTAL1/CLKI) PB0
(PCINT9/XTAL2) PB1
(PCINT11/RESET/dW) PB3
(PCINT10/INT0/OC0A/CKOUT) PB2
(PCINT7/ICP/OC0B/ADC7) PA7
(PCINT6/OC1A/SDA/MOSI/DI/ADC6) PA6
(ADC4/USCK/SCL/T1/PCINT4) PA4
(ADC3/T0/PCINT3) PA3
(ADC2/AIN1/PCINT2) PA2
(ADC1/AIN0/PCINT1) PA1
(ADC0/AREF/PCINT0) PA0
NOTE
Bottom pad should be
soldered to ground.
DNC: Do Not Connect
1
2
3
4
5
6
7
14
13
12
11
10
9
8
QFN/MLF/VQFN
PA 5
DNC
DNC
DNC
2019181716
1
2
3
4
5
678910
DNC
GND
VCC
DNC
GND
PA0 (ADC0/AREF/PCINT0)
PA1 (ADC1/AIN0/PCINT1)
PA2 (ADC2/AIN1/PCINT2)
PA3 (ADC3/T0/PCINT3)
PA4 (ADC4/USCK/SCL/T1/PCINT4)
PA5 (ADC5/DO/MISO/OC1B/PCINT5)
Pin 16: PA6 (PCINT6/OC1A/SDA/MOSI/DI/ADC6)
Pin 20: PA5 (ADC5/DO/MISO/OC1B/PCINT5)
PA 6
15
PA7 (PCINT7/ICP/OC0B/ADC7)
14
PB2 (PCINT10/INT0/OC0A/CKOUT)
13
PB3 (PCINT11/RESET/dW)
12
PB1 (PCINT9/XTAL2)
11
PB0 (PCINT8/XTAL1/CLKI)
DNC
Table 1-1.UFBGA - Pinout ATtiny24A/44A.
1234
A
BPA4PA7PB1PB3
CPA3PA2PA1PB0
DPA0GNDGNDVCC
2
ATtiny24A/44A
PA5PA6PB2
8183BS–AVR–03/10
1.1Pin Descriptions
1.1.1VCC
Supply voltage.
1.1.2GND
Ground.
1.1.3Port B (PB3...PB0)
Port B is a 4-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability except PB3 which has the RESET
RESET pin, program (‘0’) RSTDISBL fuse. As inputs, Port B pins that are externally pulled low
will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a
reset condition becomes active, even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny24A/44A as listed in
Section 10.2 “Alternate Port Functions” on page 57.
1.1.4RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The minimum pulse length is given in Table 20-4 on page 176. Shorter pulses are not guaranteed to
generate a reset.
ATtiny24A/44A
capability. To use pin PB3 as an I/O pin, instead of
The reset pin can also be used as a (weak) I/O pin.
1.1.5Port A (PA7...PA0)
Port A is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A has alternate functions as analog inputs for the ADC, analog comparator, timer/counter,
SPI and pin change interrupt as described in “Alternate Port Functions” on page 57.
8183BS–AVR–03/10
3
2.Overview
ATtiny24A/44A are low-power CMOS 8-bit microcontrollers based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny24A/44A
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
Figure 2-1.Block Diagram
VCC
GND
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
STATUS
REGISTER
ISP INTERFACE
8-BIT DATABUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER0
TIMER/
COUNTER1
INTERRUPT
UNIT
EEPROM
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
OSCILLATORS
DATA REGISTER
+
-
PORT A
ANALOG
COMPARATOR
PORT A DRIVERS
PA7-PA0
DATA DIR.
REG.PORT A
ADC
DATA REGISTER
PORT B
PORT B DRIVERS
PB3-PB0
DATA DIR.
REG.PORT B
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
4
ATtiny24A/44A
8183BS–AVR–03/10
ATtiny24A/44A
The ATtiny24A/44A provides the following features: 2K/4K byte of In-System Programmable
Flash, 128/256 bytes EEPROM, 128/256 bytes SRAM, 12 general purpose I/O lines, 32 general
purpose working registers, an 8-bit Timer/Counter with two PWM channels, a 16-bit timer/counter with two PWM channels, Internal and External Interrupts, a 8-channel 10-bit ADC,
programmable gain stage (1x, 20x) for 12 differential ADC channel pairs, a programmable
Watchdog Timer with internal oscillator, internal calibrated oscillator, and four software selectable power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. ADC Noise Reduction
mode minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules except the ADC. In Power-down mode registers keep their contents and all chip functions
are disbaled until the next interrupt or hardware reset. In Standby mode, the crystal/resonator
oscillator is running while the rest of the device is sleeping, allowing very fast start-up combined
with low power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The onchip ISP Flash allows the Program memory to be re-programmed in-system through an SPI
serial interface, by a conventional non-volatile memory programmer or by an on-chip boot code
running on the AVR core.
The ATtiny24A/44A AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
8183BS–AVR–03/10
5
3.Additional Information
3.1Resources
A comprehensive set of drivers, application notes, data sheets and descriptions on development
tools are available for download at http://www.atmel.com/avr.
3.2Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3Data Retention
3.4Disclaimer
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device has been characterized.
Note:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
8
ATtiny24A/44A
8183BS–AVR–03/10
ATtiny24A/44A
5.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND Regi stersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd − 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
3. Topside marking for ATtiny24A:
– 1st Line: T24
– 2nd Line: Axx
– 3rd Line: xxx
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazardous Substances (RoHS).
3. Topside marking for ATtiny44A:
– 1st Line: T44
– 2nd Line: Axx
– 3rd Line: xxx
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.
15-ball (4 x 4 Array), 0.65 mm Pitch, 3.0 x 3.0 x 0.6 mm, Ultra Thin, Fine-Pitch Ball Grid Array Package (UFBGA)
20M120-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead / Micro Lead Frame Package (QFN/MLF)
20M220-pad, 3 x 3 x 0.85 mm Body, Very Thin Quad Flat No Lead Package (VQFN)
12
ATtiny24A/44A
8183BS–AVR–03/10
7.Packaging Information
2325 Orchard Parkway
San Jose, CA 95131
TITLE
DRAWING NO.
R
REV.
14S1, 14-lead, 0.150" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
2/5/02
14S1
A
A1
E
L
Side View
Top View
End View
H
E
b
N
1
e
A
D
COMMON DIMENSIONS
(Unit of Measure = mm/inches)
SYMBOL
MIN
NOM
MAX
NOTE
Notes:1. This drawing is for general information only; refer to JEDEC Drawing MS-012, Variation AB for additional information.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusion and gate burrs shall not
exceed 0.15 mm (0.006") per side.
3. Dimension E does not include inter-lead Flash or protrusion. Inter-lead flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. L is the length of the terminal for soldering to a substrate.
5. The lead width B, as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value
of 0.61 mm (0.024") per side.
A1.35/0.0532–1.75/0.0688
A10.1/.0040–0.25/0.0098
b0.33/0.0130–0.5/0.0200 5
D8.55/0.3367–8.74/0.34442
E3.8/0.1497–3.99/0.15743
H5.8/0.2284–6.19/0.2440
L0.41/0.0160–1.27/0.05004
e 1.27/0.050 BSC
7.114S1
ATtiny24A/44A
8183BS–AVR–03/10
13
7.214P3
PIN
1
E1
A1
B
E
B1
C
L
SEATING PLANE
A
D
e
eC
eB
Notes: 1. This package conforms to JEDEC reference MS-001, Variation AA.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
14P3, 14-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
– Section 6. “Ordering Information” on page 11, added tape & reel and topside
marking, updated notes
5.Updated Figures:
– Figure 4-1“Block Diagram of the AVR Architecture” on page 7
– Figure 8-1“Reset Logic” on page 37
– Figure 14-1“Universal Serial Interface, Block Diagram” on page 116, USIDB ->
USIBR
– Figure 19-5“High-voltage Serial Programming Waveforms” on page 169
6.Updated Tables:
– Table 19-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM
Location,” on page 164, updated value for t
WD_ERASE
ATtiny24A/44A
9.2Rev. 8183A – 12/08
1.Initial revision. Created from document 8006H.
2.Updated "Ordering Information" on page 18 and page 18. Pb-plated packages are no
3.Updated data sheet template.
4.Removed all references to 8K device.
5.Updated characteristic plots of section “Typical Characteristics”, starting on page 182.
6.Added characteristic plots:
7.Updated sections:
longer offered and there are no separate ordering codes for commercial operation
range, the only available option now is industrial. Also, updated some order codes to
reflect changes in leadframe composition and added VQFN package option.
– “Internal Bandgap Voltage vs. Supply Voltage” on page 233
– “Internal Bandgap Voltage vs. Temperature” on page 233
– “Features” on page 1
– “Power Reduction Register” on page 34
– “Analog Comparator” on page 128
– “Features” on page 132
– “Operation” on page 133
– “Starting a Conversion” on page 134
– “ADC Voltage Reference” on page 139
8183BS–AVR–03/10
19
– “Speed Grades” on page 174
8.Updated Figures:
– “Program Memory Map” on page 15
– “Data Memory Map” on page 16
9.Update Tables:
– “Device Signature Bytes” on page 161
– “DC Characteristics. T
– “Additional Current Consumption for the different I/O modules (absolute values)” on
page 182
– “Additional Current Consumption (percentage) in Active and Idle mode” on page 183
= -40°C to +85°C” on page 173
A
20
ATtiny24A/44A
8183BS–AVR–03/10
ATtiny24A/44A
8183BS–AVR–03/10
21
HeadquartersInternational
Atmel Corporation
2325 Orchard Parkway
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www.atmel.com/contacts
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