– 64 Bytes of In-System Programmable EEPROM Data Memory for ATtiny12
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program and EEPROM Data Security
• Peripheral Features
– Interrupt and Wake-up on Pin Change
– One 8-bit Timer/Counter with Separate Prescaler
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
– Low-power Idle and Power-down Modes
– External and Internal Interrupt Sources
– In-System Programmable via SPI Port (ATtiny12)
– Enhanced Power-on Reset Circuit (ATtiny12)
– Internal Calibrated RC Oscillator (ATtiny12)
• Specification
– Low-power, High-speed CMOS Process Technology
– Fully Static Operation
• Power Consumption at 4 MHz, 3V, 25°C
– Active: 2.2 mA
– Idle Mode: 0.5 mA
– Power-down Mode: <1 µA
• Packages
– 8-pin PDIP and SOIC
• Operating Voltages
– 1.8 - 5.5V for ATtiny12V-1
– 2.7 - 5.5V for ATtiny11L-2 and ATtiny12L-4
– 4.0 - 5.5V for ATtiny11-6 and ATtiny12-8
Note: This is a summary document. A complete document
is available on our Web site at www.atmel.com.
design
1006FS–AVR–06/07
Rev. 1006FS–AVR–06/07
Not recommended for new
1
OverviewThe ATtiny11/12 is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny11/12
achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general-purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU),
allowing two independent registers to be accessed in one single instruction executed in
one clock cycle. The resulting architecture is more code efficient while achieving
throughputs up to ten times faster than conventional CISC microcontrollers.
Table 1. Parts Description
DeviceFlashEEPROMRegisterVoltage RangeFrequency
ATtiny11L1K-322.7 - 5.5V0-2 MHz
ATtiny111K-324.0 - 5.5V0-6 MHz
ATtiny12V1K64 B321.8 - 5.5V0-1.2 MHz
ATtiny12L1K64 B322.7 - 5.5V0-4 MHz
ATtiny121K64 B324.0 - 5.5V0-8 MHz
The ATtiny11/12 AVR is supported with a full suite of program and system development
tools including: macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
2
ATtiny11/12
1006FS–AVR–06/07
ATtiny11/12
ATtiny11 Block DiagramSee Figure 1 on page 3. The ATtiny11 provides the following features: 1K bytes of
Flash, up to five general-purpose I/O lines, one input line, 32 general-purpose working
registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with internal oscillator, and two software-selectable power-saving modes.
The Idle Mode stops the CPU while allowing the timer/counters and interrupt system to
continue functioning. The Power-down Mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next interrupt or hardware reset. The
wake-up or interrupt on pin change features enable the ATtiny11 to be highly responsive
to external events, still featuring the lowest power consumption while in the power-down
modes.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny11 is
a powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.
Figure 1. The ATtiny11 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
-
ANALOG
DATA REGISTER
ARATOR
COMP
+
PORTB
PORTB DRIVERS
HARDWARE
STACK
GENERALPURPOSE
REGISTERS
Z
ALU
STATUS
REGISTER
DATA DIR.
REG. PORTB
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
OSCILLATORS
1006FS–AVR–06/07
PB0-PB5
3
ATtiny12 Block DiagramFigure 2 on page 4. The ATtiny12 provides the following features: 1K bytes of Flash, 64
bytes EEPROM, up to six general-purpose I/O lines, 32 general-purpose working registers, an 8-bit timer/counter, internal and external interrupts, programmable Watchdog
Timer with internal oscillator, and two software-selectable power-saving modes. The
Idle Mode stops the CPU while allowing the timer/counters and interrupt system to continue functioning. The Power-down Mode saves the register contents but freezes the
oscillator, disabling all other chip functions until the next interrupt or hardware reset. The
wake-up or interrupt on pin change features enable the ATtiny12 to be highly responsive
to external events, still featuring the lowest power consumption while in the power-down
modes.
The device is manufactured using Atmel’s high-density nonvolatile memory technology.
By combining an RISC 8-bit CPU with Flash on a monolithic chip, the Atmel ATtiny12 is
a powerful microcontroller that provides a highly-flexible and cost-effective solution to
many embedded control applications.
Figure 2. The ATtiny12 Block Diagram
VCC
8-BIT DATA BUS
INTERNAL
CALIBRATED
OSCILLATOR
TIMING AND
CONTROL
GND
PROGRAM
COUNTER
STACK
POINTER
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
PROGRAMMING
LOGIC
-
ANALOG
DATA REGISTER
ARATOR
COMP
+
PORTB
PORTB DRIVERS
HARDWARE
STACK
GENERALPURPOSE
REGISTERS
Z
ALU
STATUS
REGISTER
SPI
DATA DIR.
REG. PORTB
MCU CONTROL
REGISTER
MCU STATUS
REGISTER
TIMER/
COUNTER
INTERRUPT
UNIT
EEPROM
OSCILLATORS
PB0-PB5
4
ATtiny11/12
1006FS–AVR–06/07
ATtiny11/12
Pin Descriptions
VCCSupply voltage pin.
GNDGround pin.
Port B (PB5..PB0)Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain
output. The port pins are tri-stated when a reset condition becomes active, even if the
clock is not running. The use of pins PB5..3 as input or I/O pins is limited, depending on
reset and clock settings, as shown below.
Table 2. PB5..PB3 Functionality vs. Device Clocking Options
Device Clocking OptionPB5PB4PB3
External Reset EnabledUsed
External Reset Disabled Input
External Crystal-UsedUsed
External Low-frequency Crystal-UsedUsed
External Ceramic Resonator-UsedUsed
External RC Oscillator-I/O
External Clock-I/OUsed
(1)
(3)
(4)
/I/O
(2)
-
--
(5)
-
Used
Internal RC Oscillator-I/OI/O
Notes:1. “Used” means the pin is used for reset or clock purposes.
2. “-” means the pin function is unaffected by the option.
3. Input means the pin is a port input pin.
4. On ATtiny11, PB5 is input only. On ATtiny12, PB5 is input or open-drain output.
5. I/O means the pin is a port input/output pin.
XTAL1Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2Output from the inverting oscillator amplifier.
RESET
Reset input. An external reset is generated by a low level on the RESET pin. Reset
pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter
pulses are not guaranteed to generate a reset.
Notes:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
Note:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. Some of the status flags are cleared by writing a logical one to them. Note that the CBI and SBI instructions will operate on
all bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions
work with registers $00 to $1F only.
1006FS–AVR–06/07
7
Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd⊕RrZ,N,V1
COMRdOne’s ComplementRd ← $FF - RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← $00 - RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (FFh - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd - 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd⊕RdZ,N,V1
SERRdSet RegisterRd ← $FFNone1
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1 None2
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2
CPRd,RrCompareRd - RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd - Rr - CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd - KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC + k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC + k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
SLEEPSleep(see specific descr. for Sleep function)None1
WDRWatch Dog Reset(see specific descr. for WDR/timer)None1
1006FS–AVR–06/07
9
Ordering Information
ATtiny11
Power SupplySpeed (MHz)Ordering CodePackageOperation Range
ATtiny11L-2PC
ATtiny11L-2SC
2.7 - 5.5V2
4.0 - 5.5V6
Notes:1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil-
lator has the same nominal clock frequency for all speed grades.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
8S28-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
10
ATtiny11/12
1006FS–AVR–06/07
ATtiny11/12
ATtiny12
Power SupplySpeed (MHz)Ordering CodePackageOperation Range
ATtiny12V-1PC
ATtiny12V-1SC
1.8 - 5.5V1.2
ATtiny12V-1PI
ATtiny12V-1PU
(2)
ATtiny12V-1SI
ATtiny12V-1SU
(2)
ATtiny12L-4PC
ATtiny12L-4SC
2.7 - 5.5V4
ATtiny12L-4PI
ATtiny12L-4PU
(2)
ATtiny12L-4SI
ATtiny12L-4SU
(2)
ATtiny12-8PC
ATtiny12-8SC
4.0 - 5.5V8
ATtiny12-8PI
ATtiny12-8PU
(2)
ATtiny12-8SI
ATtiny12-8SU
(2)
Notes:1. The speed grade refers to maximum clock rate when using an external crystal or external clock drive. The internal RC oscil-
lator has the same nominal clock frequency for all speed grades.
2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
8S28-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
1006FS–AVR–06/07
11
Packaging Information
8P3
D1
b3
4 PLCS
Top View
D
e
Side View
1
E
E1
N
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
b
b2
A2 A
SYMBOL
A0.2102
A20.1150.1300.195
b0.0140.0180.0225
b20.0450.0600.0706
b30.0300.0390.0456
c0.0080.0100.014
D0.3550.3650.4003
L
D10.0053
E0.3000.3100.3254
E10.2400.2500.2803
e0.100 BSC
eA0.300 BSC4
L0.1150.1300.1502
MIN
NOM
MAX
NOTE
Notes:1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
12
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
2325 Orchard Parkway
R
San Jose, CA 95131
TITLE
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
ATtiny11/12
DRAWING NO.
8P3
1006FS–AVR–06/07
01/09/02
REV.
B
8S2
θ
1
N
E
TOP VIEW
C
E1
END VIEW
A
b
L
A1
e
D
SIDE VIEW
ATtiny11/12
C
1
TOP VIEW
E
N
θ
E1
L
END VIEW
b
A
SYMBOL
A1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A 1.70 2.16
A1 0.05 0.25
b 0.35 0.48 5
C 0.15 0.35 5
D 5.13 5.35
E1 5.18 5.40 2, 3
E 7.70 8.26
L 0.51 0.85
θ 0° 8°
e 1.27 BSC 4
NOM
MAX
e
SIDE VIEW
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs are not included.
3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.
4. Determines the true geometric position.
5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
D
NOTE
4/7/06
R
1006FS–AVR–06/07
2325 Orchard Parkway
San Jose, CA 95131
TITLE
8S2, 8-lead, 0.209" Body, Plastic Small
Outline Package (EIAJ)
DRAWING NO.
8S2D
REV.
13
Datasheet Revision
History
Please note that the page numbers listed in this section are refering to this document.
The revision numbers are referring to the document revision.
Rev. 1006F-06/071.“Not recommended for new design”
Rev. 1006E-07/061. Updated chapter layout.
2. Updated Power-down in “Sleep Modes for the ATtiny11” on page 20.
3. Updated Power-down in “Sleep Modes for the ATtiny12” on page 20.
4. Updated Table 16 on page 36.
5. Updated “Calibration Byte in ATtiny12” on page 49.
6. Updated “Ordering Information” on page 10.
7. Updated “Packaging Information” on page 12.
Rev. 1006D-07/031. Updated V
Rev. 1006C-09/011. N/A
values in Table 9 on page 24.
BOT
14
ATtiny11/12
1006FS–AVR–06/07
HeadquartersInternational
Atmel Corporation
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