ATMEL ATmega8515, ATmega8515L User Manual

Features

• High-performance, Low-power AVR

• RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier

• Nonvolatile Program and Data Memories

– 8K Bytes of In-System Self-programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock bits

In-System Programming by On-chip Boot Program T rue R ead- While -W ri te Operation

– 512 Bytes EEPROM

Endurance: 100,000 Write/Erase Cycles – 512 Bytes Internal SRAM – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security

• Peripheral Features

– One 8-bit Timer/Counter with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Three PWM Chan nels – Programmable Serial USART – Master/Sl ave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Three Sleep Modes: Idle, Power-down and Standby

• I/O and Packages

– 35 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, 44-lead PLCC, and 44-pad MLF

• Operating Voltages

– 2.7 - 5.5V for ATmega8515L – 4.5 - 5.5V for ATmega8515

• Speed Grades

– 0 - 8 MHz for ATmega8515L – 0 - 16 MHz for ATmega8515

8-bit Microcontroller

8-bit Microcontroller with 8K Bytes In-System Programmable Flash

ATmega8515 ATmega8515L

2512F–AVR–12/03

Rev. 2512 F–AVR–12 /03

Pin Configurations

(May

)

Figure 1. Pinout ATmega8515

PDIP

TQFP/MLF

(OC0/T0) PB0

(T1) PB1 (AIN0) PB2 (AIN1) PB3

(SS) PB4 (MOSI) PB5 (MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

(TDX) PD1 (INT0) PD2 (INT1) PD3

(XCK) PD4

(OC1A) PD5

(WR) PD6

(RD) PD7

XTAL2 XTAL1

GND

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PLCC

(MOSI) PB5 (MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

NC*

(TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4

(OC1A) PD5

PB4 (SS)

PB3 (AIN1)

PB2 (AIN0)

PB1 (T1)

PB0 (OC0/T0)

NC*

4443424140393837363534

1 2 3 4 5 6 7 8 9 10 11

1213141516171819202122

NC*

GND

XTAL2

XTAL1

(RD) PD7

(WR) PD6

VCC

PA0 (AD0)

PA1 (AD1)

(A8) PC0

(A9) PC1

(A10) PC2

PA2 (AD2)

PA3 (AD3)

33 32 31 30 29 28 27 26 25 24 23

(A11) PC3

(A12) PC4

NC*

7 8 9 10 11 12 13 14 15 16 17

PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE0 (ICP/INT2) NC* PE1 (ALE) PE2 (OC1B) PC7 (A15) PC6 (A14) PC5 (A13)

NOTES:

1. MLF bottom pad should be soldered to ground.

2. * NC = Do not connect

(MOSI) PB5 (MISO) PB6

(SCK) PB7

RESET

(RXD) PD0

(TXD) PD1 (INT0) PD2 (INT1) PD3 (XCK) PD4

(OC1A) PD5

be used in future devices

PB4 (SS)

PB3 (AIN1)

PB2 (AIN0)

PB1 (T1)

PB0 (OC0/T0)

NC*

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

65432

4443424140

1819202122232425262728

NC*

GND

XTAL2

(RD) PD7

(WR) PD6

XTAL1

(A8) PC0

(A9) PC1

(A10) PC2

(A11) PC3

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE0 (ICP/INT2)

NC*

PE1 (ALE)

PE2 (OC1B)

PC7 (A15)

PC6 (A14)

PC5 (A13)

(A12) PC4

ATmega8515(L)

2512F–AVR–12/03

ATmega8515(L)

Overview The ATmega8515 is a low-powe r CMOS 8-bit microcontroller base d on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8515 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram Figure 2. Block Diagram

VCC

PA0 - PA7 PC0 - PC7

PORTA DRIVERS/BUFFERS

PE0 - PE2

PORTE DRIVERS/ BUFFERS

PORTC DRIVERS/BUFFERS

GND

PORTA DIGITAL INTERFACE

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

AVR CPU

PROGRAMMING

LOGIC

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

SPI

PORTE

DIGITAL

INTERFACE

PORTC DIGITAL INTERFACE

TIMERS/

COUNTERS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CTRL.

& TIMING

INTERRUPT

UNIT

EEPROM

USART

OSCILLATOR

INTERNAL CALIBRATED OSCILLATOR

XTAL1

XTAL2

RESET

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PORTB DIGITAL INTERFACE

PORTB DRIVERS/BUFFERS

COMP.

INTERFACE

PORTD DIGITAL INTERFACE

PORTD DRIVERS/BUFFERS

PD0 - PD7PB0 - PB7

The AVR core combines a ric h instr uctio n set wit h 32 general purpose worki ng regi sters . All the 32 regi sters are dire ctly conn ected to the Arithm etic Logic U nit (A LU), all owing two independent regist ers t o be acces sed i n one sing le inst ructi on execut ed in one clo ck cycle. The resulting arc hitect ur e is more code eff icient whil e achievi ng throug hput s up to ten times faster than conventional CISC microcontrollers.

The ATmega8515 provides the foll owing featur es: 8K bytes of In-Sy stem Progra mmable Flash with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, an External memory interfa ce, 35 genera l purpose I/O lines, 32 ge neral purpo se working registers, two flexible Timer/Counters with compare modes, Internal and External interrupts, a Serial Prog rammabl e U SART, a pr ogramma ble Watch dog T imer w ith in ternal Oscillator, a SPI se rial port, and three s oft ware sel ectabl e power saving modes . The Idl e mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and Interrupt system to continue functioning. The Power-down mode saves the Register contents but freezes the Oscillator, disab ling all other chip f unctions unt il the ne xt interrupt or ha rdware reset. In St andby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density nonvolatile memory technology. The On-chip ISP Flash allows the Program memory to be reprogrammed In-System through an SPI serial interf ace, by a convent ional nonvol atile memory p rogrammer, or by an On-chip Boot program running on the AVR core. The boot program can u se any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC C PU with In-System Self-programmable Flash on a monolithic chip, the Atmel ATmega8515 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega8515 is supported with a full suite of program and system development tools including: C Com pilers, M acro assembl ers, Program debugge r/simulators, In-circuit Emulators, and Evaluation kits.

Disclaimer Typical values contained i n this dat asheet are based on simulatio ns and ch aracteriza-

tion of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

AT90S4414/8515 and ATmega8515 Compatibility

A T90S4414/8515 Compatibility Mode

The ATmega8515 provides all the features of the AT90S4414/8515. In addition, several new features are added. The ATmeg a8515 is backward compatible with AT90S4414/8515 in most c ases. However, some inco mpatibilities be tween the two microcontrollers exist. To solve this problem, an AT90S4414/8515 com patibility mode can be selected by programming the S8515C Fuse. ATmega8515 is 100% pin compatible with AT90S4414/8515, and can replace the AT90S4414/8515 on current printed circuit boards. However, the location of Fuse bits and the electrical characteris tics differs between the two devices.

Programming the S8515C Fuse will change the following functi onality:

• The timed sequence for changing the Watchdog Time-out period i s disabled. See “Timed Sequences for Changing t he Configurat ion of the Watchdog Timer” on page 52 for details .

• The double buffering of the USART Receive Registers is disabl ed. See “AVR USART vs. AVR UART – Compatibility” on page 135 for details.

• PORTE(2:1) will be set as output, and PORTE0 will be set as input.

ATmega8515(L)

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ATmega8515(L)

Pin Descriptions

VCC Digital supply voltage. GND Ground. Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port A output buf fers have symmetrical drive char acteristics with both high sink and source capability. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-u p resistors are activated. The Por t A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port A also serves the functions of vario us special features of the ATmega8515 as listed on page 66.

Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port B output buf fers have symmetrical drive char acteristics with both high sink and source capability. As inputs, Por t B pins that are externally p ulled low w ill source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B also serves the functions of vario us special features of the ATmega8515 as listed on page 66.

Port C (PC7..PC0) Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port C output buffers have symmetri cal drive character ist ics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D (PD7..PD0) Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port D output buffers have symmetri cal drive character ist ics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functi ons of vari ous spe cial featu res of the ATmega85 15 as list ed on page 71.

Port E(PE2..PE0) Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each

bit). The Port E output buf fers have symmetrical drive char acteristics with both high sink and source capability. As inputs, Por t E pins that are externally p ulled low w ill source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of vario us special features of the ATmega8515 as listed on page 73.

RESET

XTAL1 Input to the inverting Osci ll ator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting Oscillator amplifier.

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Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 18 on page 45. Shorter pulses are not guara nteed to generate a reset.

About Code Examples

This documentation contai ns simpl e code examples that bri efly show how to use var ious parts of the device. These cod e example s assume tha t the part speci fic header file is included before compilation. Be aware that not all C Compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C Compiler documentation for more det ails.

ATmega8515(L)

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ATmega8515(L)

AVR CPU Core

Introduction This section discusses the AV R core architecture in general. The main function of the

CPU core is to e nsu re corre ct program exec ution. The CP U mu st there fore b e abl e to access memories, perform cal culations, control peripher als, and handle interrupts.

Architectural Overview Figure 3. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Status

and Control

32 x 8 General Purpose

Registrers

ALU

Indirect Addressing

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

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I/O Lines

In order to maximize per formance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the Program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the Program memory. This concept enables in struc tions to be exec uted in ever y clock cy cle. Th e Progr am mem ory is I nSystem re programmable Flash memory.

The fast-access Regist er File contains 32 x 8-bit general purpose working registers with a single clock cycle a ccess time. This a llows single -cycle Arithmetic Logic Unit (ALU) operation. In a typical AL U operation, two operands are out put from the Registe r File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for loo k up tables in Flash Program memory. These adde d function registers are the 1 6-bit X-, Y-, and Z-register, described later in t his section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the St atus Regist er is updat ed to reflect i nformation a bout the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every Program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program secti on. Both sections hav e dedicated Lock bits for write and read/write protect ion. The SPM instruction that writ es into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine cal ls, the return address Program Counter (PC) is stored on the Stack . Th e Stac k is effectiv ely al locat ed in t he general data SRAM , a nd consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The Stack Pointer SP is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

ALU – Arithmetic Logic Unit

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its Control Registers in the I/O space with an additional

Global Interrupt Enable bit in the Status Registe r. All interrupts have a separat e interrupt vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector pos ition. The lower the Interrupt Vect or address, the higher the priorit y.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations follo wing those of the Register File, $20 - $5F.

The high-performance AVR ALU operates in direct connection with all the 32 general purpose worki ng register s. Withi n a single cl ock cycle, arithmet ic operat ions betw een general purp ose regis ters or be tween a re giste r and an imme diate ar e ex ecuted . T he ALU operations are divided i nto three main categories – ari thmet ic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsi gned m ultiplic ation and fractio nal format. See the “Ins truction Set” section for a detailed description.

ATmega8515(L)

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ATmega8515(L)

Status Register The Status Register contains information about the result of the most recently executed

arithmetic instruction. This information can be used for altering program flow in order to perform conditi onal opera tions. Note that the Stat us Registe r is update d after all AL U operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not a utomaticall y stored wh en ent ering an i nterrupt routine and restored when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 76543210

ITHSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Glob a l In te r ru p t En a bl e

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable cont rol i s then pe rf ormed in se parat e Contro l Reg isters. I f the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable sett ings. The I-bit is cl eared by hardwar e after an in terrup t has occurred, and is set by the RETI instruction to enable subsequent interrupts. The Ibit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as sour ce or destination for the operated bit. A bit from a register in the Reg ister File can be copied into T by the BST instruction, and a bit i n T can be copied into a b it in a reg ister in the Register File by the BLD instruct ion.

• Bit 5 – H: Half Car ry Flag

The Half Carry Fl ag H indicates a Hal f Carry in some ari thmetic operations. Half Carry is useful in BCD arithmetic. See the “Instru cti on Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusiv e or between t he Negative Flag N and the Two’ s Complement Overflow Flag V. See the “Instruction Set Descr iption” for detailed information.

• Bit 3 – V: Two’s Complement O ve r fl ow F lag

The Two’s C omplem ent O verflow Fla g V s upports two’s compl eme nt a rithmet ics. S ee the “Instruction Set Descr iption” for detailed information.

• Bit 2 – N: N e gative F lag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Descr iption” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result i n an arith metic or logic operation. S ee the “Instruction Set Description” for detailed information.

• Bit 0 – C: Carry Flag

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The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

General Purpose Register File

The Register F ile is optim ized f or the A VR E nhanc ed RIS C in struction set. I n orde r to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit resu lt input

• One 16-bit output operand and one 16-bit result input Figure 4 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4. AVR CPU General Purpose Working Registers

70Addr.

R0 $00 R1 $01 R2 $02

…

R13 $0D

General R14 $0E Purpose R15 $0F Working R16 $10

Registers R17 $11

… R26 $1A X-register Low Byte R27 $1B X-register High Byte R28 $1C Y-register Low Byte R29 $1D Y-register High Byte R30 $1E Z-register Low Byte R31 $1F Z-register High Byte

Most of the instruction s operati ng on the Regist er File have di rec t access to al l regi sters , and most of them are single cycle instructions.

As shown in Figure 4, each register is also assigned a Data memory address, mapping them directly into the first 32 locati ons of the user Data Space. Although not being physically implemented as SRAM locations, t his memory organizati on provides great flexibility in access of the registers, as the X-, Y-, and Z-pointer Registers can be set to index any register in the file.

ATmega8515(L)

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ATmega8515(L)

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for i ndirect addressing of the Data Sp ace. The three indirect address registers X, Y, and Z are defined as described in Figure 5.

Figure 5. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 ($1B ) R26 ($1A )

15 YH YL 0

Y-register 7 0 7 0

R29 ($1D ) R28 ($1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 ($1F ) R30 ( $1E)

In the different addressi ng mode s these ad dress registe rs have f unctions as f ixed di splacement, automatic increm ent, and autom atic decremen t (see the Inst ruction Set reference for details).

Stack Pointer The Stack is mainly used for storing temp orary data, for storing l ocal variables and for

storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memory locati ons to lower mem ory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above $60. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by two when address is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used i s implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 1514131211109 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value00000000

00000000

2512F–AVR–12/03

Instruction Execution Timing

This section describes the gener al access timing conc epts for i nstruct ion execut ion. The AVR CPU is driven by the CPU clock clk

, directly generated from the selected clock

CPU

source for the chip. No internal clock division is used. Figure 6 shows the parallel instructi on fetches and instruc tion exec utions enab led by the

Harvard architecture and the fast-access Register Fil e concept. This is the basic pipelining concept t o obtain up t o 1 M IPS p er MH z with t he co rrespondin g u nique res ults for functions per cost, functions per clocks, and functions per power-unit.

Figure 6. The Paral lel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 7 shows the internal timing concept for the Register File. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination regis ter.

Reset and Interrupt Handling

Figure 7. Single Cycle ALU Operat ion

T1 T2 T3 T4

clk

CPU

Total Execution Time

ALU Operation Execute

Result Write Back

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vecto r in the Program memory space. All interrupts are assigned indi vidual en able bits w hich must b e wr itten logic one together with the Global Interru pt Ena ble bit i n the Stat us Reg ister in orde r to enabl e the i nterr upt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memor y Programming” on page 177 for details.

The lowest addresse s in the Program memory spa ce are by default define d as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 53. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority l evel. RESET ha s the highe st priority, and next is INT0 – the External Interrupt Request 0. The Interr upt Vectors can be moved to the star t of the Boot Flash section by setting the IVSEL bit in the General Int errupt Control Register (GICR). Refer to “Interrupts” on page 53 for more information. The Reset Vector can

ATmega8515(L)

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ATmega8515(L)

also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Boot Loader Support – Read-While-Write Self-Programming” on page 164.

When an interrupt occurs, the Global In terrupt Enab le I-bit is cleared and al l interrupts are disabled. The user softw are ca n wri te logi c on e to the I-bit t o en able n este d int errupts. All enabled interrupts can then i nterrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basicall y two types of inter rupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bi t posi tion( s) to be c leared. If an i nterr upt condi tion oc cur s while the corresponding Interrupt Enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding interrupt flag(s) will be set and remembered until th e Global Interrupt Enable bit is set, and will then be executed by order of pri ority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the interrupt is enabled, the interrupt will not be tri ggered.

When the AVR exits from an interrupt, it will always return to the main pr ogram and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid int errupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value cli ; disable interrupts during timed sequence sbi EECR, EEMWE ; start EEPROM write sbi EECR, EEWE out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ _CLI(); EECR |= (1<<EEMWE); /* start EEPROM write */ EECR |= (1<<EEWE); SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending inter rupt s, as shown in this example.

Assembly Code Example

sei ; set global interrupt enable sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending ; interrupt(s)

C Code Example

_SEI(); /* set global interrupt enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */

Interrupt Response Time The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the Program Vector address for the actual interrupt handling routine is executed. During this f our clock cycle period, the Program Counter is pushed onto the Stack. Th e Vector is n ormally a jum p to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in additio n to the st art-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock cycles, t he Program Counter (two bytes) is popped back from the St ack, the Stack Pointer is incremented by two, and the I-bit in SREG is set.

ATmega8515(L)

2512F–AVR–12/03

ATmega8515(L)

AVR ATmega8515 Memories

In-System Reprogramma ble Flash Program memory

This section describes the different memories in the ATm ega8515. The AVR archit ecture has two main memory spaces, the Data Memory and the Program memory space. In addition, the ATmega8515 features an EEPROM Mem ory for data storage. All three memory spaces are linear and regul ar.

The ATmega8515 contains 8K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 4K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash me mory has an endurance of at least 10 ,000 write/erase cycles. The ATmega8515 Program Cou nter (PC) is 1 2 bits wi de, th us add ressing the 4K Progra m memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – ReadWhile-Write Self-Pr ogramming” on page 164. “Memory Programming” on page 177 contains a detailed description on Flash data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space, see the LPM – Load Program memory instruction description.

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Timing” on page 12.

Figure 8. Program memory Map

Application Flash Section

Boot Flash Section

$000

$FFF

2512F–AVR–12/03

SRAM Data Memory Figure 9 shows how the ATmega8515 SRAM Memory is organized.

The lower 608 Data Me mory loc ations address the Regi ster File, the I/O Mem ory, and the internal data SRAM. The first 96 locations ad dress the R egister File and I /O Memory, and the next 512 locations address the internal data SRAM.

An optional external data SRAM can be used with the ATmega8515. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register File, I/O, Extended I/O and Internal SRAM occu pies the lowest 608 bytes i n normal mode, so when using 64KB (65536 bytes) of External Memory, 64928 Bytes of External Memory are available. See “External Memory Interface” on page 24 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal Data memory locations, the external data SRAM is accessed using the same instructions as for the internal Data mem ory access. W hen the internal d ata mem ories are acce ssed, the read and write strobe pins (PD7 and PD6) are inactive during the whole access cycle. External SRAM operation is enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycl e per byte compar ed to acce ss of the internal SRAM. This means that the commands LD, ST, LD S, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subrou tine cal ls and r eturn s take t hre e clock cy cles ext ra because t he two-byte Progra m Counte r is pushed and po pped, and external me mory acce ss does not take advantage of the interna l pipe-line memory access. When external SRAM interface is used with wait-stat e, one-byt e external acces s takes two, three, or fo ur additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the i nstruction set manual for one, two, and three wait-states.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displacement, Indirect , Indi rect with Pre- decr ement, and Indir ect wit h Post-i ncre ment. In the Register File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing rea ches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base

address given by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-

increment, the address regis ter s X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O Registers, and the 512 bytes of inter-

nal data SRAM in the ATmega8515 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 10.

ATmega8515(L)

2512F–AVR–12/03

Figure 9. Data Memory Map

ATmega8515(L)

Data Memory

32 Registers

64 I/O Registers

Internal SRAM

(512 x 8)

External SRAM

(0 - 64K x 8)

$0000 - $001F $0020 - $005F $0060

$025F $0260

$FFFF

Data Memory Access Times This section describes the general access timing concepts for internal memory access.

The internal data SRAM access is performed in two clk

cycles as described in Figure

CPU

10. Figure 10. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Compute Address

Address Valid

Data

Write

Data

Memory Access Instruction

Next Instruction

Read

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EEPROM Data Memory The ATmega8515 contains 512 bytes of data EEPROM memory. It is organized as a

separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at l east 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

“Memory Programming” on page 177 contains a detailed description on EEPROM Programming in SPI or Parallel Programming mode.

EEPROM Read/Write Access The EEPROM Access Registers are accessible in the I/O space.

The write access time for the EEPROM is given in Table 1. A self-timing function, however, lets the us er softw are detec t wh en the n ext b yte can be written. If the u ser code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See “Preventing EEPROM Corruption” on page

23. for details on how to avoid problems in these si tuations. In order to prevent unintenti onal EEPROM writes, a specific wr ite pro cedure must be f ol-

lowed. Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU i s halted for four clock cycles before the next

instruction is execut ed. Wh en the E EPRO M is w ritten, the CPU is h alted fo r two cl ock cycles before the next instr u ction is executed.

is likely to rise or fal l slowly on Power-up/down. Thi s

The EEPROM Address Register – EEARH and EEARL

Bit 151413121110 9 8

–––––––EEAR8EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543210

Read/Write R R R R R R R R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000000X

XXXXXXXX

• Bits 15..9 – Res: Reserved Bits

These bits are reserved bit s in t he ATmega8515 and will always read as zero.

• Bits 8..0 – EEAR8..0: EEPROM Address

The EEPROM Ad dress Registers – EEAR H and EEARL – speci fy the EEPROM address in the 512 bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 511. The ini tial val ue o f EEAR is undefi ned. A proper value must be written before the EEPROM may be accessed.

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ATmega8515(L)

The EEPROM Data Register – EEDR

The EEPROM Control Regi ster – EECR

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bit s in t he ATmega8515 and will always read as zero.

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Re ady interrupt generates a constant interrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines wh ether setting E EWE to one causes the EEP ROM to be written. When EEMWE is set, setting EEWE within four clock cyc les will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to one by software, hardware cl ears the bit to zero after four clock cycles. See the description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be written to one to write the value into the EEPROM. The EEMWE bit must be written to one before a logical one is written to EEWE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN in SPMCR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE. The EEPROM can not be progra mmed du ring a CPU write to the Flash me mory. The

software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader al lowing the CPU to program the F lash. If the F lash is never being u pdated by the CPU, st ep 2 can be omitted. See “Boot Loa der Suppo rt – Read-While-Writ e Self-Programmin g” on page 164 for details about boot programming.

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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing th e inte rrupted E EPROM acce ss to fa il. It is recom mended to ha ve the Global Interrupt Flag cleared during all the steps to avoid these prob lems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero bef ore writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the n ext instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit be fore st artin g the read oper ation. If a wri te opera tion is in progress, it is neither pos sible to read the EEPRO M, nor to change the EEAR Register.

The calibrated Oscil lator is used to time the EEPROM accesses. Tabl e 1 lists the typical programming time for EEPROM access from the CPU.

Table 1. EEPROM Programming Time

Number of Calibrated RC

Symbol

EEPROM Write (from CPU) 8448 8.5 ms

Note: 1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

Oscillator Cycles

(1)

Typ Programming Time

The following code examples show one assembly and on e C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no inte rrupts w ill occur d uring execut ion of t hese functions. T he examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

ATmega8515(L)

2512F–AVR–12/03

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE ret

C Code Example

ATmega8515(L)

void EEPROM_write(unsigned int uiAddress, unsigned char ucData) {

/* Wait for completion of previous write */ while(EECR & (1<<EEWE))

; /* Set up address and data registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMWE */ EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interru pts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18 out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress) {

/* Wait for completion of previous write */

while(EECR & (1<<EEWE))

; /* Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

EEPROM Write During Power down Sleep Mode

ATmega8515(L)

When enteri ng Pow er-down Sl eep mo de while an EEPROM write op eration i s active, the EEPRO M write operat ion w ill con tinue, and will comple te b efore t he Wr ite Access time has passed. However, when the write operation is completed, the crystal Oscillator continues running, an d as a conseq uence, the d evice doe s not enter Po wer-down entirely. It is therefore recommended to verify that the EEPROM write operation is completed before entering Power-down.

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ATmega8515(L)

Preventing EEPROM Corruption

During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is too low for the CPU and the EEPROM to operate properly. These issues are the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations wh en the voltage is too low. First, a regular write sequence to t he EEPROM requires a minimum volt age to operate correctly. Second ly, the CPU itself can execute ins tructions incorrectly , if the supply voltage is too low.

EEPROM da ta corruption can easily be avoided by fol lowing this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can be done by enabling the internal Brown-out Detector (BOD). If the detection level of the intern al BOD does no t match the needed det ection l evel, an external low V write operation is in pro gres s, the writ e oper ation will be complet ed provi ded that t he power supply voltage is suffici ent.

Reset Protection circuit can be used. If a Reset occurs while a

I/O Memory The I/O space definition of the ATmega85 15 is shown i n “Register Summa ry” on page

237. All ATmega8515 I/Os and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 $1F are directly bit-accessible using th e SBI and CBI instructions. I n these registers, t he value of single bit s can be checked by u sing the SB IS a nd SBIC instructions. R efer to the instruction set sect ion for more details. Wh en using the I/O spec ific commands I N and OUT, the I/O addresse s $00 - $3F must be used. When addr essing I /O Regist ers as data space using LD and ST instructions, $20 must be added to th ese addresses.

For compatibility wit h future devices, reserved bits should be writ ten to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writi ng a logical one to them. Note that the CBI and SBI instructions will operate on all bits in the I/O Register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work with registers $00 to $1F only.

The I/O and Peripherals Control Registers are explained in later sections.

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External Memory Interface

Overview When the eXternal MEMory (XMEM) is enabled, address space outside the internal

With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as external SRAM and Flash, and peri pherals such as LCD-display, A/D, and D/A. The main features are:

Four Different Wait State Settings (Including No wait State)

•

• Independent Wait State Setting for Different External Memory Sectors (Configurable

Sector Size)

• The Number of Bits Dedicated to Address High Byte is Selectable

• Bus Keepers on Data Lines to Minimize Current Consumption (Optional)

SRAM becomes availab le us ing the de dicated exte rnal mem ory pi ns (see Figure 1 o n page 2, Table 26 on page 65, Table 32 on page 69, and Table 38 on page 73). The memory configuration is shown in Figure 11.

Figure 11. External Memory with Sector Select

0x0000

Internal Memory

0x25F 0x260

Lower Sector

Using the External Memory Interface

SRW01 SRW00

External Memory

(0-64K x 8)

The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus

• A15:8: High-order address bus (configurable number of bits)

• ALE: Address latch enable

•RD

•WR

: Read strobe

: Write strobe

Upper Sector

SRW11 SRW10

0xFFFF

SRL[2..0]

ATmega8515(L)

2512F–AVR–12/03

ATmega8515(L)

The control bits for the External Memory Interface are located in three registers, the MCU Control Register – MCUCR, the Extended MCU Control Register – EMCUCR, and the Special Function IO Register – SFIOR.

When the XMEM interface is enabled, it will override the settings in the data direction registers corr esponding to the po rt s dedicat ed to t he i nterfa ce. For de tail s about t his port override, see the alternate functions in section “I/O Ports” on page 58. The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, da ta, and the control signals on the ports according to Figure 13 (this figure shows the wave forms without wait states). When ALE goes from high to low, there is a valid address on AD7:0. ALE is low during a data transfer. When the XM EM interface is enabled, also an internal access will cause activity on address-, data-, and ALE ports, but the RD internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 12 illustrat es how to conn ect an ext ern al SRAM to th e AVR using an oc tal latch (typically “74x573” or equivalent) which is transparent when G is high.

Address Latch Requirements Due to the high-speed operation o f the XR AM interfac e, the address latch mus t be

selected with care for syste m frequencies abo ve 8 MHz @ 4V and 4 MHz @ 2.7V. When operating a t conditions above t hese frequencies, the typical old style 74HC series latch becomes inadequate. The external memory interface is designed in compliance to the 74AHC series l atch. How ever, m ost latch es can b e used a s long they com ply w ith the main timing parameters. The main para meters for the address latch are:

• D to Q propagation delay (t

• Data setup time before G low (t

• Data (address) hold time after G low ( The external memory interface is desi gned to guaran ty minimum address hol d time afte r

G is asserted low of t

202). The D to Q propagation delay (t ing the access time requirement of the external component. The data setup time before G low (t (dependent on the capacitive load).

) must not exceed address valid to ALE low (t

= 5 ns (refer to t

)

LAXX_LD/tLLAXX_ST

) must be taken into considera tion when cal culat -

and WR strobes will not toggle during

)

in Table 98 to Table 105 on page

) minus PCB wiring delay

AVLLC

2512F–AVR–12/03

Figure 12. External SRAM Connected to the AVR

AD7:0

ALE

DQ G

AVR

A15:8

D[7:0]

A[7:0]

SRAM

A[15:8] RD

Pull-up and Bus Keeper The pull-up resistors on the AD7:0 ports may be activated if the corresponding Port

Register is written to one. To reduce power consumption in sleep mode, it is recommended to disa ble the p ull-ups by writing the P ort Registe r to zero bef ore entering sleep.

The XMEM interfa ce als o provi des a b us keep er on th e AD7: 0 lines . The b us keep er can be disabled and enabl ed in soft ware as desc ribed i n “Speci al Funct ion IO Regi ster – SFIOR” on page 30. When enabled, the bus keeper will keep the previous value on the AD7:0 bus while these lines are tri-stat ed by the XMEM interface.

Timing External memory devices have various timing requirements. To meet these require-

ments, the ATmega8515 XMEM interface provides four different wait states as shown in Table 3. It is imp ortant to conside r the timing specific ation of the ex ternal me mory device before selecting the wait state. The most impo rtant parame ters are the access time for the external memory in conjunction with the set-up requirement of the ATmega8515. The a ccess time for the e xternal me mory is def ined to be the tim e from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time fr om the AL E pulse is asserted low until data must be stab le during a read se quence (t

LLRL

+ t

RLRH

- t

in Tabl e 98 to T able

DVRH

105 on page 202). The different wait states are set up in software. As an additional feature, it is possible to divi de the exte rnal memory spac e in two sector s with ind ividual wai t state settings. This makes it possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Figure 89 to Fig ure 92, and Table 98 to Table 105.

Note that the XMEM interface is asynchronous and that the waveforms in the figures below are related to the i ntern al syst em cloc k. The skew bet ween the I nternal and Exter nal clock (XTAL1) is not gu aranteed ( it var ies bet ween devices , temperat ure, and supply voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Figure 13. External Data Memory Cycles without Wait State (SRWn1 = 0 and SRWn0 = 0)

System Clock (CLK

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

(1)

CPU

ALE

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

T1 T2 T3

)

AddressPrev. Addr.

Address DataPrev. Data XX

DataPrev. Data Address

sector) or SRW00 (lower sector) The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

Write

Read

ATmega8515(L)

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ATmega8515(L)

Figure 14. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1

System Clock (CLK

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

CPU

ALE

A15:8

DA7:0

T1 T2 T3

)

AddressPrev. Addr.

Address DataPrev. Data XX

DataPrev. Data Address

(1)

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector) The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).

Figure 15. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0

System Clock (CLK

CPU

T1 T2 T3

)

T4 T5

(1)

Write

Read

ALE

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

Address DataPrev. Data XX

AddressPrev. Addr.

DataPrev. Data Address

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector) The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).

Write

Read

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Figure 16. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1

System Clock (CLK

CPU

)

T1 T2 T3

ALE

T4 T5 T6

(1)

XMEM Register Description

MCU Control Register – MCUCR

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

Address DataPrev. Data XX

AddressPrev. Addr.

DataPrev. Data Address

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper

sector) or SRW00 (lower sector) The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).

Bit 76543210

SRE SRW10

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

SE SM1 ISC11 ISC10 ISC01 ISC00 MCUCR

• Bit 7 – SRE: Exte r n a l S R A M /XMEM Enable

Write

Read

Extended MCU Control Register – EMCUCR

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR

, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective Data Direction Registers. Writing SRE to zero, disables the Ext ernal Me mo ry Interfac e and th e n ormal pin a nd data di rection settings are used.

• Bit 6 – SRW10: Wait State Select Bit

For a detailed description, see common description for the SRWn bits below (EMCUCR description).

Bit 76543210

SM0 SRL2SRL1SRL0SRW01SRW00SRW11ISC2 EMCUCR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 6..4 – SRL2, SRL1, SRL0: Wait State Sector Limit

It is possible to configure different wait states for different external memory addresses. The External Memory address space can be di vided in two sectors that have sepa rate wait state bits. The SRL2, SRL1, and SRL0 bits select the spl itting of these sectors, see Table 2 and Figure 11. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire External Memory address space is treated as one sector. When the entire

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ATmega8515(L)

SRAM address space is configured as one sector, the wait states are configured by the SRW11 and SRW10 bits.

Table 2. Sector Limits with Different Settings of SRL2..0

SRL2 SRL1 SRL0 Sector Limits

000

001

010

011

100

101

110

111

Lower sector = N/A Upper sector = 0x0260 - 0xFFFF

Lower sector = 0x0260 - 0x1FFF Upper sector = 0x2000 - 0xFFFF

Lower sector = 0x0260 - 0x3FFF Upper sector = 0x4000 - 0xFFFF

Lower sector = 0x0260 - 0x5FFF Upper sector = 0x6000 - 0xFFFF

Lower sector = 0x0260 - 0x7FFF Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x0260 - 0x9FFF Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x0260 - 0xBFFF Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x0260 - 0xDFFF Upper sector = 0xE000 - 0xFFFF

• Bit 1 and Bit 6 MCUCR – SRW11, SRW10: Wait State Select Bits for Upper

Sector

The SRW11 and SRW1 0 bits control th e numb er of wait states for the upper se ctor of the External Memory address space, see Table 3.

• Bit 3..2 – SRW01, SRW00: Wait State Select Bits for Lower Sector

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The SRW01 and SR W00 bits cont rol the number of wait states for the lower secto r of the External Memory address space, see Table 3.

Table 3. Wait States

SRWn1 SRWn0 Wait States

0 0 No wait states. 0 1 Wait one cycle during read/write strobe. 1 0 Wait two cycles during read/write strobe.

Note: 1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait states of the External Memory Interface, see Figure 13 to Figure 16 how the setting of the SRW bits affects the timing.

(1)

Wait two cycles during read/write and wait one cycle before driving out new address.

Special Function IO Register – SFIOR

Bit 76543210

– XMBK XMM2 XMM1 XMM0 PUD – PSR10 SFIOR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 6 – XMBK: External Memory Bus Keeper Enable

Writing XMBK to one enables the Bus Keeper on the AD7:0 line s. When the Bus Keeper is enabled, AD7:0 will keep the last driven val ue on the lines even if the XMEM interface has tri-stated the lines. Writing XMBK to zero disables the Bus Keeper. XMBK is not qualified with SRE, so even if the XMEM interface is disabled, the Bus Keepers are still activated as long as XMBK is one.

• Bit 5..3 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are used for the high address byte by default. If the full 64,928 bytes address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 4. As described in “Using all 64KB Locations of External Memory” on page 32, it is possible to use t he XMMn bits to acc ess all 64 KB locati ons of the Exter nal Memory.

Table 4. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2 X MM1 XMM0 # Bits for External Memory Address Released Port Pins

Using all Locations of External Memory Small er than 64 KB

0 0 0 8 (Full 64,928 Bytes Space) None 0017 PC7 0106 PC7 - PC6 0115 PC7 - PC5 1004 PC7 - PC4 1013 PC7 - PC3 1102 PC7 - PC2 1 1 1 No Address High bits Full Port C

Since the external memory is mapped after the internal memory as shown in Figure 11, the external me mory is not addre ssed when ad dressing the fir st 608 bytes of d ata space. It m ay appe ar that t he firs t 608 byte s of the ext erna l me mory are ina ccess ible (external memory addresses 0x0000 to 0x025F). Ho wever, whe n connecting an external memory smaller than 64 KB, for exampl e 32 KB, these lo cations are easily acces sed simply by address ing from addres s 0x8000 to 0x8 25F. Since the External Memory Address bit A15 is not connected to the external memory, addresses 0x8000 to 0x825F will appear as addresses 0x0000 to 0x025F for the external memory. Addressing above address 0x825F is not recommended, since this will address an external memory location that is already accessed by anoth er (lower) address. To the Ap plication softw are, the external 32 KB memory will appear as one linear 32 KB address space from 0x0260 to 0x825F. This is illustrat ed in Fi gure 17.

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