ATMEL ATmega644, ATmega644V User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 131 Powe rful Instructions – Most Single-c lo ck Cycle Execut ion – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz

• High Endurance Non-volatile Memory segments

– 64K Bytes of In-System Self-programmable Flash program memory – 2K Bytes EEPROM – 4K Bytes Internal SRAM – Write/Erase cyles: 10,000 Flash/100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x – Byte-oriented Two-wire Serial Interface – One Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Pr ogrammab l e Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby

and Extended Standby

• I/O and Pac kages

– 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Speed Grades

– ATmega644V: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V – ATmega644: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1 MHz, 3V, 25°C for

– Active: 240 µA @ 1.8V, 1MHz – Power-down Mode: 0.1 µA @ 1.8V

8-bit Microcontroller

(1)(3)

(2)(3)

8-bit

Microcontroller with 64K Bytes In-System Programmable Flash

ATmega644/V

Preliminary

Summary

Notes: 1. Worst case temperature. Guaranteed after last write cycle.

2. Failure rate less than 1 ppm.

3. Characterized through accelerated tests.

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ATmega644

1. Pin Configurations

Figure 1-1. Pinout ATmega644

PDIP

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/INT0) PD2

(PCINT27/INT1) PD3 (PCINT28/OC1B) PD4 (PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVC C PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31)

TQFP/QFN/MLF

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/INT0) PD2

VCC

GND

(PCINT27/INT1) PD3

(PCINT28/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT31/OC2A) PD7

(PCINT30/OC2B/ICP) PD6

(PCINT16/SCL) PC0

(PCINT18/TCK) PC2

(PCINT17/SDA) PC1

PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20)

(PCINT19/TMS) PC3

Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the

board to ensure good mechanical stability.

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1.1 Disclaimer

PC7..0

PA7..0

PB7..0

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured o n th e same proce ss te ch nolo gy. Min a nd Ma x valu es will be available after the device is characterized.

2. Overview

The ATmega644 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmeg a644 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

VCC

ATmega644

RESET

XTAL1

GND

XTAL2

Power

Supervision

POR / BOD &

RESET

Watchdog

Timer

Watchdog

Oscillator

Circuits /

Clock

Generation

PORT A (8)

A/D

Converter

EEPROM

JTAG

TWI

Internal

Bandgap reference

CPU

SRAMFLASH

PORT B (8)

Analog

Comparator

SPI

16bit T/C 1

8bit T/C 0

8bit T/C 2

USART 0

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PORT C (8)

PORT D (8)

PD7..0

ATmega644

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The ATmega644 provides the following features: 64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K bytes EEPROM, 4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscilla tor, an SPI serial port, IEEE std. 1149. 1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU wh ile allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modu les except Asynchr onous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega644 is a powerful microcontroller that pro vides a highly flexible and co st effective solution to many embedded control applications.

The ATmega644 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Conver ter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

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and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-st ated when a reset co ndition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega644 as listed on page

73.

2.2.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega644 as listed on page

75.

2.2.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

ATmega644

Port C also serves the functions of the JTAG interface, along with special features of the ATmega644 as listed on page 78.

2.2.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega644 as listed on page

80.

2.2.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 320. Shorter pulses are not guaranteed to generate a reset.

2.2.8 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.9 XTAL2

Output from the inverting Oscillator amplifier.

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ATmega644

2.2.10 AVCC

2.2.11 AREF

3. Resources

AVCC is the supply voltage pin for Port F and the Analog-to-digital Convert er. It should be exte rnally connected to V to V

through a low-pass filter.

This is the analog reference pin for the Analog-to-digital Converter.

A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.

, even if the ADC is not used. If the ADC is used, it should be connected

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ATmega644

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - (0xFE) Reserved - - - - - - - (0xFD) Reserved - - - - - - - (0xFC) Reserved - - - - - - - (0xFB) Reserved - - - - - - (0xFA) Reserved - - - - - - - (0xF9) Reserved - - - - - - (0xF8) Reserved - - - - - - - (0xF7) Reserved - - - - - - - (0xF6) Reserved - - - - - - - (0xF5) Reserved - - - - - - (0xF4) Reserved - - - - - - - (0xF3) Reserved - - - - - - - (0xF2) Reserved - - - - - - - (0xF1) Reserved (0xF0) Reserved (0xEF) Reserved - - - - - - -

(0xEE) Reserved (0xED) Reserved (0xEC) Reserved - - - - - - - (0xEB) Reserved - - - - - - (0xEA) Reserved - - - - - - - (0xE9) Reserved - - - - - - - (0xE8) Reserved - - - - - - - (0xE7) Reserved - - - - - - (0xE6) Reserved - - - - - - - (0xE5) Reserved - - - - - - - (0xE4) Reserved - - - - - - - (0xE3) Reserved - - - - - - (0xE2) Reserved - - - - - - - (0xE1) Reserved - - - - - - (0xE0) Reserved - - - - - - (0xDF) Reserved - - - - - - - (0xDE) Reserved - - - - - - - (0xDD) Reserved - - - - - - - (0xDC) Reserved - - - - - - (0xDB) Reserved - - - - - - - (0xDA) Reserved - - - - - - - (0xD9) Reserved - - - - - - - (0xD8) Reserved - - - - - - - (0xD7) Reserved - - - - - - - (0xD6) Reserved (0xD5) Reserved (0xD4) Reserved - - - - - - - (0xD3) Reserved (0xD2) Reserved (0xD1) Reserved (0xD0) Reserved - - - - - - - (0xCF) Reserved (0xCE) Reserved (0xCD) Reserved - - - - - - - (0xCC) Reserved (0xCB) Reserved (0xCA) Reserved - - - - - - - (0xC9) Reserved (0xC8) Reserved (0xC7) Reserved - - - - - - - (0xC6) UDR0 USART0 I/O Data Register 182 (0xC5) UBRR0H (0xC4) UBRR0L USART0 Baud Rate Register Low Byte 186/198 (0xC3) Reserved - - - - - - - (0xC2) UCSR0C UMSEL01 UMSEL00 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 184/197 (0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 183/197 (0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 182/196

- - - - - - -

- - - - - - - -

- - - - USART0 Baud Rate Register High Byte 186/198

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