ATMEL AT MEGA 325 P V Service Manual

www.DataSheet4U.com

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20 MHz
– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles

32K bytes

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

– EEPROM, Endurance: 100,000 Write/Erase Cycles

1K bytes

– Internal SRAM

2K bytes

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 54/69 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega325PV/ATmega3250PV:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega325P/3250P:

0 - 10 MHz @ 2.7 - 5.5V, 0 - 10 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

420µA at 1 MHz, 1.8V

– Power-down Mode:

40 nA at 1.8V

– Power-save Mode:

750 nA at 1.8V

®

8-Bit Microcontroller

8-bit

Microcontroller
with 32K Bytes
In-System
Programmable
Flash

ATmega325P/V
ATmega3250P/V

Preliminary
Summary

8023AS–AVR–12/06

1. Pin Configurations

Figure 1-1. Pinout ATmega3250P

(RXD/PCINT0) PE0

DNC

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24) PJ0

(PCINT25) PJ1

DNC

DNC

DNC

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

DNC

PH7 (PCINT23)

PH6 (PCINT22)

PH5 (PCINT21)

PH4 (PCINT20)

DNC

DNC

GND

9998979695949392919089888786858483828180797877

100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26272829303132333435363738394041424344454647484950

(OC2A/PCINT15) PB7

DNC

INDEX CORNER

(T1) PG3

(T0) PG4

VCC

RESET/PG5

GND

(TOSC2) XTAL2

DNC

(TOSC1) XTAL1

ATm ega3250

DNC

(PCINT26) PJ2

(PCINT27) PJ3

(PCINT28) PJ4

DNC

(PCINT29) PJ5

(PCINT30) PJ6

(INT0) PD1

(ICP1) PD0

PD2

VCC

PD3

DNC

PD4

PA0

PD5

PA1

PD6

PA2

76

PD7

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PA3

PA4

PA5

PA6

PA7

PG2

PC7

PC6

DNC

PH3 (PCINT19)

PH2 (PCINT18)

PH1 (PCINT17)

PH0 (PCINT16)

DNC

DNC

DNC

DNC

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

2

ATmega325P/3250P

8023AS–AVR–12/06

Figure 1-2. Pinout ATmega325P

GND

AVCC

64

63

DNC

1

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

PF0 (ADC0)

PF1 (ADC1)

AREF

61

6018592058

62

INDEX CORNER

19

21

ATmega325P/3250P

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

57225623552454255326522751

ATmega325

GND

PF7 (ADC7/TDI)

PF6 (ADC6/TDO)

28

VCC

29

PA 0

PA 1

PA 2

50

49

PA 3

48

PA 4

47

PA 5

46

PA 6

45

PA 7

44

43

PG2

42

PC7

41

PC6

40

PC5

PC4

39

PC3

38

PC2

37

PC1

36

PC0

35

34

PG1

33

PG0

32

31

30

(T1) PG3

(T0) PG4

RESET/PG5

(OC2A/PCINT15) PB7

VCC

GND

(TOSC2) XTAL2

(TOSC1) XTAL1

(INT0) PD1

(ICP1) PD0

PD2

PD3

PD4

PD5

PD6

PD7

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.

1.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.

2. Overview

The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By
executing powerful instructions in a single clock cycle, the ATmega325P/3250P achieves throughputs approaching 1 MIPS
per MHz allowing the system designer to optimize power consumption versus processing speed.

8023AS–AVR–12/06

3

2.1 Block Diagram

Figure 2-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

AVR CPU

PORTF DRIVERS

ADC

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

REGISTER

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

XTAL1

XTAL2

RESET

4

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

+

COMPARATOR

USART

DATA REGISTER

PORTE

-

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

ATmega325P/3250P

DATA REGISTER

PORTB

PORTB DRIVERS

SPI

DATA DIR.

REG. PORTB

PB0 - PB7PE0 - PE7

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

8023AS–AVR–12/06

ATmega325P/3250P

The ATmega325P/3250P provides the following features: 32K bytes of In-System Programma­ble Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general
purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan,
On-chip Debugging support and programming, three flexible Timer/Counters with compare
modes, internal and external interrupts, a serial programmable USART, Universal Serial Inter­face with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer
with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The
Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt sys­tem to continue functioning. The Power-down mode saves the register contents but freezes the
Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power­save mode, the asynchronous timer, allowing the user to maintain a timer base while the rest of
the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules
except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping.
This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip In-System re-Programmable (ISP) Flash allows the program memory to be repro­grammed In-System through an SPI serial interface, by a conventional non-volatile memory
programmer, or by an On-chip Boot program running on the AVR core. The Boot program can
use any interface to download the application program in the Application Flash memory. Soft­ware in the Boot Flash section will continue to run while the Application Flash section is updated,
providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega325P/3250P is a powerful
microcontroller that provides a highly flexible and cost effective solution to many embedded con­trol applications.

The ATmega325P/3250P AVR is supported with a full suite of program and system develop­ment tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit
Emulators, and Evaluation kits.

2.2 Comparison between ATmega325P and ATmega3250P

The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. Table

2-1 on page 5 summarizes the different configurations for the four devices.

Table 2-1. Configuration Summary

Device Flash EEPROM RAM

ATmega325P 32K bytes 1K bytes 2K bytes 54

ATmega3250P 32K bytes 1K bytes 2K bytes 69

General Purpose
I/O Pins

8023AS–AVR–12/06

5

2.3 Pin Descriptions

The following section describes the I/O-pin special functions.

2.3.1 V

2.3.2 GND

2.3.3 Port A (PA7..PA0)

2.3.4 Port B (PB7..PB0)

CC

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega325P/3250P as listed
on page 72.

2.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

2.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325P/3250P as listed
on page 75.

2.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

6

ATmega325P/3250P

8023AS–AVR–12/06

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port E also serves the functions of various special features of the ATmega325P/3250P as listed
on page 76.

2.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym­metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

ATmega325P/3250P

Port G also serves the functions of various special features of the ATmega325P/3250P as listed
on page 76.

2.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port H output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port H pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250P as listed on

page 76.

2.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port J output buffers have symmetrical drive characteristics with both high sink and source capa­bility. As inputs, Port J pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port J pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250P as listed on

page 76.

8023AS–AVR–12/06

7

2.3.12 RESET

2.3.13 XTAL1

2.3.14 XTAL2

2.3.15 AVCC

2.3.16 AREF

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characterizations” on page 309. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con­nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

CC

through a low-pass filter.

This is the analog reference pin for the A/D Converter.

8

ATmega325P/3250P

8023AS–AVR–12/06