ATMEL AT MEGA 325 P V Service Manual

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Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– In-System Self-Programmable Flash, Endurance: 10,000 Write/Erase Cycles

32K bytes

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– EEPROM, Endurance: 100,000 Write/Erase Cycles

1K bytes

– Internal SRAM

2K bytes

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode – Real Time Counter with Separate Oscillator –Four PWM Channels – 8-channel, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Universal Serial Interface with Start Condition Detector – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 54/69 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF, and 100-lead TQFP

• Speed Grade:

– ATmega325PV/ATmega3250PV:

0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATmega325P/3250P:

0 - 10 MHz @ 2.7 - 5.5V, 0 - 10 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

420µA at 1 MHz, 1.8V

– Power-down Mode:

40 nA at 1.8V

– Power-save Mode:

750 nA at 1.8V

®

8-Bit Microcontroller

8-bit

Microcontroller with 32K Bytes In-System Programmable Flash

ATmega325P/V ATmega3250P/V

Preliminary Summary

8023AS–AVR–12/06

1. Pin Configurations

Figure 1-1. Pinout ATmega3250P

(RXD/PCINT0) PE0

DNC

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

VCC

GND

DNC

(PCINT24) PJ0

(PCINT25) PJ1

DNC

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

TQFP

AVCC

AGND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

PF6 (ADC6/TDO)

PF7 (ADC7/TDI)

DNC

PH7 (PCINT23)

PH6 (PCINT22)

PH5 (PCINT21)

PH4 (PCINT20)

DNC

GND

9998979695949392919089888786858483828180797877

100

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26272829303132333435363738394041424344454647484950

(OC2A/PCINT15) PB7

DNC

INDEX CORNER

(T1) PG3

(T0) PG4

VCC

RESET/PG5

GND

(TOSC2) XTAL2

DNC

(TOSC1) XTAL1

ATm ega3250

DNC

(PCINT26) PJ2

(PCINT27) PJ3

(PCINT28) PJ4

DNC

(PCINT29) PJ5

(PCINT30) PJ6

(INT0) PD1

(ICP1) PD0

PD2

VCC

PD3

DNC

PD4

PA0

PD5

PA1

PD6

PA2

76

PD7

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PA3

PA4

PA5

PA6

PA7

PG2

PC7

PC6

DNC

PH3 (PCINT19)

PH2 (PCINT18)

PH1 (PCINT17)

PH0 (PCINT16)

DNC

PC5

PC4

PC3

PC2

PC1

PC0

PG1

PG0

2

ATmega325P/3250P

8023AS–AVR–12/06

Figure 1-2. Pinout ATmega325P

GND

AVCC

64

63

DNC

1

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

PF0 (ADC0)

PF1 (ADC1)

AREF

61

6018592058

62

INDEX CORNER

19

21

ATmega325P/3250P

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

PF5 (ADC5/TMS)

57225623552454255326522751

ATmega325

GND

PF7 (ADC7/TDI)

PF6 (ADC6/TDO)

28

VCC

29

PA 0

PA 1

PA 2

50

49

PA 3

48

PA 4

47

PA 5

46

PA 6

45

PA 7

44

43

PG2

42

PC7

41

PC6

40

PC5

PC4

39

PC3

38

PC2

37

PC1

36

PC0

35

34

PG1

33

PG0

32

31

30

(T1) PG3

(T0) PG4

RESET/PG5

(OC2A/PCINT15) PB7

VCC

GND

(TOSC2) XTAL2

(TOSC1) XTAL1

(INT0) PD1

(ICP1) PD0

PD2

PD3

PD4

PD5

PD6

PD7

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

1.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2. Overview

The ATmega325P/3250P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega325P/3250P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

8023AS–AVR–12/06

3

2.1 Block Diagram

Figure 2-1. Block Diagram

AVCC

AGND

AREF

PH0 - PH7

PORTH DRIVERS

VCCGND

DATA DIR.

REG. PORTH

PORTH

DATA REGISTER

DATA DIR.

REG. PORTJ

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

AVR CPU

PORTF DRIVERS

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

DATA DIR.

REG. PORTF

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL

PURPOSE

REGISTERS

X

Y

Z

ALU

STATUS

REGISTER

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

REGISTER

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

XTAL1

XTAL2

RESET

4

PJ0 - PJ6

PORTJ DRIVERS

PORTJ

DATA REGISTER

ANALOG

+

COMPARATOR

USART

DATA REGISTER

PORTE

-

UNIVERSAL

SERIAL INTERFACE

REG. PORTE

PORTE DRIVERS

DATA DIR.

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

ATmega325P/3250P

DATA REGISTER

PORTB

PORTB DRIVERS

SPI

DATA DIR.

REG. PORTB

PB0 - PB7PE0 - PE7

DATAREGISTER

PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

REG. PORTD

DATAREG.

PORTG

PORTG DRIVERS

DATA DIR.

REG. PORTG

PG0 - PG4

8023AS–AVR–12/06

ATmega325P/3250P

The ATmega325P/3250P provides the following features: 32K bytes of In-System Programmable Flash with Read-While-Write capabilities, 1K bytes EEPROM, 2K byte SRAM, 54/69 general purpose I/O lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip Debugging support and programming, three flexible Timer/Counters with compare modes, internal and external interrupts, a serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8-channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial port, and five software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Powersave mode, the asynchronous timer, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except asynchronous timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip In-System re-Programmable (ISP) Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the application program in the Application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega325P/3250P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The ATmega325P/3250P AVR is supported with a full suite of program and system development tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

2.2 Comparison between ATmega325P and ATmega3250P

The ATmega325P and ATmega3250P differs only in memory sizes, pin count and pinout. Table

2-1 on page 5 summarizes the different configurations for the four devices.

Table 2-1. Configuration Summary

Device Flash EEPROM RAM

ATmega325P 32K bytes 1K bytes 2K bytes 54

ATmega3250P 32K bytes 1K bytes 2K bytes 69

General Purpose I/O Pins

8023AS–AVR–12/06

5

2.3 Pin Descriptions

The following section describes the I/O-pin special functions.

2.3.1 V

2.3.2 GND

2.3.3 Port A (PA7..PA0)

2.3.4 Port B (PB7..PB0)

CC

Digital supply voltage.

Ground.

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega325P/3250P as listed on page 72.

2.3.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

2.3.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega325P/3250P as listed on page 75.

2.3.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up

6

ATmega325P/3250P

8023AS–AVR–12/06

resistors are activated. The Port E pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the ATmega325P/3250P as listed on page 76.

2.3.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface.

2.3.9 Port G (PG5..PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port G output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

ATmega325P/3250P

Port G also serves the functions of various special features of the ATmega325P/3250P as listed on page 76.

2.3.10 Port H (PH7..PH0)

Port H is a 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port H output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port H pins that are externally pulled low will source current if the pull-up resistors are activated. The Port H pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port H also serves the functions of various special features of the ATmega3250P as listed on

page 76.

2.3.11 Port J (PJ6..PJ0)

Port J is a 7-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port J output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port J pins that are externally pulled low will source current if the pull-up resistors are activated. The Port J pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port J also serves the functions of various special features of the ATmega3250P as listed on

page 76.

8023AS–AVR–12/06

7

2.3.12 RESET

2.3.13 XTAL1

2.3.14 XTAL2

2.3.15 AVCC

2.3.16 AREF

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characterizations” on page 309. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

through a low-pass filter.

This is the analog reference pin for the A/D Converter.

8

ATmega325P/3250P

8023AS–AVR–12/06

3. Resources

ATmega325P/3250P

A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr.

8023AS–AVR–12/06

9

4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is included before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.

10

ATmega325P/3250P

8023AS–AVR–12/06

ATmega325P/3250P

5. Register Summary

Note: Registers with bold type only available in ATmega3250P.

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF)

(0xFE)

(0xFD)

(0xFC)

(0xFB)

(0xFA)

(0xF9)

(0xF8)

(0xF7)

(0xF6)

(0xF5)

(0xF4)

(0xF3)

(0xF2)

(0xF1)

(0xF0)

(0xEF)

(0xEE)

(0xED)

(0xEC)

(0xEB)

(0xEA)

(0xE9)

(0xE8)

(0xE7)

(0xE6)

(0xE5)

(0xE4)

(0xE3)

(0xE2)

(0xE1)

(0xE0)

(0xDF)

(0xDE)

(0xDD)

(0xDC)

(0xDB)

(0xDA)

(0xD9)

(0xD8)

(0xD7)

(0xD6)

(0xD5)

(0xD4)

(0xD3)

(0xD2)

(0xD1)

(0xD0)

(0xCF)

(0xCE)

(0xCD)

(0xCC)

(0xCB)

(0xCA)

(0xC9)

(0xC8)

(0xC7)

(0xC6)

(0xC5)

Reserved

Reserved - - - - - - - -

PORTJ - PORTJ6 PORTJ5 PORTJ4 PORTJ3 PORTJ2 PORTJ1 PORTJ0 89

DDRJ - DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 89

PINJ

PORTH PORTH7 PORTH6 PORTH5 PORTH4 PORTH3 PORTH2 PORTH1 PORTH0 88

DDRH DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 89

PINHPINH7 PINH6 PINH5 PINH4 PINH3 PINH2 PINH1 PINH0 89

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

UDR0 USART0 Data Register 183

UBRR0H

- - - - - - - -

-PINJ6 PINJ5 PINJ4 PINJ3 PINJ2 PINJ1 PINJ0 89

- - - - - - - -

USART0 Baud Rate Register H igh 187

8023AS–AVR–12/06

11

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xC4)

(0xC3)

(0xC2)

(0xC1)

(0xC0)

(0xBF)

(0xBE)

(0xBD)

(0xBC)

(0xBB)

(0xBA)

(0xB9)

(0xB8)

(0xB7)

(0xB6)

(0xB5)

(0xB4)

(0xB3)

(0xB2)

(0xB1)

(0xB0)

(0xAF)

(0xAE)

(0xAD)

(0xAC)

(0xAB)

(0xAA)

(0xA9)

(0xA8)

(0xA7)

(0xA6)

(0xA5)

(0xA4)

(0xA3)

(0xA2)

(0xA1)

(0xA0)

(0x9F)

(0x9E)

(0x9D)

(0x9C)

(0x9B)

(0x9A)

(0x99)

(0x98)

(0x97)

(0x96)

(0x95)

(0x94)

(0x93)

(0x92)

(0x91)

(0x90)

(0x8F)

(0x8E)

(0x8D)

(0x8C)

(0x8B)

(0x8A)

(0x89)

(0x88)

(0x87)

(0x86)

UBRR0L USART0 Baud Rate Register Low 187

Reserved - - - - - - - -

UCSR0C - UMSEL0 UPM01 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 185

UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0TXEN0 UCSZ02 RXB80 TXB80 184

UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 183

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

USIDR USI Data Register 200

USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 200

USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 201

Reserved - - - - - - - -

ASSR - - - EXCLK AS2 TCN2UB OCR2UB TCR2UB 152

Reserved - - - - - - - -

OCR2A Timer/Counter 2 Output Compare Register A 152

TCNT2 Timer/Counter2 152

Reserved - - - - - - - -

TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 150

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

Reserved - - - - - - - -

Reserved

OCR1BH Timer/Counter1 Output Compare Register B High 133

OCR1BL Timer/Counter1 Output Compare Register B Low 133

OCR1AH Timer/Counter1 Output Compare Register A High 133

OCR1AL Timer/Counter1 Output Compare Register A Low 133

ICR1H Timer/Counter1 Input Capture Register High 134

ICR1L Timer/Counter1 Input Capture Register Low 134

- - - - - - - -

12

ATmega325P/3250P

8023AS–AVR–12/06

ATmega325P/3250P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0x85)

(0x84)

(0x83)

(0x82)

(0x81)

(0x80)

(0x7F)

(0x7E)

(0x7D)

(0x7C)

(0x7B)

(0x7A)

(0x79)

(0x78)

(0x77)

(0x76)

(0x75)

(0x74)

(0x73)

(0x72)

(0x71)

(0x70)

(0x6F)

(0x6E)

(0x6D)

(0x6C)

(0x6B)

(0x6A)

(0x69)

(0x68)

(0x67)

(0x66)

(0x65)

(0x64)

(0x63)

(0x62)

(0x61)

(0x60)

0x3F (0x5F)

0x3E (0x5E)

0x3D (0x5D)

0x3C (0x5C)

0x3B (0x5B)

0x3A (0x5A)

0x39 (0x59)

0x38 (0x58)

0x37 (0x57)

0x36 (0x56)

0x35 (0x55)

0x34 (0x54)

0x33 (0x53)

0x32 (0x52)

0x31 (0x51)

0x30 (0x50)

0x2F (0x4F)

0x2E (0x4E)

0x2D (0x4D)

0x2C (0x4C)

0x2B (0x4B)

0x2A (0x4A)

0x29 (0x49)

0x28 (0x48)

0x27 (0x47)

TCNT1H Timer/Counter1 High 133

TCNT1L Timer/Counter1 Low 133

Reserved - - - - - - - -

TCCR1C FOC1A FOC1B - - - - - -132

TCCR1B ICNC1 ICES1 - WGM13WGM12CS12CS11CS10 131

TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 - -WGM11WGM10129

DIDR1

DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 223

Reserved

ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 219

ADCSRB -ACME- - - ADTS2 ADTS1 ADTS0 205/223

ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 221

ADCH ADC Data Register High 222

ADCL ADC Data Register Low 222

Reserved - - - - - - - -

PCMSK3 -PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 63

Reserved - - - - - - - -

TIMSK2 - - - - - - OCIE2A TOIE2 153

TIMSK1 - -ICIE1- - OCIE1B OCIE1A TOIE1 134

TIMSK0 - - - - - - OCIE0A TOIE0 105

PCMSK2 PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 63

PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 63

PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 63

Reserved - - - - - - - -

EICRA - - - - - -ISC01ISC0060

Reserved - - - - - - - -

OSCCAL Oscillator Calibration Register [CAL7..0] 36

Reserved - - - - - - - -

PRR - - - - PRTIM1 PRSPI PSUSART0 PRADC 45

Reserved - - - - - - - -

CLKPR CLKPCE - - - CLKPS3 CLKPS2 CLKPS1 CLKPS0 37

WDTCR - - - WDCE WDE WDP2 WDP1 WDP0 52

SREG I T H S V N ZC13

SPH Stack Pointer High 15

SPL Stack Pointer Low 15

Reserved

Reserved - - - - - - - -

Reserved

SPMCSR SPMIE RWWSB

Reserved

MCUCR JTD BODS BODSE PUD

MCUSR

SMCR - - - - SM2 SM1 SM0 SE 44

Reserved

OCDR IDRD/OCDR7 OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 229

ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 205

Reserved - - - - - - - -

SPDR SPI Data Register 163

SPSR SPIF WCOL

SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 161

GPIOR2 General Purpose I/O Register 27

GPIOR1 General Purpose I/O Register 27

Reserved - - - - - - - -

Reserved

OCR0A Timer/Counter0 Output Compare A 105

- - - - - -AIN1D AIN0D 206

- - - - - - - -

- RWWSRE BLBSET PGWRT PGERS SPMEN 270

- - IVSEL IVCE 57/86/256

- - - JTRF WDRF BORF EXTRF PORF 51

- - - - - - - -

- - - - - SPI2X 163

- - - - - - - -

8023AS–AVR–12/06

13

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x26 (0x46)

0x25 (0x45)

0x24 (0x44)

0x23 (0x43)

0x22 (0x42)

0x21 (0x41)

0x20 (0x40)

0x1F (0x3F)

0x1E (0x3E)

0x1D (0x3D)

0x1C (0x3C)

0x1B (0x3B)

0x1A (0x3A)

0x19 (0x39)

0x18 (0x38)

0x17 (0x37)

0x16 (0x36)

0x15 (0x35)

0x14 (0x34)

0x13 (0x33)

0x12 (0x32)

0x11 (0x31)

0x10 (0x30)

0x0F (0x2F)

0x0E (0x2E)

0x0D (0x2D)

0x0C (0x2C)

0x0B (0x2B)

0x0A (0x2A)

0x09 (0x29)

0x08 (0x28)

0x07 (0x27)

0x06 (0x26)

0x05 (0x25)

0x04 (0x24)

0x03 (0x23)

0x02 (0x22)

0x01 (0x21)

0x00 (0x20)

TCNT0 Timer/Counter0 105

Reserved - - - - - - - -

TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 103

GTCCR TSM - - - - - PSR2 PSR10 106/154

EEARH - - - - - EEPROM Address Register High 23

EEARL EEPROM Address Register Low 23

EEDR EEPROM Data Register 23

EECR - - - - EERIE EEMWE EEWE EERE 24

GPIOR0 General Purpose I/O Register 28

EIMSK PCIE3 PCIE2 PCIE1 PCIE0 - - -INT0 61

EIFR PCIF3 PCIF2 PCIF1 PCIF0 - - -INTF0 62

Reserved - - - - - - - -

TIFR2 - - - - - -OCF2ATOV2154

TIFR1 - -ICF1- -OCF1BOCF1ATOV1134

TIFR0 - - - - - -OCF0ATOV0106

PORTG - - - PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 88

DDRG - - - DDG4 DDG3 DDG2 DDG1 DDG0 88

PING - -PIN G5 PING4 PING3 PING2 PING1 PING0 88

PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 88

DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 88

PINFPINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 88

PORTE PORTE7 PORTE6 PORTE5 PORTE4 PORTE3 PORTE2 PORTE1 PORTE0 87

DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 87

PINEPINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 88

PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 87

DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 87

PINDPIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 87

PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 87

DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 87

PINCPINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 87

PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 86

DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 86

PINBPINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 86

P OR TA P O RTA 7 P OR TA 6 PO RTA 5 P OR TA 4 PO R TA3 P O RTA 2 PO R TA 1 PO RTA 0 8 6

DDR A DDA7 DDA6 DDA5 D DA4 DDA3 DDA 2 DDA1 DDA0 86

PINAPINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 86

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega325P/3250P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

14

ATmega325P/3250P

8023AS–AVR–12/06

ATmega325P/3250P

6. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • KZ,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2 FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2 FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← k None 3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← Z None 3

CALL k Direct Subroutine Call PC ← k None 4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if N

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

ot Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

8023AS–AVR–12/06

15

Mnemonics Operands Description Operation Flags #Clocks

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← T None 1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1 N 1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1 CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word

LDI Rd, K Load Immediate Rd ← K None 1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 N one 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← P None 1

OUT P, Rr Out Port P ← Rr None 1

Rd+1:Rd ← Rr+1:Rr

None 1

16

ATmega325P/3250P

8023AS–AVR–12/06

ATmega325P/3250P

Mnemonics Operands Description Operation Flags #Clocks

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1 BREAK Break For On-chip Debug Only None N/A

8023AS–AVR–12/06

17

7. Ordering Information

7.1 ATmega325P

Speed (MHz)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

3. For Speed vs. V

(3)

10 1.8 - 5.5V

20 2.7 - 5.5V

and minimum quantities.

Halide free and fully Green.

Power Supply Ordering Code

see Figure 25-1 on page 307 and Figure 25-2 on page 307.

CC

ATmega325PV-10AU

ATmega325PV-10MU

ATmega325P-20AU

ATmega325P-20MU

(2)

Package Type

64A

64M1

64A

64M1

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

(-4

0°C to 85°C)

Package Type

64A 64-lead, 14 x 14 x 1.0 mm, Thin Profile Plastic Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

18

ATmega325P/3250P

8023AS–AVR–12/06

ATmega325P/3250P

7.2 ATmega3250P

Speed (MHz)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

3. For Speed vs. V

(3)

10 1.8 - 5.5V ATmega3250PV-10AU 100A

20 2.7 - 5.5V ATmega3250P-20AU 100A

and minimum quantities.

Halide free and fully Green.

Power Supply Ordering Code

see Figure 25-1 on page 307 and Figure 25-2 on page 307.

CC

(2)

Package Type

(1)

Operational Range

Industrial

0°C to 85°C)

(-4

Industrial

(-4

0°C to 85°C)

Package Type

100A 100-lead, 14 x 14 x 1.0 mm, 0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

8023AS–AVR–12/06

19

8. Packaging Information

8.1 64A

PIN 1

PIN 1 IDENTIFIER

B

e

E1 E

D1

D

C

0˚~7˚

A1

L

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

20

2325 Orchard Parkway

R

San Jose, CA 95131

TITLE

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

ATmega325P/3250P

10/5/2001

DRAWING NO.

64A

8023AS–AVR–12/06

REV.

B

8.2 64M1

D

Marked Pin# 1 ID

ATmega325P/3250P

E

SEATING PLANE

C

TOP VIEW

A1

A

K

L

D2

E2

K

b

e

BOTTOM VIEW

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

Note:

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Pin #1 Corner

1 2 3

Option A

Option B

Option C

Pin #1 Triangle

Pin #1 Chamfer (C 0.30)

Pin #1 Notch (0.20 R)

SIDE VIEW

SYMBOL

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D

D2 5.20 5.40 5.60

E

E2 5.20 5.40 5.60

e 0.50 BSC

L 0.35 0.40 0.45

K 1.25 1.40 1.55

0.08

C

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

8.90 9.00 9.10

NOM

MAX

NOTE

R

8023AS–AVR–12/06

2325 Orchard Parkway San Jose, CA 95131

TITLE

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.

64M1

5/25/06

REV.

G

21

8.3 100A

PIN 1

B

PIN 1 IDENTIFIER

e

E1 E

D1

D

C

0˚~7˚

A1

L

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AED.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.08 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.17 – 0.27

C 0.09 – 0.20

L 0.45 – 0.75

e 0.50 TYP

NOM

MAX

NOTE

22

2325 Orchard Parkway

R

San Jose, CA 95131

TITLE

100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

ATmega325P/3250P

10/5/2001

DRAWING NO.

100A

8023AS–AVR–12/06

REV.

C

9. Errata

9.1 ATmega325P rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer.

1. Interrupts may be lost when writing the timer registers in the asynchronous timer.

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workoround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

9.2 ATmega3250P rev. A

• Interrupts may be lost when writing the timer registers in the asynchronous timer.

1. Interrupts may be lost when writing the timer registers in the asynchronous timer.

If one of the timer registers which is synchronized to the asynchronous timer2 clock is written in the cycle before a overflow interrupt occurs, the interrupt may be lost.

Problem Fix/Workoround

Always check that the Timer2 Timer/Counter register, TCNT2, does not have the value 0xFF before writing the Timer2 Control Register, TCCR2, or Output Compare Register, OCR2.

ATmega325P/3250P

8023AS–AVR–12/06

23

10. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document.The referring revision in this section are referring to the document revision.

10.1 Rev.8023A – 12/06

1. Initial version.

24

ATmega325P/3250P

8023AS–AVR–12/06

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8023AS–AVR–12/06

ATMEL AT MEGA 325 P V Service Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Disclaimer

2. Overview

2.1 Block Diagram

2.2 Comparison between ATmega325P and ATmega3250P

2.3 Pin Descriptions

2.3.2 GND

2.3.3 Port A (PA7..PA0)

2.3.4 Port B (PB7..PB0)

2.3.5 Port C (PC7..PC0)

2.3.6 Port D (PD7..PD0)

2.3.7 Port E (PE7..PE0)

2.3.8 Port F (PF7..PF0)

2.3.9 Port G (PG5..PG0)

2.3.10 Port H (PH7..PH0)

2.3.11 Port J (PJ6..PJ0)

2.3.12 RESET

2.3.13 XTAL1

2.3.14 XTAL2

2.3.15 AVCC

2.3.16 AREF

3. Resources

4. About Code Examples

5. Register Summary

6. Instruction Set Summary

7. Ordering Information

7.1 ATmega325P

7.2 ATmega3250P

8. Packaging Information

8.1 64A

8.2 64M1

8.3 100A

9. Errata

9.1 ATmega325P rev. A

9.2 ATmega3250P rev. A

10. Datasheet Revision History