– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories
– 16K bytes of In-System Self-Programmable Flash
Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– 4 x 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169P
ATmega169PV
Preliminary
Summary
8018IS-AVR-11/06
1.Pin Configurations
Figure 1-1.Pinout ATmega169P
LCDCAP
(RXD/PCINT0) PE0
(TXD/PCINT1) PE1
(XCK/AIN0/PCINT2) PE2
(AIN1/PCINT3) PE3
(USCK/SCL/PCINT4) PE4
(DI/SDA/PCINT5) PE5
(DO/PCINT6) PE6
(CLKO/PCINT7) PE7
(SS/PCINT8) PB0
(SCK/PCINT9) PB1
(MOSI/PCINT10) PB2
(MISO/PCINT11) PB3
(OC0A/PCINT12) PB4
(OC1A/PCINT13) PB5
(OC1B/PCINT14) PB6
VCC
PF0 (ADC0)
PF1 (ADC1)
PF2 (ADC2)
PF3 (ADC3)
PF4 (ADC4/TCK)
AREF
GND
AVCC
61
64
63
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
INDEX CORNER
17
6018592058
62
19
21
PF5 (ADC5/TMS)
57225623552454255326522751
GND
PF7 (ADC7/TDI)
PF6 (ADC6/TDO)
28
29
PA0 (COM0)
PA1 (COM1)
50
31
30
PA2 (COM2)
49
PA3 (COM3)
48
PA4 (SEG0)
47
PA5 (SEG1)
46
PA6 (SEG2)
45
PA7 (SEG3)
44
43
PG2 (SEG4)
42
PC7 (SEG5)
41
PC6 (SEG6)
40
PC5 (SEG7)
PC4 (SEG8)
39
PC3 (SEG9)
38
PC2 (SEG10)
37
PC1 (SEG11)
36
PC0 (SEG12)
35
34
PG1 (SEG13)
33
PG0 (SEG14)
32
1.1Disclaimer
VCC
GND
RESET/PG5
(T1/SEG24) PG3
(T0/SEG23) PG4
(OC2A/PCINT15) PB7
(TOSC1) XTAL1
(TOSC2) XTAL2
(ICP1/SEG22) PD0
(SEG20) PD2
(INT0/SEG21) PD1
(SEG17) PD5
(SEG18) PD4
(SEG19) PD3
(SEG15) PD7
(SEG16) PD6
Note:The large center pad underneath the QFN/MLF packages is made of metal and internally con-
nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.
2
ATmega169P
8018IS–AVR–11/06
ATmega169P
2.Overview
The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.
2.1Block Diagram
Figure 2-1.Block Diagram
AVCC
AREF
VCC
GND
DATA REGISTER
JTAG TAP
ON-CHIP DEBUG
BOUNDARY-
SCAN
PROGRAMMING
LOGIC
PORTF DRIVERS
PORTF
DATA DIR.
REG. PORTF
ADC
PROGRAM
COUNTER
PROGRAM
FLASH
INSTRUCTION
REGISTER
INSTRUCTION
DECODER
CONTROL
LINES
DATA REGISTER
PORTA
STACK
POINTER
SRAM
GENERAL
PURPOSE
REGISTERS
X
Y
Z
ALU
PA0 - PA7PF0 - PF7
PORTA DRIVERS
DATA DIR.
REG. PORTA
8-BIT DATA BUS
INTERNAL
OSCILLATOR
WATCHDOG
TIMER
MCU CONTROL
REGISTER
TIMER/
COUNTERS
INTERRUPT
UNIT
EEPROM
PORTC DRIVERS
DATA REGISTER
PORTC
CALIB. OSC
OSCILLATOR
TIMING AND
CONTROL
PC0 - PC7
DATA DIR.
REG. PORTC
CONTROLLER/
LCD
DRIVER
XTAL1
XTAL2
RESET
ANALOG
COMPARATOR
8018IS–AVR–11/06
DATA REGISTER
+
-
AVR CPU
USART
PORTE
UNIVERSAL
SERIAL INTERFACE
DATA DIR.
REG. PORTE
PORTE DRIVERS
STATUS
REGISTER
DATA REGISTER
PORTB
PORTB DRIVERS
PB0 - PB7PE0 - PE7
DATA DIR.
REG. PORTB
SPI
DATA REGISTER
PORTD
REG. PORTD
PORTD DRIVERS
PD0 - PD7
DATA DIR.
DATA REG.
PORTG
PORTG DRIVERS
PG0 - PG4
DATA DIR.
REG. PORTG
3
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega169P provides the following features: 16K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, a complete On-chip LCD controller with internal step-up
voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a
serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer and the LCD controller continues to run, allowing the user to maintain a timer base and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low-power consumption.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot program running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega169P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.
4
ATmega169P
8018IS–AVR–11/06
2.2Pin Descriptions
2.2.1VCC
Digital supply voltage.
2.2.2GND
Ground.
2.2.3Port A (PA7:PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port A” on page 72.
2.2.4Port B (PB7:PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
ATmega169P
Port B has better driving capabilities than the other ports.
Port B also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port B” on page 73.
2.2.5Port C (PC7:PC0)
Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port C also serves the functions of special features of the ATmega169P as listed on ”Alternate
Functions of Port C” on page 76.
2.2.6Port D (PD7:PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port D also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port D” on page 78.
8018IS–AVR–11/06
5
2.2.7Port E (PE7:PE0)
Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port E also serves the functions of various special features of the ATmega169P as listed on
”Alternate Functions of Port E” on page 80.
2.2.8Port F (PF7:PF0)
Port F serves as the analog inputs to the A/D Converter.
Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.
Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on
page 82
2.2.9Port G (PG5:PG0)
Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port G also serves the functions of various special features of the ATmega169P as listed on
page 84.
2.2.10RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page
46. Shorter pulses are not guaranteed to generate a reset.
2.2.11XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
2.2.12XTAL2
Output from the inverting Oscillator amplifier.
2.2.13AVCC
AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V
, even if the ADC is not used. If the ADC is used, it should be connected to V
CC
CC
through a low-pass filter.
6
ATmega169P
8018IS–AVR–11/06
2.2.14AREF
2.2.15LCDCAP
3.Resources
ATmega169P
This is the analog reference pin for the A/D Converter.
An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-
ure 22-2 on page 234. This capacitor acts as a reservoir for LCD power (V
capacitance reduces ripple on V
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Note:1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
8018IS–AVR–11/06
11
5.Instruction Set Summary
MnemonicsOperandsDescriptionOperationFlags#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADDRd, RrAdd two RegistersRd ← Rd + RrZ,C,N,V,H1
ADCRd, RrAdd with Carry two RegistersRd ← Rd + Rr + CZ,C,N,V,H1
ADIWRdl,KAdd Immediate to WordRdh:Rdl ← Rdh:Rdl + KZ,C,N,V,S2
SUBRd, RrSubtract two RegistersRd ← Rd - RrZ,C,N,V,H1
SUBIRd, KSubtract Constant from Register Rd ← Rd - KZ,C,N,V,H1
SBCRd, RrSubtract with Carry two RegistersRd ← Rd - Rr - CZ,C,N,V,H1
SBCIRd, KSubtract with Carry Constant from Reg.Rd ← Rd - K - CZ,C,N,V,H1
SBIWRdl,KSubtract Immediate from WordRdh:Rdl ← Rdh:Rdl - KZ,C,N,V,S2
ANDRd, RrLogical AND RegistersRd ← Rd • RrZ,N,V1
ANDIRd, KLogical AND Register and ConstantRd ← Rd • KZ,N,V1
ORRd, RrLogical OR RegistersRd ← Rd v RrZ,N,V1
ORIRd, KLogical OR Register and ConstantRd ← Rd v KZ,N,V1
EORRd, RrExclusive OR RegistersRd ← Rd ⊕ RrZ,N,V1
COMRdOne’s ComplementRd ← 0xFF − RdZ,C,N,V1
NEGRdTwo’s ComplementRd ← 0x00 − RdZ,C,N,V,H1
SBRRd,KSet Bit(s) in RegisterRd ← Rd v KZ,N,V1
CBRRd,KClear Bit(s) in RegisterRd ← Rd • (0xFF - K)Z,N,V1
INCRdIncrementRd ← Rd + 1Z,N,V1
DECRdDecrementRd ← Rd − 1 Z,N,V1
TSTRdTest for Zero or MinusRd ← Rd • Rd Z,N,V1
CLRRdClear RegisterRd ← Rd ⊕ RdZ,N,V1
SERRdSet RegisterRd ← 0xFFNone1
MULRd, RrMultiply UnsignedR1:R0 ← Rd x RrZ,C2
MULSRd, RrMultiply SignedR1:R0 ← Rd x RrZ,C2
MULSURd, RrMultiply Signed with UnsignedR1:R0 ← Rd x RrZ,C2
FMULRd, RrFractional Multiply UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSRd, RrFractional Multiply SignedR1:R0 ← (Rd x Rr) << 1Z,C2
FMULSURd, RrFractional Multiply Signed with UnsignedR1:R0 ← (Rd x Rr) << 1Z,C2
BRANCH INSTRUCTIONS
RJMPkRelative JumpPC ← PC + k + 1None2
IJMPIndirect Jump to (Z)PC ← Z None2
JMPkDirect JumpPC ← kNone3
RCALLkRelative Subroutine Call PC ← PC + k + 1None3
ICALLIndirect Call to (Z)PC ← ZNone3
CALLkDirect Subroutine Call PC ← kNone4
RETSubroutine ReturnPC ← STACKNone4
RETIInterrupt ReturnPC ← STACKI4
CPSERd,RrCompare, Skip if Equalif (Rd = Rr) PC ← PC + 2 or 3None1/2/3
CPRd,RrCompareRd − RrZ, N,V,C,H1
CPCRd,RrCompare with CarryRd − Rr − CZ, N,V,C,H1
CPIRd,KCompare Register with ImmediateRd − KZ, N,V,C,H1
SBRCRr, bSkip if Bit in Register Clearedif (Rr(b)=0) PC ← PC + 2 or 3 None1/2/3
SBRSRr, bSkip if Bit in Register is Setif (Rr(b)=1) PC ← PC + 2 or 3None1/2/3
SBICP, bSkip if Bit in I/O Register Clearedif (P(b)=0) PC ← PC + 2 or 3 None1/2/3
SBISP, bSkip if Bit in I/O Register is Setif (P(b)=1) PC ← PC + 2 or 3None1/2/3
BRBSs, kBranch if Status Flag Setif (SREG(s) = 1) then PC←PC+k + 1None1/2
BRBCs, kBranch if Status Flag Clearedif (SREG(s) = 0) then PC←PC+k + 1None1/2
BREQ kBranch if Equal if (Z = 1) then PC ← PC + k + 1None1/2
BRNE kBranch if Not Equalif (Z = 0) then PC ← PC + k + 1None1/2
BRCS kBranch if Carry Setif (C = 1) then PC ← PC + k + 1None1/2
BRCC kBranch if Carry Clearedif (C = 0) then PC ← PC + k + 1None1/2
BRSH kBranch if Same or Higher if (C = 0) then PC ← PC + k + 1None1/2
BRLO kBranch if Lowerif (C = 1) then PC ← PC + k + 1None1/2
BRMI kBranch if Minusif (N = 1) then PC ← PC + k + 1None1/2
BRPL kBranch if Plus if (N = 0) then PC ← PC + k + 1None1/2
BRGE kBranch if Greater or Equal, Signedif (N ⊕ V= 0) then PC ← PC + k + 1None1/2
BRLT kBranch if Less Than Zero, Signedif (N ⊕ V= 1) then PC ← PC + k + 1None1/2
BRHS kBranch if Half Carry Flag Setif (H = 1) then PC ← PC + k + 1None1/2
BRHC kBranch if Half Carry Flag Clearedif (H = 0) then PC ← PC + k + 1None1/2
BRTS kBranch if T Flag Setif (T = 1) then PC ← PC + k + 1None1/2
BRTC kBranch if T Flag Clearedif (T = 0) then PC ← PC + k + 1None1/2
BRVS kBranch if Overflow Flag is Setif (V = 1) then PC ← PC + k + 1None1/2
12
ATmega169P
8018IS–AVR–11/06
ATmega169P
MnemonicsOperandsDescriptionOperationFlags#Clocks
BRVC kBranch if Overflow Flag is Clearedif (V = 0) then PC ← PC + k + 1None1/2
BRIE kBranch if Interrupt Enabledif ( I = 1) then PC ← PC + k + 1None1/2
BRID kBranch if Interrupt Disabledif ( I = 0) then PC ← PC + k + 1None1/2
64M164-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
8018IS–AVR–11/06
15
7.Packaging Information
7.164A
PIN 1
PIN 1 IDENTIFIER
B
e
E1E
D1
D
C
0˚~7˚
A1
L
Notes:1. This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A2A
SYMBOL
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A––1.20
A10.05–0.15
A2 0.951.001.05
D15.7516.0016.25
D113.9014.0014.10Note 2
E15.7516.0016.25
E113.9014.0014.10Note 2
B 0.30–0.45
C0.09–0.20
L0.45– 0.75
e0.80 TYP
NOM
MAX
NOTE
16
2325 Orchard Parkway
R
San Jose, CA 95131
ATmega169P
TITLE
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
10/5/2001
DRAWING NO.
64A
REV.
B
8018IS–AVR–11/06
7.264M1
D
Marked Pin# 1 ID
ATmega169P
E
SEATING PLANE
C
TOP VIEW
A1
A
K
L
D2
E2
K
b
e
BOTTOM VIEW
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
Note:
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Pin #1 Corner
1
2
3
Option A
Option B
Option C
Pin #1
Triangle
Pin #1
Chamfer
(C 0.30)
Pin #1
Notch
(0.20 R)
SIDE VIEW
SYMBOL
A 0.80 0.90 1.00
A1 – 0.02 0.05
b 0.180.250.30
D
D2 5.205.405.60
E
E2 5.205.405.60
e 0.50 BSC
L0.35 0.40 0.45
K1.251.401.55
0.08
C
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
8.909.009.10
8.909.009.10
NOM
MAX
NOTE
R
8018IS–AVR–11/06
2325 Orchard Parkway
San Jose, CA 95131
TITLE
64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)
DRAWING NO.
64M1
5/25/06
REV.
G
17
8.Errata
8.1ATmega169P Rev. G
No known errata.
8.2ATmega169P Rev. A to F
Not sampled.
18
ATmega169P
8018IS–AVR–11/06
9.Datasheet Revision History
Please note that the referring page numbers in this section are referring to this document. The
referring revision in this section are referring to the document revision.
9.1Rev. I 11/06
1.Updated ”Low-frequency Crystal Oscillator” on page 33.
2.Updated Table 7-8 on page 34, Table 7-9 on page 34, Table 7-10 on page 34, Table
27-7 on page 332.
3.Updated note in Table 27-7 on page 332.
9.2Rev. H 09/06
1.All characterization data moved to ”Electrical Characteristics” on page 325.
2.Updated ”Calibrated Internal RC Oscillator” on page 31.
3.Updated ”System Control and Reset” on page 46.
4.Added note to Table 26-16 on page 310.
5.Updated ”LCD Controller Characteristics” on page 333.
ATmega169P
9.3Rev. G 08/06
9.4Rev. F 08/06
9.5Rev. E 08/06
9.6Rev. D 07/06
1.Updated ”LCD Controller Characteristics” on page 333.
1.Updated ”DC Characteristics” on page 326.
2.Updated Table 12-19 on page 84.
1.Updated ”Low-frequency Crystal Oscillator” on page 33.
2.Updated ”Device Identification Register” on page 258.
3.Updated ”Signature Bytes” on page 297.
4.Added Table 26-6 on page 297.
8018IS–AVR–11/06
1.Updated ”Register Description for I/O-Ports” on page 88.
2.Updated ”Fast PWM Mode” on page 97.
3.Updated ”Fast PWM Mode” on page 120.
19
9.7Rev. C 06/06
9.8Rev. B 04/06
9.9Rev. A 03/06
4.Updated Table 13-2 on page 102, Table 13-4 on page 103, Table 14-3 on page 129,
Table 14-4 on page 130, Table 16-2 on page 153 and Table 16-4 on page 154.
5Updated ”UCSRnC – USART Control and Status Register n C” on page 192.
6.Updated Features in ”USI – Universal Serial Interface” on page 199.
7.Added ”Clock speed considerations.” on page 206.
8.Updated Features in ”LCD Controller” on page 233.
9.Updated ”Register Summary” on page 370.
1.Updated typos.
2.Updated ”Calibrated Internal RC Oscillator” on page 31.
3.Updated ”OSCCAL – Oscillator Calibration Register” on page 37.
4.Added Table 27-5 on page 334.
1.Updated ”Calibrated Internal RC Oscillator” on page 31.
1.Initial revision.
20
ATmega169P
8018IS–AVR–11/06
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