ATMEL AT MEGA 169 P V Service Manual

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Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 16K bytes of In-System Self-Programmable Flash

Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program
True Read-While-Write Operation

– 512 bytes EEPROM

Endurance: 100,000 Write/Erase Cycles
– 1K byte Internal SRAM
– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

• Peripheral Features

– 4 x 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture

Mode
– Real Time Counter with Separate Oscillator
–Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby

• I/O and Packages

– 54 Programmable I/O Lines
– 64-lead TQFP and 64-pad QFN/MLF

• Speed Grade:

– ATmega169PV: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 8 MHz @ 2.7 - 5.5V
– ATmega169P: 0 - 8 MHz @ 2.7 - 5.5V, 0 - 16 MHz @ 4.5 - 5.5V

• Temperature range:

– -40°C to 85°C Industrial

• Ultra-Low Power Consumption

– Active Mode:

1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
32 kHz, 1.8V: 25 µA (including Oscillator and LCD)

– Power-down Mode:

0.1 µA at 1.8V

– Power-save Mode:

0.6 µA at 1.8V(Including 32 kHz RTC)

®

8-Bit Microcontroller

8-bit

Microcontroller
with 16K Bytes
In-System
Programmable
Flash

ATmega169P
ATmega169PV

Preliminary
Summary

8018IS-AVR-11/06

1. Pin Configurations

Figure 1-1. Pinout ATmega169P

LCDCAP

(RXD/PCINT0) PE0

(TXD/PCINT1) PE1

(XCK/AIN0/PCINT2) PE2

(AIN1/PCINT3) PE3

(USCK/SCL/PCINT4) PE4

(DI/SDA/PCINT5) PE5

(DO/PCINT6) PE6

(CLKO/PCINT7) PE7

(SS/PCINT8) PB0

(SCK/PCINT9) PB1

(MOSI/PCINT10) PB2

(MISO/PCINT11) PB3

(OC0A/PCINT12) PB4

(OC1A/PCINT13) PB5

(OC1B/PCINT14) PB6

VCC

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

PF4 (ADC4/TCK)

AREF

GND

AVCC

61

64

63

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

INDEX CORNER

17

6018592058

62

19

21

PF5 (ADC5/TMS)

57225623552454255326522751

GND

PF7 (ADC7/TDI)

PF6 (ADC6/TDO)

28

29

PA0 (COM0)

PA1 (COM1)

50

31

30

PA2 (COM2)

49

PA3 (COM3)

48

PA4 (SEG0)

47

PA5 (SEG1)

46

PA6 (SEG2)

45

PA7 (SEG3)

44

43

PG2 (SEG4)

42

PC7 (SEG5)

41

PC6 (SEG6)

40

PC5 (SEG7)

PC4 (SEG8)

39

PC3 (SEG9)

38

PC2 (SEG10)

37

PC1 (SEG11)

36

PC0 (SEG12)

35

34

PG1 (SEG13)

33

PG0 (SEG14)

32

1.1 Disclaimer

VCC

GND

RESET/PG5

(T1/SEG24) PG3

(T0/SEG23) PG4

(OC2A/PCINT15) PB7

(TOSC1) XTAL1

(TOSC2) XTAL2

(ICP1/SEG22) PD0

(SEG20) PD2

(INT0/SEG21) PD1

(SEG17) PD5

(SEG18) PD4

(SEG19) PD3

(SEG15) PD7

(SEG16) PD6

Note: The large center pad underneath the QFN/MLF packages is made of metal and internally con-

nected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If
the center pad is left unconnected, the package might loosen from the board.

Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values
will be available after the device is characterized.

2

ATmega169P

8018IS–AVR–11/06

ATmega169P

2. Overview

The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut­ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz
allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

AVCC

AREF

VCC

GND

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF DRIVERS

PORTF

DATA DIR.

REG. PORTF

ADC

PROGRAM
COUNTER

PROGRAM

FLASH

INSTRUCTION

REGISTER

INSTRUCTION

DECODER

CONTROL

LINES

DATA REGISTER

PORTA

STACK

POINTER

SRAM

GENERAL
PURPOSE

REGISTERS

X

Y

Z

ALU

PA0 - PA7PF0 - PF7

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

REGISTER

TIMER/

COUNTERS

INTERRUPT

UNIT

EEPROM

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC0 - PC7

DATA DIR.

REG. PORTC

CONTROLLER/

LCD

DRIVER

XTAL1

XTAL2

RESET

ANALOG

COMPARATOR

8018IS–AVR–11/06

DATA REGISTER

+

-

AVR CPU

USART

PORTE

UNIVERSAL

SERIAL INTERFACE

DATA DIR.

REG. PORTE

PORTE DRIVERS

STATUS

REGISTER

DATA REGISTER

PORTB

PORTB DRIVERS

PB0 - PB7PE0 - PE7

DATA DIR.

REG. PORTB

SPI

DATA REGISTER

PORTD

REG. PORTD

PORTD DRIVERS

PD0 - PD7

DATA DIR.

DATA REG.

PORTG

PORTG DRIVERS

PG0 - PG4

DATA DIR.

REG. PORTG

3

The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con­ventional CISC microcontrollers.

The ATmega169P provides the following features: 16K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 1K byte SRAM, 53 general purpose I/O
lines, 32 general purpose working registers, a JTAG interface for Boundary-scan, On-chip
Debugging support and programming, a complete On-chip LCD controller with internal step-up
voltage, three flexible Timer/Counters with compare modes, internal and external interrupts, a
serial programmable USART, Universal Serial Interface with Start Condition Detector, an 8­channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, an SPI serial
port, and five software selectable power saving modes. The Idle mode stops the CPU while
allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The
Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip
functions until the next interrupt or hardware reset. In Power-save mode, the asynchronous
timer and the LCD controller continues to run, allowing the user to maintain a timer base and
operate the LCD display while the rest of the device is sleeping. The ADC Noise Reduction
mode stops the CPU and all I/O modules except asynchronous timer, LCD controller and ADC,
to minimize switching noise during ADC conversions. In Standby mode, the crystal/resonator
Oscillator is running while the rest of the device is sleeping. This allows very fast start-up com­bined with low-power consumption.

The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the program memory to be reprogrammed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer, or by an On-chip Boot pro­gram running on the AVR core. The Boot program can use any interface to download the
application program in the Application Flash memory. Software in the Boot Flash section will
continue to run while the Application Flash section is updated, providing true Read-While-Write
operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a
monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex­ible and cost effective solution to many embedded control applications.

The ATmega169P AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators,
and Evaluation kits.

4

ATmega169P

8018IS–AVR–11/06

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port A (PA7:PA0)

Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port A also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port A” on page 72.

2.2.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

ATmega169P

Port B has better driving capabilities than the other ports.

Port B also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port B” on page 73.

2.2.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port C output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port C also serves the functions of special features of the ATmega169P as listed on ”Alternate

Functions of Port C” on page 76.

2.2.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port D also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port D” on page 78.

8018IS–AVR–11/06

5

2.2.7 Port E (PE7:PE0)

Port E is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port E also serves the functions of various special features of the ATmega169P as listed on

”Alternate Functions of Port E” on page 80.

2.2.8 Port F (PF7:PF0)

Port F serves as the analog inputs to the A/D Converter.

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins
can provide internal pull-up resistors (selected for each bit). The Port F output buffers have sym­metrical drive characteristics with both high sink and source capability. As inputs, Port F pins
that are externally pulled low will source current if the pull-up resistors are activated. The Port F
pins are tri-stated when a reset condition becomes active, even if the clock is not running. If the
JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will
be activated even if a reset occurs.

Port F also serves the functions of the JTAG interface, see ”Alternate Functions of Port F” on

page 82

2.2.9 Port G (PG5:PG0)

Port G is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port G output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port G pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port G pins are tri-stated when a reset condition becomes active,
even if the clock is not running.

Port G also serves the functions of various special features of the ATmega169P as listed on

page 84.

2.2.10 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 9-1 on page

46. Shorter pulses are not guaranteed to generate a reset.

2.2.11 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.2.12 XTAL2

Output from the inverting Oscillator amplifier.

2.2.13 AVCC

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally con­nected to V

, even if the ADC is not used. If the ADC is used, it should be connected to V

CC

CC

through a low-pass filter.

6

ATmega169P

8018IS–AVR–11/06

2.2.14 AREF

2.2.15 LCDCAP

3. Resources

ATmega169P

This is the analog reference pin for the A/D Converter.

An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in Fig-

ure 22-2 on page 234. This capacitor acts as a reservoir for LCD power (V

capacitance reduces ripple on V

A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.

but increases the time until V

LCD

reaches its target value.

LCD

). A large

LCD

8018IS–AVR–11/06

7

4. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved – – – – – – – –

(0xFE) LCDDR18 – – – – – – – SEG324 248

(0xFD) LCDDR17 SEG323 SEG322 SEG321 SEG320 SEG319 SEG318 SEG317 SEG316 248

(0xFC) LCDDR16 SEG315 SEG314 SEG313 SEG312 SEG311 SEG310 SEG309 SEG308 248

(0xFB) LCDDR15 SEG307 SEG306 SEG305 SEG304 SEG303 SEG302 SEG301 SEG300 248

(0xFA) Reserved – – – – – – – –

(0xF9) LCDDR13 – – – – – – – SEG224 248

(0xF8) LCDDR12 SEG223 SEG222 SEG221 SEG220 SEG219 SEG218 SEG217 SEG216 248

(0xF7) LCDDR11 SEG215 SEG214 SEG213 SEG212 SEG211 SEG210 SEG209 SEG208 248

(0xF6) LCDDR10 SEG207 SEG206 SEG205 SEG204 SEG203 SEG202 SEG201 SEG200 248

(0xF5) Reserved – – – – – – – –

(0xF4) LCDDR8 – – – – – – – SEG124 248

(0xF3) LCDDR7 SEG123 SEG122 SEG121 SEG120 SEG119 SEG118 SEG117 SEG116 248

(0xF2) LCDDR6 SEG115 SEG114 SEG113 SEG112 SEG111 SEG110 SEG109 SEG108 248

(0xF1) LCDDR5 SEG107 SEG106 SEG105 SEG104 SEG103 SEG102 SEG101 SEG100 248

(0xF0) Reserved – – – – – – – –

(0xEF) LCDDR3

(0xEE) LCDDR2 SEG023 SEG022 SEG021 SEG020 SEG019 SEG018 SEG017 SEG016 248

(0xED) LCDDR1 SEG015 SEG014 SEG013 SEG012 SEG011 SEG010 SEG09 SEG008 248

(0xEC) LCDDR0 SEG007 SEG006 SEG005 SEG004 SEG003 SEG002 SEG001 SEG000 248

(0xEB) Reserved

(0xEA) Reserved – – – – – – – –

(0xE9) Reserved – – – – – – – –

(0xE8) Reserved – – – – – – – –

(0xE7) LCDCCR LCDCD2 LCDCD1 LCDCC0 LCDMDT LCDCC3 LCDCC2 LCDCC1 LCDCC0 247

(0xE6) LCDFRR – LCDPS2 LCDPS1 LCDPS0 – LCDCD2 LCDCD1 LCDCD0 245

(0xE5) LCDCRB LCDCS LCD2B LCDMUX1 LCDMUX0 – LCDPM2 LCDPM1 LCDPM0 244

(0xE4) LCDCRA LCDEN LCDAB – LCDIF LCDIE LCDBD LCDCCD LCDBL 243

(0xE3) Reserved – – – – – – – –

(0xE2) Reserved – – – – – – – –

(0xE1) Reserved – – – – – – – –

(0xE0) Reserved – – – – – – – –

(0xDF) Reserved – – – – – – – –

(0xDE) Reserved – – – – – – – –

(0xDD) Reserved – – – – – – – –

(0xDC) Reserved – – – – – – – –

(0xDB) Reserved – – – – – – – –

(0xDA) Reserved – – – – – – – –

(0xD9) Reserved – – – – – – – –

(0xD8) Reserved – – – – – – – –

(0xD7) Reserved

(0xD6) Reserved

(0xD5) Reserved – – – – – – – –

(0xD4) Reserved

(0xD3) Reserved

(0xD2) Reserved

(0xD1) Reserved – – – – – – – –

(0xD0) Reserved

(0xCF) Reserved

(0xCE) Reserved – – – – – – – –

(0xCD) Reserved

(0xCC) Reserved

(0xCB) Reserved – – – – – – – –

(0xCA) Reserved

(0xC9) Reserved

(0xC8) Reserved – – – – – – – –

(0xC7) Reserved

(0xC6) UDR0 USART0 I/O Data Register 189

(0xC5) UBRR0H

(0xC4) UBRR0L USART0 Baud Rate Register Low 193

(0xC3) Reserved

(0xC2) UCSR0C

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 189

(0xC0) UCSR0A RXC0 TXC0 UDRE0 FE0 DOR0 UPE0 U2X0 MPCM0 189

– – – – – – – SEG024 248

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

USART0 Baud Rate Register High 193

– – – – – – – –

– UMSEL0 UPM10 UPM00 USBS0 UCSZ01 UCSZ00 UCPOL0 189

8

ATmega169P

8018IS–AVR–11/06

ATmega169P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xBF) Reserved – – – – – – – –

(0xBE) Reserved – – – – – – – –

(0xBD) Reserved – – – – – – – –

(0xBC) Reserved – – – – – – – –

(0xBB) Reserved – – – – – – – –

(0xBA) USIDR USI Data Register 206

(0xB9) USISR USISIF USIOIF USIPF USIDC USICNT3 USICNT2 USICNT1 USICNT0 206

(0xB8) USICR USISIE USIOIE USIWM1 USIWM0 USICS1 USICS0 USICLK USITC 207

(0xB7) Reserved – – – – – – –

(0xB6) ASSR – – – EXCLK AS2 TCN2UB OCR2UB TCR2UB 155

(0xB5) Reserved – – – – – – – –

(0xB4) Reserved – – – – – – – –

(0xB3) OCR2A Timer/Counter2 Output Compare Register A 154

(0xB2) TCNT2 Timer/Counter2 (8-bit) 154

(0xB1) Reserved – – – – – – – –

(0xB0) TCCR2A FOC2A WGM20 COM2A1 COM2A0 WGM21 CS22 CS21 CS20 152

(0xAF) Reserved

(0xAE) Reserved

(0xAD) Reserved – – – – – – – –

(0xAC) Reserved

(0xAB) Reserved

(0xAA) Reserved – – – – – – – –

(0xA9) Reserved – – – – – – – –

(0xA8) Reserved – – – – – – – –

(0xA7) Reserved – – – – – – – –

(0xA6) Reserved – – – – – – – –

(0xA5) Reserved – – – – – – – –

(0xA4) Reserved – – – – – – – –

(0xA3) Reserved – – – – – – – –

(0xA2) Reserved – – – – – – – –

(0xA1) Reserved – – – – – – – –

(0xA0) Reserved – – – – – – – –

(0x9F) Reserved – – – – – – – –

(0x9E) Reserved – – – – – – – –

(0x9D) Reserved – – – – – – – –

(0x9C) Reserved – – – – – – – –

(0x9B) Reserved – – – – – – – –

(0x9A) Reserved – – – – – – – –

(0x99) Reserved – – – – – – – –

(0x98) Reserved – – – – – – – –

(0x97) Reserved – – – – – – – –

(0x96) Reserved – – – – – – – –

(0x95) Reserved – – – – – – – –

(0x94) Reserved

(0x93) Reserved

(0x92) Reserved – – – – – – – –

(0x91) Reserved

(0x90) Reserved

(0x8F) Reserved

(0x8E) Reserved – – – – – – – –

(0x8D) Reserved

(0x8C) Reserved

(0x8B) OCR1BH Timer/Counter1 - Output Compare Register B High Byte 131

(0x8A) OCR1BL Timer/Counter1 - Output Compare Register B Low Byte 131

(0x89) OCR1AH Timer/Counter1 - Output Compare Register A High Byte 131

(0x88) OCR1AL Timer/Counter1 - Output Compare Register A Low Byte 131

(0x87) ICR1H Timer/Counter1 - Input Capture Register High Byte 132

(0x86) ICR1L Timer/Counter1 - Input Capture Register Low Byte 132

(0x85) TCNT1H Timer/Counter1 - Counter Register High Byte 131

(0x84) TCNT1L Timer/Counter1 - Counter Register Low Byte 131

(0x83) Reserved

(0x82) TCCR1C FOC1A FOC1B

(0x81) TCCR1B ICNC1 ICES1

(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – –WGM11WGM10127

(0x7F) DIDR1

(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D ADC3D ADC2D ADC1D ADC0D 231

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – – – –

– – – – – –130

– WGM13 WGM12 CS12 CS11 CS10 129

– – – – – –AIN1DAIN0D213

8018IS–AVR–11/06

9

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0x7D) Reserved – – – – – – – –

(0x7C) ADMUX REFS1 REFS0 ADLAR MUX4 MUX3 MUX2 MUX1 MUX0 227

(0x7B) ADCSRB –ACME– – – ADTS2 ADTS1 ADTS0 212, 231

(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 229

(0x79) ADCH ADC Data Register High byte 230

(0x78) ADCL ADC Data Register Low byte 230

(0x77) Reserved – – – – – – – –

(0x76) Reserved – – – – – – – –

(0x75) Reserved – – – – – – – –

(0x74) Reserved – – – – – – – –

(0x73) Reserved – – – – – – – –

(0x72) Reserved – – – – – – – –

(0x71) Reserved – – – – – – – –

(0x70) TIMSK2 – – – – – – OCIE2A TOIE2 155

(0x6F) TIMSK1 – –ICIE1– – OCIE1B OCIE1A TOIE1 132

(0x6E) TIMSK0 – – – – – – OCIE0A TOIE0 103

(0x6D) Reserved

(0x6C) PCMSK1 PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 62

(0x6B) PCMSK0 PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 63

(0x6A) Reserved – – – – – – – –

(0x69) EICRA

(0x68) Reserved – – – – – – – –

(0x67) Reserved – – – – – – – –

(0x66) OSCCAL Oscillator Calibration Register 36

(0x65) Reserved – – – – – – – –

(0x64) PRR – – – PRLCD PRTIM1 PRSPI PRUSART0 PRADC 43

(0x63) Reserved – – – – – – – –

(0x62) Reserved – – – – – – – –

(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 36

(0x60) WDTCR – – – WDCE WDE WDP2 WDP1 WDP0 53

0x3F (0x5F) SREG I T H S V N Z C 12

0x3E (0x5E) SPH – – – – – SP10 SP9 SP8 14

0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 14

0x3C (0x5C) Reserved

0x3B (0x5B) Reserved

0x3A (0x5A) Reserved

0x39 (0x59) Reserved

0x38 (0x58) Reserved

0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN 292

0x36 (0x56) Reserved – – – – – – – –

0x35 (0x55) MCUCR JTD – –PUD– – IVSEL IVCE 59, 87, 277

0x34 (0x54) MCUSR – – – JTRF WDRF BORF EXTRF PORF 277

0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE 43

0x32 (0x52) Reserved

0x31 (0x51) OCDR IDRD/OCDR7

0x30 (0x50) ACSR ACD ACBG ACO ACI ACIE ACIC ACIS1 ACIS0 212

0x2F (0x4F) Reserved

0x2E (0x4E) SPDR SPI Data Register 166

0x2D (0x4D) SPSR SPIF WCOL – – – – –SPI2X165

0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 164

0x2B (0x4B) GPIOR2 General Purpose I/O Register 2 28

0x2A (0x4A) GPIOR1 General Purpose I/O Register 1 28

0x29 (0x49) Reserved – – – – – – – –

0x28 (0x48) Reserved

0x27 (0x47) OCR0A Timer/Counter0 Output Compare Register A 103

0x26 (0x46) TCNT0 Timer/Counter0 (8 Bit) 103

0x25 (0x45) Reserved – – – – – – – –

0x24 (0x44) TCCR0A FOC0A WGM00 COM0A1 COM0A0 WGM01 CS02 CS01 CS00 101

0x23 (0x43) GTCCR TSM

0x22 (0x42) EEARH

0x21 (0x41) EEARL EEPROM Address Register Low Byte 26

0x20 (0x40) EEDR EEPROM Data Register 26

0x1F (0x3F) EECR – – – – EERIE EEMWE EEWE EERE 26

0x1E (0x3E) GPIOR0 General Purpose I/O Register 0 28

0x1D (0x3D) EIMSK PCIE1 PCIE0

0x1C (0x3C) EIFR PCIF1 PCIF0

– – – – – – – –

– – – – – –ISC01ISC0061

– – – – – – – –

OCDR6 OCDR5 OCDR4 OCDR3 OCDR2 OCDR1 OCDR0 255

– – – – – – – –

– – – – – – – –

– – – – – PSR2 PSR10 136, 156

– – – – – – – EEAR8 26

– – – – –INT061

– – – – – INTF0 62

10

ATmega169P

8018IS–AVR–11/06

ATmega169P

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

0x1B (0x3B) Reserved – – – – – – – –

0x1A (0x3A) Reserved – – – – – – – –

0x19 (0x39) Reserved – – – – – – – –

0x18 (0x38) Reserved – – – – – – – –

0x17 (0x37) TIFR2 – – – – – – OCF2A TOV2 155

0x16 (0x36) TIFR1 – –ICF1– – OCF1B OCF1A TOV1 133

0x15 (0x35) TIFR0 – – – – – – OCF0A TOV0 104

0x14 (0x34) PORTG – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 89

0x13 (0x33) DDRG – – – DDG4 DDG3 DDG2 DDG1 DDG0 89

0x12 (0x32) PING – – – PING4 PING3 PING2 PING1 PING0 89

0x11 (0x31) PORTF PORTF7 PORTF6 PORTF5 PORTF4 PORTF3 PORTF2 PORTF1 PORTF0 89

0x10 (0x30) DDRF DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 89

0x0F (0x2F) PINF PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 89

0x0E (0x2E) PORTE PORTE7 PORTE6 PORTE5PORTE4PORTE3PORTE2PORTE1PORTE0 88

0x0D (0x2D) DDRE DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 88

0x0C (0x2C) PINE PINE7 PINE6 PINE5PINE4PINE3PINE2PINE1PINE0 89

0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 88

0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 88

0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 88

0x08 (0x28) PORTC PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 88

0x07 (0x27) DDRC DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 88

0x06 (0x26) PINC PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 88

0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0 87

0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 87

0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 87

0x02 (0x22) PORTA PORTA7 PORTA6 PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0 87

0x01 (0x21) DDRA DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 87

0x00 (0x20) PINA PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 87

Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.

4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega169P is a com­plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.

8018IS–AVR–11/06

11

5. Instruction Set Summary

Mnemonics Operands Description Operation Flags #Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1

ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1

ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2

SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1

SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1

SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1

SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1

SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2

AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1

ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1

OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1

ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1

EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1

COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1

NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1

SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1

CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1

INC Rd Increment Rd ← Rd + 1 Z,N,V 1

DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1

TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1

CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1

SER Rd Set Register Rd ← 0xFF None 1

MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2

MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2

MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2

BRANCH INSTRUCTIONS

RJMP k Relative Jump PC ← PC + k + 1 None 2

IJMP Indirect Jump to (Z) PC ← Z None 2

JMP k Direct Jump PC ← kNone3

RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3

ICALL Indirect Call to (Z) PC ← ZNone3

CALL k Direct Subroutine Call PC ← kNone4

RET Subroutine Return PC ← STACK None 4

RETI Interrupt Return PC ← STACK I 4

CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3

CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1

CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1

CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1

SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3

SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3

SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3

BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2

BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2

BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2

BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2

BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2

BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2

BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2

BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2

BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2

BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2

BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2

BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2

BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2

BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2

BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2

BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2

BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2

12

ATmega169P

8018IS–AVR–11/06

ATmega169P

Mnemonics Operands Description Operation Flags #Clocks

BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2

BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2

BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2

BIT AND BIT-TEST INSTRUCTIONS

SBI P,b Set Bit in I/O Register I/O(P,b) ← 1None2

CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0None2

LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1

LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1

ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1

ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1

ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1

SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1

BSET s Flag Set SREG(s) ← 1 SREG(s) 1

BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1

BST Rr, b Bit Store from Register to T T ← Rr(b) T 1

BLD Rd, b Bit load from T to Register Rd(b) ← TNone1

SEC Set Carry C ← 1C1

CLC Clear Carry C ← 0 C 1

SEN Set Negative Flag N ← 1N1

CLN Clear Negative Flag N ← 0 N 1

SEZ Set Zero Flag Z ← 1Z1

CLZ Clear Zero Flag Z ← 0 Z 1

SEI Global Interrupt Enable I ← 1I1

CLI Global Interrupt Disable I ← 0 I 1

SES Set Signed Test Flag S ← 1S1

CLS Clear Signed Test Flag S ← 0 S 1

SEV Set Twos Complement Overflow. V ← 1V1

CLV Clear Twos Complement Overflow V ← 0 V 1

SET Set T in SREG T ← 1T1

CLT Clear T in SREG T ← 0 T 1

SEH Set Half Carry Flag in SREG H ← 1H1
CLH Clear Half Carry Flag in SREG H ← 0 H 1

DATA TRANSFER INSTRUCTIONS

MOV Rd, Rr Move Between Registers Rd ← Rr None 1

MOVW Rd, Rr Copy Register Word

LDI Rd, K Load Immediate Rd ← KNone1

LD Rd, X Load Indirect Rd ← (X) None 2

LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2

LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2

LD Rd, Y Load Indirect Rd ← (Y) None 2

LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2

LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2

LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2

LD Rd, Z Load Indirect Rd ← (Z) None 2

LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2

LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2

LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2

LDS Rd, k Load Direct from SRAM Rd ← (k) None 2

ST X, Rr Store Indirect (X) ← Rr None 2

ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2

ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2

ST Y, Rr Store Indirect (Y) ← Rr None 2

ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2

ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2

STD Y+q,Rr Store Indirect with Displacement (Y + q) ← Rr None 2

ST Z, Rr Store Indirect (Z) ← Rr None 2

ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2

ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2

STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2

STS k, Rr Store Direct to SRAM (k) ← Rr None 2

LPM Load Program Memory R0 ← (Z) None 3

LPM Rd, Z Load Program Memory Rd ← (Z) None 3

LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3

SPM Store Program Memory (Z) ← R1:R0 None -

IN Rd, P In Port Rd ← PNone1

OUT P, Rr Out Port P ← Rr None 1

Rd+1:Rd ← Rr+1:Rr

None 1

8018IS–AVR–11/06

13

Mnemonics Operands Description Operation Flags #Clocks

PUSH Rr Push Register on Stack STACK ← Rr None 2

POP Rd Pop Register from Stack Rd ← STACK None 2

MCU CONTROL INSTRUCTIONS

NOP No Operation None 1

SLEEP Sleep (see specific descr. for Sleep function) None 1

WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A

14

ATmega169P

8018IS–AVR–11/06

6. Ordering Information

ATmega169P

Speed (MHz)

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

3. For Speed vs. V

(3)

8 1.8 - 5.5V

16 2.7 - 5.5V

and minimum quantities.

Halide free and fully Green.

Power Supply Ordering Code Package

, see Figure 27-2 on page 329 and Figure 27-3 on page 329.

CC

ATmega169PV-8AU
ATmega169PV-8MU

ATmega169P-16AU
ATmega169P-16MU

64A
64M1

64A
64M1

(1)(2)

Operation Range

Industrial

0°C to 85°C)

(-4

Industrial

0°C to 85°C)

(-4

Package Type

64A 64-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP)

64M1 64-pad, 9 x 9 x 1.0 mm body, lead pitch 0.50 mm, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

8018IS–AVR–11/06

15

7. Packaging Information

7.1 64A

PIN 1

PIN 1 IDENTIFIER

B

e

E1 E

D1

D

C

0˚~7˚

A1

L

Notes: 1. This package conforms to JEDEC reference MS-026, Variation AEB.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.

3. Lead coplanarity is 0.10 mm maximum.

A2 A

SYMBOL

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

A – – 1.20

A1 0.05 – 0.15

A2 0.95 1.00 1.05

D 15.75 16.00 16.25

D1 13.90 14.00 14.10 Note 2

E 15.75 16.00 16.25

E1 13.90 14.00 14.10 Note 2

B 0.30 – 0.45

C 0.09 – 0.20

L 0.45 – 0.75

e 0.80 TYP

NOM

MAX

NOTE

16

2325 Orchard Parkway

R

San Jose, CA 95131

ATmega169P

TITLE

64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

10/5/2001

DRAWING NO.

64A

REV.

B

8018IS–AVR–11/06

7.2 64M1

D

Marked Pin# 1 ID

ATmega169P

E

SEATING PLANE

C

TOP VIEW

A1

A

K

L

D2

E2

K

b

e

BOTTOM VIEW

1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.

Note:

2. Dimension and tolerance conform to ASMEY14.5M-1994.

Pin #1 Corner

1
2
3

Option A

Option B

Option C

Pin #1
Triangle

Pin #1
Chamfer
(C 0.30)

Pin #1
Notch
(0.20 R)

SIDE VIEW

SYMBOL

A 0.80 0.90 1.00

A1 – 0.02 0.05

b 0.18 0.25 0.30

D

D2 5.20 5.40 5.60

E

E2 5.20 5.40 5.60

e 0.50 BSC

L 0.35 0.40 0.45

K 1.25 1.40 1.55

0.08

C

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

8.90 9.00 9.10

8.90 9.00 9.10

NOM

MAX

NOTE

R

8018IS–AVR–11/06

2325 Orchard Parkway
San Jose, CA 95131

TITLE

64M1, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,

5.40 mm Exposed Pad, Micro Lead Frame Package (MLF)

DRAWING NO.

64M1

5/25/06

REV.

G

17

8. Errata

8.1 ATmega169P Rev. G

No known errata.

8.2 ATmega169P Rev. A to F

Not sampled.

18

ATmega169P

8018IS–AVR–11/06

9. Datasheet Revision History

Please note that the referring page numbers in this section are referring to this document. The
referring revision in this section are referring to the document revision.

9.1 Rev. I 11/06

1. Updated ”Low-frequency Crystal Oscillator” on page 33.

2. Updated Table 7-8 on page 34, Table 7-9 on page 34, Table 7-10 on page 34, Table

27-7 on page 332.

3. Updated note in Table 27-7 on page 332.

9.2 Rev. H 09/06

1. All characterization data moved to ”Electrical Characteristics” on page 325.

2. Updated ”Calibrated Internal RC Oscillator” on page 31.

3. Updated ”System Control and Reset” on page 46.

4. Added note to Table 26-16 on page 310.

5. Updated ”LCD Controller Characteristics” on page 333.

ATmega169P

9.3 Rev. G 08/06

9.4 Rev. F 08/06

9.5 Rev. E 08/06

9.6 Rev. D 07/06

1. Updated ”LCD Controller Characteristics” on page 333.

1. Updated ”DC Characteristics” on page 326.

2. Updated Table 12-19 on page 84.

1. Updated ”Low-frequency Crystal Oscillator” on page 33.

2. Updated ”Device Identification Register” on page 258.

3. Updated ”Signature Bytes” on page 297.

4. Added Table 26-6 on page 297.

8018IS–AVR–11/06

1. Updated ”Register Description for I/O-Ports” on page 88.

2. Updated ”Fast PWM Mode” on page 97.

3. Updated ”Fast PWM Mode” on page 120.

19

9.7 Rev. C 06/06

9.8 Rev. B 04/06

9.9 Rev. A 03/06

4. Updated Table 13-2 on page 102, Table 13-4 on page 103, Table 14-3 on page 129,

Table 14-4 on page 130, Table 16-2 on page 153 and Table 16-4 on page 154.

5 Updated ”UCSRnC – USART Control and Status Register n C” on page 192.

6. Updated Features in ”USI – Universal Serial Interface” on page 199.

7. Added ”Clock speed considerations.” on page 206.

8. Updated Features in ”LCD Controller” on page 233.

9. Updated ”Register Summary” on page 370.

1. Updated typos.

2. Updated ”Calibrated Internal RC Oscillator” on page 31.

3. Updated ”OSCCAL – Oscillator Calibration Register” on page 37.

4. Added Table 27-5 on page 334.

1. Updated ”Calibrated Internal RC Oscillator” on page 31.

1. Initial revision.

20

ATmega169P

8018IS–AVR–11/06

Atmel Corporation Atmel Operations

2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: [phone]
Fax: [phone]

Regional Headquarters

Europe

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Memory

2325 Orchard Parkway
San Jose, CA 95131, USA
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Fax: [phone]

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13106 Rousset Cedex, France
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: [phone]
Fax: [phone]

RF/Automotive

Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: [phone]
Fax: [phone]

1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906, USA
Tel: [phone]
Fax: [phone]

Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom

Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: [phone]
Fax: [phone]

Literature Requests

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