ATMEL ATmega164P, ATmega164PV, ATmega324P, ATmega324PV, ATmega644P User Manual

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Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 20 MIPS Throughput at 20 MHz – On-chip 2-cycle Multiplier

• High Endurance Non-volat ile Memory segments

– 16/32/64K Bytes of In-System Self-programmable Flash program memory – 512B/1K/2K Bytes EEPROM – 1/2/4K Bytes Internal SRAM

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM – Data retention: 20 years at 85°C/100 years at 25°C – Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation

– Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits thr ough the JTAG Interface

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes – One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode – Real Time Counter with Separate Oscillator – Six PWM Channels – 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x – Byte-oriented Two-wire Serial Interface – Two Programmable Serial USART – Master/Slave SPI Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power -save, Power-down, Standby and

Extended Standby

• I/O and Packages

– 32 Programmable I/O Lines – 40-pin PDIP, 44-lead TQFP, and 44-pad QFN/MLF

• Operating Voltages

– 1.8 - 5.5V for ATmega164P/324P/644PV – 2.7 - 5.5V for ATmega164P/324P/644P

• Speed Grades

– ATmega164P/324P/644PV: 0 - 4MHz @ 1.8 - 5.5V, 0 - 10MHz @ 2.7 - 5.5V – ATmega164P/324P/644P: 0 - 10MHz @ 2.7 - 5.5V, 0 - 20MHz @ 4.5 - 5.5V

• Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644P

– Active: 0.4 mA – Power-down Mode: 0.1µA – Power-save Mode: 0.6µA (Including 32 kHz RTC)

8-bit Microcontroller

8-bit

Microcontroller with 16/32/64K Bytes In-System Programmable Flash

ATmega164P/V ATmega324P/V ATmega644P/V

Preliminary

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ATmega164P/324P/644P

1. Pin Configurations

Figure 1-1. Pinout ATmega164P/324P/644P

PDIP

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

TQFP/QFN/MLF

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA0 (ADC0/PCINT0) PA1 (ADC1/PCINT1) PA2 (ADC2/PCINT2) PA3 (ADC3/PCINT3) PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVCC PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20) PC3 (TMS/PCINT19) PC2 (TCK/PCINT18) PC1 (SDA/PCINT17) PC0 (SCL/PCINT16) PD7 (OC2A/PCINT31)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

(PCINT13/MOSI) PB5 (PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND XTAL2 XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

VCC

GND

(PCINT16/SCL) PC0

(PCINT29/OC1A) PD5

(PCINT31/OC2A) PD7

(PCINT30/OC2B/ICP) PD6

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT17/SDA) PC1

(PCINT18/TCK) PC2

PA4 (ADC4/PCINT4) PA5 (ADC5/PCINT5) PA6 (ADC6/PCINT6) PA7 (ADC7/PCINT7) AREF GND AVC C PC7 (TOSC2/PCINT23) PC6 (TOSC1/PCINT22) PC5 (TDI/PCINT21) PC4 (TDO/PCINT20)

(PCINT19/TMS) PC3

Note: The large center pad underneath the QFN/MLF package should be soldered to ground on the

board to ensure good mechanical stability.

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2. Overview

PC5..0

PA7..0

TOSC1/PC6TOSC2/PC7

The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus pr ocessing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

ATmega164P/324P/644P

RESET

XTAL1

VCC

GND

XTAL2

Power

Supervision

POR / BOD &

RESET

Watchdog

Timer

Watchdog

Oscillator

Circuits /

Clock

Generation

EEPROM

JTAG/OCD

PORT A (8)

A/D

Converter

TWI

Internal

Bandgap reference

CPU

SRAMFLASH

PB7..0

PORT B (8)

Analog

Comparator

SPI

8bit T/C 0

16bit T/C 1

8bit T/C 2

USART 0

USART 1

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PORT C (8)

PORT D (8)

PD7..0

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

ATmega164P/324P/644P

The ATmega164P/324P/644P provides the following features: 16/32/64K bytes of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K bytes EEPROM, 1/2/4K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes an d PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Powersave mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control app lications.

The ATmega164P/324P/644P AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P

Table 2-1. Differences between ATmega164P and AT meg a6 44 P

Device Flash EEPROM RAM

ATmega164P 16 Kbyte 512 Bytes 1 Kbyte ATmega324P 32 Kbyte 1 Kbyte 2 Kbyte ATmega644P 64 Kbyte 2 Kbyte 4 Kbyte

2.3 Pin Descriptions

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

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2.3.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Conver ter. Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-st ated when a reset co ndition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 80.

2.3.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 82.

ATmega164P/324P/644P

2.3.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the ATmega164P/324P/644P as listed on page 85.

2.3.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port D also serves the functions of various special features of the ATmega164P/324P/644P as listed on page 87.

2.3.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 331. Shorter pulses are not guaranteed to generate a rese t.

2.3.8 XTAL1

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Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

ATmega164P/324P/644P

2.3.9 XTAL2

2.3.10 AVCC

2.3.11 AREF

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the Analog-to-digital Convert er. It should be exte rnally connected to V to V

through a low-pass filter.

, even if the ADC is not used. If the ADC is used, it should be connected

This is the analog reference pin for the Analog-to-digital Converter.

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3. Resources

ATmega164P/324P/644P

A comprehensive set of development tools, application notes and datasheetsare available for download on http://www.atmel.com/avr.

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ATmega164P/324P/644P

4. About Code Examples

This documentation contains simple code examples t hat brief ly show h ow to us e various parts of the device. Be aware that not all C compiler vendors include bit def initions in the header files and interrupt handling in C is compiler dependent . Please con firm wit h the C com piler d ocume ntation for more details.

The code examples assume that the part specific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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6. AVR CPU Core

6.1 Overview

ATmega164P/324P/644P

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

Figure 6-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Status

and Control

32 x 8 General Purpose

Registrers

ALU

Indirect Addressing

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

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I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ATmega164P/324P/644P

ical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointe rs can also be used as an address pointe r for look up tables in Flash pr ogram memory. Thes e added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the AL U. After an arith metic operation, the Status Register is updated to reflect informat ion about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Prog ram Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164P/324P/644P has Extended I/O space from 0x60 - 0xFF in SRAM where o nly the ST/STS/STD and LD/LDS/LDD instructions can be used.

6.2 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are execut ed . The ALU ope ra tio ns are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

6.3 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as

8011G–AVR–08/07

specified in the Instruction Set Refe rence. This wil l in many cases remove the n eed for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be hand le d by so ftware.

6.3.1 SREG – Status Register

The AVR Status Register – SREG – is defined as:

Bit 76543210 0x3F (0x5F) ITHSVNZCSREG Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

ATmega164P/324P/644P

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

ATmega164P/324P/644P

6.4 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to ach ieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit resu lt input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16 -bit output operand and one 16-bit result input

Figure 6-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 6-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

70Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 6-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

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6.4.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 6-3.

Figure 6-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 707 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 707 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 70 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these addr ess regist er s have fun cti ons a s fi xed d isp lacement , automatic increment, and automatic decrement (see the instruction set reference for details).

ATmega164P/324P/644P

6.5 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is imp lemented as growing f rom higher memor y locations to lower memory locations. This implies that a Stack PUSH co mmand decr eases th e Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

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ATmega164P/324P/644P

6.5.1 SPH and SPL – Stack Pointer High and Stack pointer Low

Bit 151413121110 9 8 0x3E (0x5E) – – – SP12 SP11 SP10 SP9 SP8 SPH 0x3D (0x5D) SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R R R R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0/0/1

11111111

Note: 1. Initial values respectively for the ATmega164P/324P/644P.

6.5.2 RAMPZ – Extended Z-pointer Register for ELPM/SPM

Bit 765432 1 0 0x3B (0x5B) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value000000 0 0

RAMPZ7 RAMPZ6 RAMPZ5 RAMPZ4 RAMPZ3 RAMPZ2 RAMPZ1 RAMPZ0

For ELPM/SPM instructions, the Z-pointer is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 6-4. Note that LPM is not affected by the RAMPZ setting.

Figure 6-4. The Z-pointer used by ELPM and SPM

(1)

0/1/0

(1)

1/0/0

(1)

RAMPZ

Bit ( Individually)

Bit (Z-pointer) 23 16 15 8 7 0

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero.

6.6 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 6-5 on page 15 shows the parallel instruction fetches and instruction executions enabled

by the Harvard architecture and the fast-access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MH z with the correspo nding unique results for function s per cost, functions per clocks, and functions per power-unit.

707070

RAMPZ ZH ZL

, directly generated from the selected clock source for the

CPU

8011G–AVR–08/07

ATmega164P/324P/644P

Figure 6-5. The Parallel Instruction Fetches and Instruction Executions

T1 T2 T3 T4

clk

CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 6-6 shows the internal timing concept for th e Regi ster File . In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

Figure 6-6. Single Cycle ALU Operation

T1 T2 T3 T4

clk

CPU

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

6.7 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one toge ther with the Glo bal Interru pt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section ”Memory Program-

ming” on page 293 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ”Interrupts” on page 61. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to t he start of the Boot Flash section by setting t he IVSEL bit in the MCU Control Register (MCUCR). Refer to ”Interrupts” on page 61 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see ”Memory Programming” on page 293.

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

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ATmega164P/324P/644P

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to th e flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Int errupt Flags. If the interrup t condition disappears before t he interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt rou tine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used t o a void interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

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Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

6.7.1 Interrupt Response Time

The interrupt execution response for a ll the enabled AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling routine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

ATmega164P/324P/644P

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped bac k from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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ATmega164P/324P/644P

7. AVR Memories

7.1 Overview

This section describes the different memories in the ATmega164P/324P/644P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164P/324P/644P features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

7.2 In-System Reprogrammable Flash Program Memory

The ATmega164P/324P/644P contains 16/32/64K bytes On-chip In-System Reprogrammable Flash memory for program storage . Since all AVR instructio ns are 16 or 32 bits wide, the Flas h is organized as 32/64 x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program sectio n.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATmega164P/324P/644P Program Counter (PC) is 15/16 bits wide, thus addressing the 32/64K program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in ”Memory Programming” o n page 293.

”Memory Programming” on page 293 contains a detailed description on Flash data serial down-

loading using the SPI pins or the JTAG interface. Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description. Timing diagrams for instruction fetch and execution are presented in ”Instruction Execution Tim-

ing” on page 14.

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Figure 7-1. Program Memory Map

Program Memory

Application Flash Section

ATmega164P/324P/644P

0x0000

7.3 SRAM Data Memory

Figure 7-2 shows how the ATmega164P/324P/644P SRAM Memory is organized.

The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 4,352 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 160 locations of Extended I/O memory and the next 4,096 locations address the internal data SRAM.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decremen t, and In direct with Post -incremen t. In the Regist er file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations f rom the base address given

by the Y- or Z-register.

Boot Flash Section

0x1FFF

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When using register indirect addressing modes with automatic pre-decrement and post-increment, the address registers X, Y, and Z are decremented or incremented.

ATmega164P/324P/644P

The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the

F F

T1 T2 T3

1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all these addressing modes. The Register File is described in ”General Purpose Regis-

ter File” on page 12.

Figure 7-2. Data Memory Map

Data Memory

7.3.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

Figure 7-3. On-chip Data SRAM Access Cycles

clk

CPU

ddress

Data

32 Registers

64 I/O Registers

160 Ext I/O Reg.

Internal SRAM

(1024/2048/4096 x 8)

Compute Address

$0000 - $001 $0020 - $005 $0060 - $00F $0100

$10FF

cycles as described in Figure 7-3.

CPU

Address valid

Write

Data

Memory Access Instruction

Read

Next Instruction

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7.4 EEPROM Data Memory

The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 writ e/erase cycles. Th e access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 308, page 312, and page 297 respectively.

7.4.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. See ”Register Description” on

page 23 for details.

The write access time for the EEPROM is given in Table 7-2 on page 25. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V some period of time to run at a voltage lower than specified as minimum for the clock frequency used. See Section “7.4.2” on page 21. for details on how to avoid problems in these situations.

ATmega164P/324P/644P

is likely to rise or fall slowly on power-up/down. This causes the device for

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed. Refer to the description of the EEPROM Control Register for details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

7.4.2 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an exter nal low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

the EEPROM data can be corrupted because the supply voltage is

CC,

reset Protection circuit can

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ATmega164P/324P/644P

7.5 I/O Memory

The I/O space definition of the ATmega164P/324P/644P is shown in ”Register Summary” on

page 413.

All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections. The ATmega164P/324P/644P contains three General Purpose I/O Registers, see ”Register

Description” on page 23. These registers can be used for storing any information, and they are

particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible usin g the SBI, CBI, SBIS, and SBIC instructions.

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7.6 Register Description

7.6.1 EEARH and EEARL – The EEPROM Address Register

Bit 1514131211 10 9 8 0x22 (0x42) – – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH 0x21 (0x41) EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 2 10

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

XXXXX X XX

• Bits 15:12 – Res: Reserved Bits

These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero.

• Bits 11:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be writte n bef ore th e EEPROM may be accessed.

ATmega164P/324P/644P

7.6.2 EEDR – The EEPROM Data Register

Bit 76543210 0x20 (0x40) MSB LSB EEDR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

7.6.3 EECR – The EEPROM Control Register

Bit 76543210 0x1F (0x3F) – – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero.

• Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for the different modes are shown in Table 7-1 on page 24.

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ATmega164P/324P/644P

While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

Table 7-1. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

Time Operation

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SPMEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE. The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, st ep 2 can be o mitted. See ” Memor y Pro-

gramming” on page 293 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

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ATmega164P/324P/644P

When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Registe r, the EERE b it must be writte n to a log ic one t o trigger t he EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-2 on page 25 lists the typical programming time for EEPROM access from the CPU.

Table 7-2. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

26,368 3.3 ms

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ATmega164P/324P/644P

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

(1)

()

Note: 1. See “About Code Examples” on page 8.

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ATmega164P/324P/644P

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

(1)

8011G–AVR–08/07

Note: 1. See “About Code Examples” on page 8.

ATmega164P/324P/644P

7.6.4 GPIOR2 – General Purpose I/O Register 2

Bit 76543210 0x2B (0x4B) MSB LSB GPIOR2 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

7.6.5 GPIOR1 – General Purpose I/O Register 1

Bit 76543210 0x2A (0x4A) MSB LSB GPIOR1 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

7.6.6 GPIOR0 – General Purpose I/O Register 0

Bit 76543210 0x1E (0x3E) MSB LSB GPIOR0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

Note: 1. SR Wn1 = SRW11 (upper sector) or SRW01 (lo wer sector), SRWn0 = SR W10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

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8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

Figure 8-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consump tion, th e cloc ks to modules not being used can be halted by using different sleep modes, as described in ”Power Manage-

ment and Sleep Modes” on page 42. The clock systems are detailed below.

Figure 8-1. Clock Distribution

Asynchronous Timer/Counter

General I/O

Modules

ADC

ATmega164P/324P/644P

CPU Core RAM

clk

ADC

Flash and EEPROM

8.1.1 CPU Clock – clk

CPU

Timer/Counter

Oscillator

clk

I/O

clk

ASY

External Clock

AVR Clock Control Unit

Source clock

System Clock

Prescaler

Clock

Multiplexer

Crystal

Oscillator

clk

CPU

clk

FLASH

Reset Logic

Watchdog Timer

Watchdog clock

Watchdog

Oscillator

Low-frequency

Crystal Oscillator

Calibrated RC

Oscillator

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

8.1.2 I/O Clock – clk

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I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detectio n in the USI module is carried ou t asynchronously when clk

is halted, TWI address recognition in all sleep modes.

I/O

ATmega164P/324P/644P

8.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash inte rface. The Fla sh clock is usually active simultaneously with the CPU clock.

FLASH

8.1.4 Asynchronous Timer Clock – clk

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

8.1.5 ADC Clock – clk

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital cir cuit ry. Th is gives mo re accurat e ADC conversion results.

8.2 Clock Sources

The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected so ur ce is i npu t to th e AVR clo c k gene ra to r, and r ou te d to t he appropriate modules.

Table 8-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

Low Power Crystal Oscillator 1111 - 1000 Full Swing Crystal Oscillator 0111 - 0110 Low Frequency Crystal Oscillator 0101 - 0100

ASY

(1)

Internal 128 kHz RC Oscillator 0011 Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0001

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

8.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source set ting usi ng any available program ming interf ace.

8.2.2 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.

To ensure sufficient V the device reset is released by all other reset sources. ”On-chip Debug System” on page 46 describes the start conditions for the in ternal r eset. The delay ( t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The

to start oscillating and a minimum number of oscillating

, the device issues an internal reset with a time-out delay (t

) is timed from the Watchdog

TOUT

) after

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ATmega164P/324P/644P

selectable delays are shown in Table 8-2. The frequency of the Watchdog Oscillator is voltage dependent as shown in ”Typical Characteristics” on page 338.

Table 8-2. Number of Watchdog Oscillator Cycles

Typ Time-o ut (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit sh ould be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power -save or Po wer- do wn mode , Vcc is assumed to be at a sufficient level and only the start-up time is included.

8.2.3 Clock Source Connections

The pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 8-2 on page 31. Either a quartz crystal or a ceramic resonator may be used.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment . For cer amic resonators, t he capacitor values given by the manufacturer should be used.

Figure 8-2. Crystal Oscillator Connections

XTAL

GND

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ATmega164P/324P/644P

8.3 Low Power Crystal Oscillator

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, re fer t o th e ”Full Swing

Crystal Oscillator” on page 33.

Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-3. The crystal should be connected as described in ”Clock Source Connections” on page 31.

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-3.

Table 8-3. Low Power Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1

Frequency Range (MHz) CKSEL3..1

0.4 - 0.9 100

(2)

(3)

(1)

and C2 (pF)

–

0.9 - 3.0 101 12 - 22

3.0 - 8.0 110 12 - 22

8.0 - 16.0 111 12 - 22

Notes: 1. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

2. This is the recommended CKSEL settings for the different frequency ranges.

3. This option should not be used with crystals, only with ceramic resonators.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

8-4.

Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Start-up Time from

Power-down and

Power-save

258 CK 14CK + 4.1 ms

258 CK 14CK + 65 ms

Additional Delay

from Reset

= 5.0V) CKSEL0 S UT1..0

(1)

000

001

Ceramic resonator, BOD enabled

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

1K CK 14CK

(2)

1K CK 14CK + 4.1 ms

1K CK 14CK + 65 ms

010

(2)

011

100

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Table 8-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection (Continued)

Oscillator Source / Power Conditions

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with cer amic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

8.4 Full Swing Crystal Oscillator

This Crystal Oscillator is a full swing oscillator, with rail-to-rail swing on the XTAL2 output. This is useful for driving other clock inputs and in noisy environments. The current consumption is higher than the ”Low Power Crystal Oscillator” on page 32. Note that the Full Swing Crystal Oscillator will only operate for Vcc = 2.7 - 5.5 volts.

Start-up Time from

Power-down and

Power-save

16K CK 14CK 1 01

16K CK 14CK + 4.1 ms 1 10

16K CK 14CK + 65 ms 1 11

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 S UT1..0

Some initial guidelines for choosing capacitors for use with crystals are given in Table 8-6. The crystal should be connected as described in ”Clock Source Connections” on page 31.

The operating mode is selected by the fuses CKSEL3..1 as shown in Table 8-5.

Table 8-5. Full Swing Cry stal Oscillator Operating Modes

Frequency Range

Notes: 1. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

(1)

(MHz) CKSEL3..1

0.4 - 20 011 12 - 22

Recommended Range for Capacitors C1

and C2 (pF)

Table 8-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Start-up Time from

Power-down and

Power-save

258 CK 14CK + 4.1 ms

258 CK 14CK + 65 ms

1K CK 14CK

Additional Delay

from Reset

= 5.0V) CKSEL0 SUT1..0

(1)

(2)

000

001

010

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ATmega164P/324P/644P

Table 8-6. Start-up Times for the Full Swing Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

8.5 Low Frequency Crystal Oscillator

Start-up Time from

Power-down and

Power-save

1K CK 14CK + 4.1 ms

1K CK 14CK + 65 ms

16K CK 14CK 1 01

16K CK 14CK + 4.1 ms 1 10

16K CK 14CK + 65 ms 1 11

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

(2)

011

100

The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega164P/324P/644P oscillator is optimized for very low power consumption, and thus when selecting crystals, see Table 8-7 on page 34 for maximum ESR recommendations on 9 pF and

12.5 pF crystals

Table 8-7. Maximum ESR Recommendation for 32.768 kHz Watch Crystal

Crystal CL (pF) Max ESR [kΩ]

9.0 65

12.5 30

Note: 1. Maximum ESR is typical value based on characterization

(1)

The Low-frequency Crystal Oscillator provides an internal load capacitance of typical 8.0 pF. Crystals with recommended 8.0 pF load capacitance can be without external capacitors as shown in Figure 8-3 on page 35.

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ATmega164P/324P/644P

Figure 8-3. Crystal Oscillator Connections

TOSC

Crystals specifying load capacitance (CL) higher t han 8.0 pF , require e xternal capa citors ap plied as described in Figure 8-2 on page 31.

To find suitable load capacitance for a 32.768 kHz crysal, please consult the crystal datasheet. When this oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL 0

as shown in Table 8-8.

Table 8-8. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power-down and

Power Conditions

BOD enabled 1K CK 14CK Fast rising power 1K CK 14CK + 4.1 ms Slowly rising power 1K CK 14CK + 65 ms

BOD enabled 32K CK 14CK 1 00 Fast rising power 32K CK 14CK + 4.1 ms 1 01 Slowly rising power 32K CK 14CK + 65 ms 1 10

Note: 1. These options should only be used if frequency stability at start-up is not important for the

application.

Power-save

Reserved 0 11

Reserved 1 11

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

(1)

000 001 010

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8.6 Calibrated Internal RC Oscillator

By default, the Internal RC Oscillator provides an approximate 8 MHz clock. Though voltage and temperature dependent, this clock can be very accurately calibrated by the the user. See Table

27-4 on page 330 and ”Internal Oscillator Speed” on page 356 and page 380 for more details.

The device is shipped with the CKDIV8 Fuse programmed. See ”System Clock Prescaler” on

page 38 for more details.

This clock may be selected as the system cloc k by p rogr am m in g th e CKS E L Fus es a s sh own in

Table 8-9. If selected, it will operate with no external components. During reset, hardware loads

the pre-programmed calibration value into th e OSCCAL Re giste r a nd the reby aut omat ica lly calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in

Table 27-4 on page 330.

By changing the OSCCAL register from SW, see ”OSCCAL – Oscillator Calibration Register” on

page 40, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 27-4 on page 330. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed calibration value, see the section ”Calibration Byte” on page 296.

Table 8-9. Internal Calibrated RC Oscillator Operating Modes

Frequency Range

(2)

(MHz) CKSEL3..0

7.3 - 8.1 0010

(1)

Notes: 1. The device is shipped with this option selected.

2. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8 Fuse can be programmed in order to divide the internal frequency by 8.

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-10 on page 36.

Table 8-10. Start-up times for the Internal Calibrated RC Oscillator clock selection

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10

Note: 1. The device is shipped with this option selected.

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

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8.7 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “0011” as shown in Table 8-11.

ATmega164P/324P/644P

8.8 External Clock

Table 8-11. 128 kHz Internal Oscillator Operating Modes

Nominal Frequency CKSEL3..0

128 kHz 0011

Note: 1. Note that the 128kHz oscillator is a very low power clock source, and is not designed for high

accuracy.

(2)

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-12.

Table 8-12. Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4 ms 01 Slowly rising power 6 CK 14CK + 64 ms 10

down and Power-save

Reserved 11

Additional Delay from

Reset SUT1..0

To drive the device from an external clock source, XTAL1 should be driven as shown in Figure

8-4. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”.

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Figure 8-4. External Clock Drive Configuration

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 8-14.

Table 8-13. Crystal Oscillator Clock Frequency

Nominal Frequency CKSEL3..0

0 - 20 MHz 0000

ATmega164P/324P/644P

Table 8-14. Start-up Times for the External Clock Selection

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-ti me changes of the int ernal clock frequency while still ensuring stable operation. Refer to ”System Clock Prescaler” on page

38 for details.

8.9 Timer/Counter Oscillator

ATmega164P/324P/644P uses the same type of crystal oscillator for Low-frequency Crystal Oscillator and Timer/Counter Oscillator. See ”Low Frequency Crystal Oscillator” on page 34 for details on the oscillator and crystal requirements.

The device can operate its Timer/Counter2 from an exte rnal 32.768 kHz watch crystal or a external clock source. See ”Clock Source Connections” on page 31 for details.

Start-up Time from Power-

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is written to logic one. See ”The Output Compare Register B contains an 8-bit value that is contin-

uously compared with the counter value (TCNT2). A match can be used to generate an Output Compare interrupt, or to generate a waveform output on the OC2B pin.” on page 157 for further

description on selecting external clock as input instead of a 32.768 kHz watch crystal.

8.10 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suit able when the chip clock is u sed to drive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

8.11 System Clock Prescaler

The ATmega164P/324P/644P has a system clock prescaler, and the system clock can be divided by setting the ”CLKPR – Clock Prescale Register” on page 40. This feature can be used to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk are divided by a factor as shown in Table 8-15 on page 41.

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also en sures th at no in te rme diate freq ue ncy is higher t han

I/O

, clk

ADC

, clk

CPU

, and clk

FLASH

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ATmega164P/324P/644P

neither the clock frequency corresponding to the pr eviou s sett ing, nor t he clock fr equency co rr esponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure t he write procedur e is not interrupted.

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ATmega164P/324P/644P

8.12 Register Description

8.12.1 OSCCAL – Oscillator Calibration Register

Bit 76543210 (0x66) CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. A pre-programmed calibration value is automatically written to this register during chip reset, giving the Factory calibrated frequency as specified in Table 27-4 on page 330. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 27-

4 on page 330. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that r ange, and a setting of 0x7F g ives the high est freq uency in the range.

8.12.2 CLKPR – Clock Prescale Register

Bit 76543210 (0x61) Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 See Bit Description

CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 CLKPR

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Selec t Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to t he MCU, the speed o f all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 8-15 on page 41.

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ATmega164P/324P/644P

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

Table 8-15. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

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ATmega164P/324P/644P

9. Power Management and Sleep Modes

9.1 Overview

Sleep modes enable the application to shut down unused modules in the MCU, thereby savingpower. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s require m en ts .

When enabled, the Brown-out Detector (BOD) actively monitors the power supply volta ge dur ing the sleep periods. To further save power, it is possib le to d isable the BOD in some sleep modes. See ”BOD Disable” on page 43 for more details.

9.2 Sleep Modes

Figure 8-1 on page 29 presents the different clo ck systems in the ATmega1 64P/324P/64 4P, and

their distribution. The figure is helpful in selecting an appropriate sleep mode. Table 9-1 shows the different sleep modes, their wake up sources and BOD disable ability.

Table 9-1. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

CPU

FLASH

Sleep Mode

Idle X X X X X ADCNRM X X X X Power-down X Power-save X X Standby

(1)

Extended Standby

clk

clkIOclk

ADC

ASY

Software

clk

Main Clock

Source

Enabled

Timer Osc

Enabled

INT2:0 and

Pin Change

TWI Address

Match

Timer2

SPM/

EEPROM Ready

ADC

WDT Interrupt

(2)

XXXXXXX

(2)X(3)

(3)

(2)X(3)

(2)

(3)

(2)X(3)

(2)

XXX XXX XX X X XXX

XX X X

Other I/O

BOD Disdable

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT0, only level interrupt.

To enter any of the sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruction. See Table 9-2 on page 47 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from slee p. I f a r eset occurs d uri ng sle ep mode, the MCU wakes up and executes from the Reset Vector.

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9.3 BOD Disable

9.4 Idle Mode

ATmega164P/324P/644P

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 26-3 on page 294, the BOD is actively monitoring the power supply voltage during a sleep period. To save power, it is possible to disable the BOD by software for some of the sleep modes, see Table 9-1 on page

42. The sleep mode power consumption will then be at the same level as when BOD is globally

disabled by fuses. If BOD is disabled in software, the BOD function is turned off immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe operation in case the V

When the BOD has been disabled, the wake-up time from sleep mode will be approximately 60 µs to ensure that the BOD is working correctly before the MCU continues executing code.

BOD disable is controlled by bit 6, BODS (B OD Sleep) in the control register MCUCR, see

”MCUCR – MCU Control Register” on page 48. Writing this bit to one turns off the BOD in rele-

vant sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e. BODS set to zero.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see ”MCUCR –

MCU Control Register” on page 48.

level has dropped during the sleep period.

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the inter ru pt syste m to con tinue o pe ratin g. This sleep mode basically halts clk

Idle mode enables the MCU to wake up from external triggered interrupts as well a s internal ones like the Timer Overflow and USART Transmit Complete interru pts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be po wered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

9.5 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is e ntered. Apart fo rm the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial inte rface interrupt, a Timer/Counter 2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU from ADC Noise Reduction mode.

CPU

and clk

, while allowing the other clocks to run.

FLASH

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ATmega164P/324P/644P

9.6 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2wire Serial Interface, and the Watchdog continu e oper at ing (i f enab led ). Only an Exter nal Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on PCINT7:4, an external interrupt on INT2:0, or a pin change interrupt can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to ”External Interrupts” on page 67 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in ”Clock Sources” on page 30.

9.7 Power-save Mode

When the SM2:0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down, with one exception:

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2.

9.8 Standby Mode

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

9.9 Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.

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9.10 Power Reduction Register

The Power Reduction Register(PRR), see ”PRR – Power Reduction Register” on page 48, pro- vides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a peripheral, which is done by clearing the bit in PRR, puts the peripheral in the same state as before shutdown.

Peripheral shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. In all other sleep modes, the clock is already stopped.

9.11 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

9.11.1 Analog to Digital Converter

ATmega164P/324P/644P

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to ”ADC - Analog-to-digital Converter” on page

240 for details on ADC operation.

9.11.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independe nt of sleep mode. Refer to ”AC - Analog Comparator” on page 237 for details on how to configure the Analog Comparator.

9.11.3 Brown-out Detector

If the Brown-out Detector is not needed by the a pplication, this module sh ould be turned off. If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Brown-out Detection” on page 53 for details on how to configure the Brown-out Detector.

9.11.4 Internal Voltage Reference

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The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to ”Internal Volt-

age Reference” on page 54 for details on the start-up time.

ATmega164P/324P/644P

9.11.5 Watchdog Timer

If the Watchdog Timer is not needed in t he application, the m odule should be tu rned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to ”Interrupts” on page 61 for details on how to configure the Watchdog Timer.

9.11.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section ”Digital Input Enable and Sleep Modes” on page 76 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to ”DIDR1 – Digital Input Disable Register 1” on page 239 and ”DIDR0 – Digital

Input Disable Register 0” on page 259 for details.

9.11.7 On-chip Debug System

) and the ADC clock (clk

I/O

/2, the input buffer will use excessive power.

/2 on an input pin can cause significant current even in active mode. Digital

) are stopped, the input buffers of the device will

ADC

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

There are three alternative ways to disable the OCD system:

• Disable the OCDEN Fuse.

• Disable the JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

8011G–AVR–08/07

9.12 Register Description

9.12.1 SMCR – Sle ep Mod e Co nt rol Register

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210 0x33 (0x53) ––––SM2SM1SM0SESMCR Read/Write RRRRR/WR/WR/WR/W Initial Value00000000

• Bits 3, 2, 1 – SM2:0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the five available sleep modes as shown in Table 9-2.

Table 9-2. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle 0 0 1 ADC Noise Reduction 010Power-down 011Power-save 100Reserved

ATmega164P/324P/644P

101Reserved 110Standby 1 1 1 Extended Standby

Note: 1. Standby modes are only recommended for use with external crystals or resonators.

(1)

• Bit 0 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when th e SLEEP instruction is executed. To avoid the MCU enteri ng th e sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enable (SE) b it to one just befor e the exe cution of the SLEEP instruction and to clear it immediately after waking up.

8011G–AVR–08/07

ATmega164P/324P/644P

9.12.2 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

• Bit 6 – BODS: BOD Sleep

The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 9-1

on page 42. Writing to the BODS bit is controlled by a timed sequence and an enable bit,

BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be set to zero within four clock cycles.

The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for the actual sleep mode . The BODS bit is automatically cleared after three clock cycles.

• Bit 5 – BODSE: BOD Sleep Enable

BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD disab le is controlled by a timed sequence.

9.12.3 PRR – Power Reduction Register

Bit 7 6 5 4 3 2 1 0 (0x64) PRTWI PRTIM2 PRTIM0 PRUSART1 PRTIM1 PRSPI PRUSART0 PRADC PRR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down th e Timer /Coun ter2 mo dule in synchronous mo de (AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 4 - PRUSART1: Power Reduction USART1

Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be reinitialized to ensure proper operation.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

8011G–AVR–08/07

ATmega164P/324P/644P

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.

• Bit 1 - PRUSART0: Power Reduction USART0

Writing a logic one to this bit shuts down the USART0 by stopping the clock to the module. When waking up the USART0 again, the USART0 should be reinitialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts do wn the ADC. The ADC mu st be disabled b efore shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

8011G–AVR–08/07

ATmega164P/324P/644P

10. System Control and Reset

10.0.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 10-1 on page 51 shows the reset logic. ”System and Reset Charac teristics” on page 331 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in ”Clock Sources” on page 30.

10.0.2 Reset Sources

The ATmega164P/324P/644P has five sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply v oltage V threshold (V

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one of the scan chains of the JTAG system. Refer to the section ”IEEE 1149.1 (JTAG) Boundary-

scan” on page 266 for details.

POT

BOT

) and the Brown-out Detector is enabled.

pin for longer than

is below the Brown-out Rese t

8011G–AVR–08/07

Figure 10-1. Reset Logic

Power-on Reset

Circuit

ATmega164P/324P/644P

DATA BU S

MCU Status

JTRF

BORF

PORF

WDRF

EXTRF

10.0.3 Power-on Reset

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Brown-out

Reset Circuit

Watchdog Oscillator

Clock

Generator

CKSEL[3:0]

SUT[1:0]

Delay Counters

TIMEOUT

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in ”System and Reset Characteristics” on page 331. The POR is activated whenever V

is below the detection level. The POR circuit can be used to trigger the start-up Reset, as

well as to detect a failure in supply voltage.

8011G–AVR–08/07

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V

decreases below the detection level.

rise. The RESET signal is activated again, without any delay,

ATmega164P/324P/644P

Figure 10-2. MCU Start-up, RESET Tied to V

RESET

IME-OUT

NTERNAL

POT

RST

TOUT

Figure 10-3. MCU Start-up, RESET Extended Externally

RESET

IME-OUT

POT

RST

TOUT

10.0.4 External Reset

NTERNAL

RESET

An External Reset is generated by a low level on the RESET

pin. Reset pulses longer than the minimum pulse width (see ”System and Reset Characteristics ” on page 331) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V delay counter starts the MCU after the Time-out period – t

TOUT –

– on its positive edge, the

RST

has expired.

Figure 10-4. External Reset During Operation

8011G–AVR–08/07

10.0.5 Brown-out Detection

ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V

level during operation by comparing it to a fixed trigger level. The trigger level for the BOD

can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the det ection leve l should be interp rete d as V V

BOT

When the BOD is enabled, and V

10-5 on page 53), the Brown-out Reset is imme diatel y activate d. Wh en V

trigger level (V out period t

The BOD circuit will only detect a drop in V longer than t

Figure 10-5. Brown-out Reset During Operation

+ V

HYST

/2 and V

TOUT

BOD

ATmega164P/324P/644P

= V

BOT-

in Figure 10-5 on page 53), the delay counter starts the MCU after the Time-

BOT+

has expired.

given in ”System and Reset Characteristics” on page 331.

BOT

- V

/2.

HYST

decreases to a value below the trigger level (V

if the voltage stays below the trigger level for

BOT-

increases above the

BOT+

in Figure

10.0.6 Watchdog Reset

RESET

IME-OUT

NTERNAL

RESET

BOT-

BOT+

TOUT

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

TOUT

. Refer to

page 61 for details on operation of the Wat chdog Timer.

Figure 10-6. Watchdog Reset During Operation

8011G–AVR–08/07

ATmega164P/324P/644P

10.1 Internal Voltage Reference

ATmega164P/324P/644P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

10.1.1 Voltage Refe rence Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. T he start-up time is given in ”System and Reset Characteristics” on page 331. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit i n ACSR) .

3. When the ADC is enabled. Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

8011G–AVR–08/07

10.2 Watchdog Timer

10.2.1 Features

•

• 3 Operating modes

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog al ways on (WDTON) for fail-safe mode

10.2.2 Overview

ATmega164P/324P/644P has an Enhanced Watchdog Timer (WDT). The WDT is a timer co unting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

Figure 10-7. Watchdog Timer

ATmega164P/324P/644P

Clocked from separate On-chip Oscillator

–Interrupt – System Reset – Interrupt and System Reset

128kHz

OSCILLATOR

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0

WATCHDOG RESET

WDE

WDIF

WDIE

WDP1 WDP2 WDP3

MCU RESET

INTERRUPT

In Interrupt mode, the WDT gives an interrupt when the time r expires. This int errupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, th e WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

8011G–AVR–08/07

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing WDE and changing time-out configuration is as follows:

ATmega164P/324P/644P

1. In the same operation, write a logic one to the W atchd og change enab le bit (WDCE) and

WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) as

desired, but with the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example

(1)

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note: 1. The example code assumes that the part specific header fi le is included.

8011G–AVR–08/07

ATmega164P/324P/644P

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is n ot set up to handle the Watchdog, this might lead to an etern al loop of time-out resets. To avoid t his situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

Assembly Code Example

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

out WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

(1)

8011G–AVR–08/07

Note: 1. The example code assumes that the part specific header fi le is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

ATmega164P/324P/644P

10.3 Register Description

10.3.1 MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU reset.

Bit 76543210 0x34 (0x54) Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

– – – JTRF WDRF BORF EXTRF PORF MCUSR

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag. To make use of the Reset Flags to identify a reset condition, the user should read and then

Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

8011G–AVR–08/07

10.3.2 WDTCSR – Watchdog Timer Control Register

Bit 76543210 (0x60) WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value0000X000

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, WDIF is clear ed by writing a logic on e to the f lag. Whe n the I-bi t in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed .

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Re gister is set, the Wa tchdog Interr upt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should h owever not be done within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

ATmega164P/324P/644P

Table 10-1. Watchdog Timer Configuration

WDTON WDE WDIE Mode Action on Time-out

1 0 0 Stopped None 1 0 1 Interrupt Mode Interrupt 1 1 0 System Reset Mode Reset

111

0 x x System Reset Mode Reset

Interrupt and System Reset Mode

Interrupt, then go to System Reset Mode

• Bit 4 - WDCE: Watchdog Change Enable

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensur es multiple reset s during co nditions causing failure, and a safe start-up after the failure.

8011G–AVR–08/07

ATmega164P/324P/644P

• Bit 5, 2:0 - WDP3:0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in

Table 10-2 on page 60.

Table 10-2. Watchdog Timer Prescale Select

Number of WDT Oscillator

WDP3 WDP2 WDP1 WDP0

0000 2K (2048) cycles 16 ms 0001 4K (4096) cycles 32 ms 0010 8K (8192) cycles 64 ms 0011 16K (16384) cycles 0.125 s 0100 32K (32768) cycles 0.25 s 0101 64K (65536) cycles 0.5 s 0110 128K (131072) cycles 1.0 s 0111 256K (262144) cycles 2.0 s 1000 512K (524288) cycles 4.0 s 10011024K (1048576) cycles 8.0 s 1010 1011 1100 1101 1110 1111

Cycles

Reserved

Typical Time-out at

VCC = 5.0V

8011G–AVR–08/07

11. Interrupts

11.1 Overview

This section describes the specifics of the interrupt handling as performed in ATmega164P/324P/644P. For a general explanation of the AVR interrupt handling, refer to

”Reset and Interrupt Handling” on page 15.

11.2 Interrupt Vector s in ATmega164P/324P/644P

Table 11-1. Reset and Interrupt Vectors

ATmega164P/324P/644P

Vector

No.

1 $0000

2 $ 0002 INT0 External Interrupt Request 0 3 $ 0004 INT1 External Interrupt Request 1 4 $ 0006 INT2 External Interrupt Request 2 5 $ 0008 PCINT0 Pin Change Interrupt Request 0 6 $ 000A PCINT1 Pin Change Interrupt Request 1 7 $ 000C PCINT2 Pin Change Interrupt Request 2 8 $ 000E PCINT3 Pin Change Interrupt Request 3

9 $ 0010 WDT Watchdog Time-out Interrupt 10 $0012 TIMER2_COMPA Timer/Counter2 Compare Match A 11 $0014 TIMER2_COMPB Timer/Counter2 Compare Match B 12 $0016 TIMER2_OVF Timer/Counter2 Overflow 13 $0018 TIMER1_CAPT Timer/Counter1 Capture Event 14 $001A TIMER1_COMPA Timer/Counter1 Compare Match A 15 $001C TIMER1_COMPB Timer/Counter1 Compare Match B 16 $001E TIMER1_OVF Timer/Counter1 Overflow 17 $0020 TIMER0_COMPA Timer/Counter0 Compare Match A

Program

Address

(1)

(2)

Source Interrupt Definition

RESET

External Pin, Power-on Reset, Brown-out Reset , Watchdog Reset, and JTAG AVR Reset

8011G–AVR–08/07

18 $0022 TIMER0_COMPB Timer/Counter0 Compare match B 19 $0024 TIMER0_OVF Timer/Counter0 Overflow 20 $0026 SPI_STC SPI Serial Transfer Complete 21 $0028 USART0_RX USART0 Rx Complete 22 $002A USART0_UDRE USART0 Data Register Empty 23 $002C USART0_TX USART0 Tx Complete 24 $002E ANALOG_COMP Analog Comparator 25 $0030 ADC ADC Conversion Complete 26 $0032 EE_READY EEPROM Ready 27 $0034 TWI 2-wire Serial Interface

ATmega164P/324P/644P

Table 11-1. Reset and Interrupt Vectors (Continued)

Vector

No.

28 $0036 SPM_READY Store Program Memory Ready 29 $0038 USART1_RX USART1 Rx Complete 30 $003A USART1_UDRE USART1 Data Register Empty 31 $003C USART1_TX USART1 Tx Complete

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

Program

Address

reset, see ”Memory Programming” on page 293.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

(2)

Source Interrupt Definition

Table 11-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program co de can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

Table 11-2. Reset and Interrupt Vectors Placement

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boot Reset Address 0x0002

(1)

0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 25-7 on page 288. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega164P/324P/644P is:

Address Labels Code Comments 0x0000 jmp RESET ; Reset 0x0002 jmp INT0 ; IRQ0 0x0004 jmp INT1 ; IRQ1 0x0006 jmp INT2 ; IRQ2 0x0008 jmp PCINT0 ; PCINT0 0x000A jmp PCINT1 ; PCINT1 0x000C jmp PCINT2 ; PCINT2 0x000E jmp PCINT3 ; PCINT3 0x0010 jmp WDT ; Watchdog Timeout 0x0012 jmp TIM2_COMPA ; Timer2 CompareA 0x0014 jmp TIM2_COMPB ; Timer2 CompareB 0x0016 jmp TIM2_OVF ; Timer2 Overflow 0x0018 jmp TIM1_CAPT ; Timer1 Capture 0x001A jmp TIM1_COMPA ; Timer1 CompareA 0x001C jmp TIM1_COMPB ; Timer1 CompareB 0x001E jmp TIM1_OVF ; Timer1 Overflow 0x0020 jmp TIM0_COMPA ; Timer0 CompareA

8011G–AVR–08/07

ATmega164P/324P/644P

0x0022 jmp TIM0_COMPB ; Timer0 CompareB 0x0024 jmp TIM0_OVF ; Timer0 Overflow 0x0026 jmp SPI_STC ; SPI Transfer Complete 0x0028 jmp USART0_RXC ; USART0 RX Complete 0x002A jmp USART0_UDRE ; USART0,UDR Empty 0x002C jmp USART0_TXC ; USART0 TX Complete 0x002E jmp ANA_COMP ; Analog Comparator 0x0030 jmp ADC ; ADC Conversion Complete 0x0032 jmp EE_RDY ; EEPROM Ready 0x0034 jmp TWI ; 2-wire Serial 0x0036 jmp SPM_RDY ; SPM Ready 0x0038 jmp USART1_RXC ; USART1 RX Complete 0x003A jmp USART1_UDRE ; USART1,UDR Empty 0x003C jmp USART1_TXC ; USART1 TX Complete ; 0x003E RESET: ldi r16,

high(RAMEND)

0x003F out SPH,r16 ; Set Stack Pointer to

0x0040 ldi r16,

low(RAMEND) 0x0041 out SPL,r16 0x0042 sei ; Enable interrupts 0x0043 <instr> xxx

... ... ... ...

; Main program start

top of RAM

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

0x00000 RESET: ldi r16,high(RAMEND); Main program start

0x00001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x00002 ldi r16,low(RAMEND)

0x00003 out SPL,r16 0x00004 sei ; Enable interrupts

0x00005 <instr> xxx

;

.org 0x1F002

0x1F002 jmp EXT_INT0 ; IRQ0 Handler

0x1F004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x1FO36 jmp SPM_RDY ; SPM Ready Handler

When the BOOTRST Fuse is programmed and the Boot section size set to 8K bytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

.org 0x0002

0x00002 jmp EXT_INT0 ; IRQ0 Handler

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ATmega164P/324P/644P

0x00004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x00036 jmp SPM_RDY ; SPM Ready Handler

;

.org 0x1F000 0x1F000 RESET: ldi r16,high(RAMEND); Main program start

0x1F001 out SPH,r16 ; Set Stack Pointer to top of RAM

0x1F002 ldi r16,low(RAMEND)

0x1F003 out SPL,r16 0x1F004 sei ; Enable interrupts

0x1F005 <instr> xxx

When the BOOTRST Fuse is programmed, the Boot section size set to 8K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup for the Reset and Interrupt Vector Addresses is:

Address Labels Code Comments

;

.org 0x1F000 0x1F000 jmp RESET ; Reset handler 0x1F002 jmp EXT_INT0 ; IRQ0 Handler

0x1F004 jmp EXT_INT1 ; IRQ1 Handler

... ... ... ;

0x1F036 jmp SPM_RDY ; SPM Ready Handler

;

0x1F03E RESET: ldi r16,high(RAMEND); Main program start

0x1F03F out SPH,r16 ; Set Stack Pointer to top of RAM

0x1F040 ldi r16,low(RAMEND)

0x1F041 out SPL,r16 0x1F042 sei ; Enable interrupts

0x1FO43 <instr> xxx

11.2.1 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

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11.3 Register Description

11.3.1 MCUCR – MCU Control Register

Bit 76543210 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section ”Memory Programming” on p age 293 for details. To avoid unintentional changes of Interr upt Vector tables, a special writ e procedure must be followed to change the IVSEL bit:

a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

ATmega164P/324P/644P

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is programmed,

interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section ”Memory Programming” on page 293 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above . See the following Code Example.

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ATmega164P/324P/644P

Assembly Code Example

Move_interrupts:

; Get MCUCR

in r16, MCUCR

mov r17, r16

; Enable change of Interrupt Vectors

ori r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ori r17, (1<<IVSEL)

out MCUCR, r17

ret

C Code Example

void Move_interrupts(void)

{

uchar temp;

/* GET MCUCR*/

temp = MCUCR;

/* Enable change of Interrupt Vectors */

MCUCR = temp|(1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = temp|(1<<IVSEL);

}

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12. External Interrupts

12.1 Overview

The External Interrupts are triggered by the INT2:0 pin or any of the PCINT31:0 pins. Observe that, if enabled, the interrupts will trigger even if the INT2:0 or PCINT31:0 pins are configured as outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI3 will trigger if any enabled PCINT31:24 pin toggle, Pin change interrupt PCI2 will trigger if any enabled PCINT23:16 pin toggles, Pin change interrupt PCI1 if any enabled PCINT15:8 toggles and Pin change interrupts PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK3, PCMSK2, PCMSK1 and PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT31:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT2:0). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Low level interrupts and the edge interrupt on INT2:0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

ATmega164P/324P/644P

Note that if a level triggered interrupt is used for wake-up from Power -down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in ”System Clock and Clock Options” on page 29.

12.2 Register Description

12.2.1 EICRA – External Interrupt Control Register A

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210 (0x69) – – ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7:6 – Reserved

These bits are reserved in the ATmega164P/324P/644P, and will always read as zero.

• Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Int errupt 2 - 0 Sense Control Bits

The External Interrupts 2 - 0 are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in th e EIMS K is set. Th e leve l and e dges on the e xtern al pins that activate the interrupts are defined in Table 12-1. Edges on INT2..INT0 are registered asynchronously. Pulses on INT2:0 pins wider than the minimum pulse width given in ”External Interrupts

Characteristics” on page 331 will generate an interrupt. Shorter pulses are not guaranteed to

generate an interrupt. If low level interrupt is selected, the low level must be held until the com-

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ATmega164P/324P/644P

pletion of the currently executing instruct ion to gen erate an int errupt . If en abled, a level trig gered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. There fore, it is recommended to first d isable INTn by clearing its Interrupt Enable bit in the EIMSK Register. Then, the I SCn bit can be chang ed. Finally, th e INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Register before the interrupt is re-enabled.

Table 12-1. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request.

Note: 1. n = 2, 1 or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

12.2.2 EIMSK – External Interrupt Mask Register

Bit 76543210 0x1D (0x3D) Read/Write RRRRRR/WR/WR/W Initial Value00000000

– – – – – INT2 INT1 IINT0 EIMSK

• Bits 2:0 – INT2:0: External Interrupt Reques t 2 - 0 Enable

When an INT2:0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Register, EICRA, defines wh et he r the ext er nal inte rr up t is activat ed on ri sin g or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

(1)

12.2.3 EIFR –External Interrupt Flag Register

Bit 76543210 0x1C (0x3C) Read/WriteR/WRRRRR/WR/WR/W Initial Value00000000

• Bits 2:0 – INTF2:0: External Interrupt Flags 2 - 0

When an edge or logic change on the I NT2:0 pin tri ggers a n inter rupt r equest, INTF2: 0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT2:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. The se flags are always cleared when INT2:0 are configured as level interrupt. Note that when entering sleep mode with the INT2:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF2:0 flags. See ”Digital Input

Enable and Sleep Modes” on page 76 for more information.

– – – – – INTF2 INTF1 IINTF0 EIFR

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12.2.4 PCICR – Pin Change Interrupt Control Register

Bit 76543210 (0x68) Read/Write RRRRR/WR/WR/WR/W Initial Value00000000

– – – – PCIE3 PCIE2 PCIE1 PCIE0 PCICR

• Bit 3 – PCIE3: Pin Change Interrupt Enable 3

When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 3 is enabled. Any change on any enabled PCINT31..24 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3 Interrupt Vector. PCINT31..24 pins are enabled individually by the PCMSK3 Register.

• Bit 2 – PCIE2: Pin Change Interrupt Enable 2

When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 2 is enabled. Any change on any enabled PCINT23..16 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2 Interrupt Vector. PCINT23..16 pins are enabled individually by the PCMSK2 Register.

• Bit 1 – PCIE1: Pin Change Interrupt Enable 1

When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1 Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.

ATmega164P/324P/644P

• Bit 0 – PCIE0: Pin Change Interrupt Enable 0

When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an interrupt. The corresponding interrupt of Pin Change Interrupt Request is e xecuted from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.

12.2.5 PCIFR – Pin Change Interrupt Flag Register

Bit 76543210 0x1B (0x3B) Read/Write RRRRR/WR/WR/WR/W Initial Value00000000

• Bit 3– PCIF3: Pin Change Interrupt Flag 3

When a logic change on any PCINT31..24 pin triggers an interrupt request, PCIF3 becomes set (one). If the I-bit in SREG and the PCIE3 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 2 – PCIF2: Pin Change Interrupt Flag 2

When a logic change on any PCINT23..16 pin triggers an interrupt request, PCIF2 becomes set (one). If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

– – PCIF3 PCIF2 PCIF1 PCIF0 PCIFR

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ATmega164P/324P/644P

• Bit 1 – PCIF1: Pin Change Interrupt Flag 1

When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set (one). If the I-bit in SREG and the PCIE1 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

• Bit 0 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

12.2.6 PCMSK3 – Pin Change Mask Register 3

Bit 76543210 (0x73) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PCINT31 PCINT30 PCINT29 PCINT28 PCINT27 PCINT26 PCINT25 PCINT24 PCMSK3

• Bit 7:0 – PCINT31:24: Pin Change Enable Mask 31:24

Each PCINT31:24-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT31:24 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT31..24 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.2.7 PCMSK2 – Pin Change Mask Register 2

Bit 76543210 (0x6D) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PCINT23 PCINT22 PCINT21 PCINT20 PCINT19 PCINT18 PCINT17 PCINT16 PCMSK2

• Bit 7:0 – PCINT23:16: Pin Change Enable Mask 23..16

Each PCINT23:16-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT23:16 is set and the PCIE2 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT23..16 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

12.2.8 PCMSK1 – Pin Change Mask Register 1

Bit 76543210 (0x6C) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

PCINT15 PCINT14 PCINT13 PCINT12 PCINT11 PCINT10 PCINT9 PCINT8 PCMSK1

• Bit 7:0 – PCINT15:8: Pin Change Enable Mask 15..8

Each PCINT15:8-bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT15:8 is set and the PCIE1 bit in EIMSK is set, pin change interr upt is enabled o n the corresponding I/O pin. If PCINT15:8 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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12.2.9 PCMSK0 – Pin Change Mask Register 0

Bit 76543210 (0x6B) PCINT7 PCINT6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0 Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7..0

Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interru p t is en abled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

ATmega164P/324P/644P

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ATmega164P/324P/644P

13. I/O-Ports

13.1 Overview

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/ disabling of p ull-up resist ors (if con figured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

acteristics” on page 325 for a complete list of parameters.

Figure 13-1. I/O Pin Equivalent Schematic

and Ground as indicated in Figure 13-1. Refer to ”Electrical Char-

Pxn

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” rep resents the bit number. However, when using the register or bit defines in a program , the precise form must be used. For examp le, PORTB3 for bit no. 3 in Port B, here documented ge ner ally as PO RTxn . The physical I /O Registers and bit locations are listed in ”Register Description” on page 91.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Data Direction Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in ”Ports as General Digital I/O” on page

73. Most port pins are multiplexed with alternate func tions for the peripheral featur es on the

device. How each alternate function interferes with the port pin is described in ”Alternate Port

Functions” on page 78. Refer to the individual module sections for a full description of the alter-

nate functions.

See Figure

"General Digital I/O" for

Logic

Details

8011G–AVR–08/07

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

13.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 13-2 shows a functional description of one I/O-port pin, here generically called Pxn.

ATmega164P/324P/644P

Figure 13-2. General Digital I/O

Pxn

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk

: I/O CLOCK

I/O

(1)

SLEEP

SYNCHRONIZER

DLQ

PINxn

PUD

DDxn

CLR

RESET

PORTxn

CLR

RESET

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

RRx

WDx

RDx

RPx

clk

I/O

WRx

DATA BUS

WPx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

13.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in ”Register

Description” on page 91, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin h as to be configured as an output pin. The port pi ns are tri-stated when re set condition b ecomes active, even if no clocks are running.

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SLEEP, and PUD are common to all ports.

I/O

ATmega164P/324P/644P

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

13.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

13.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-sta te ({DDxn, PORTxn} = 0b00) o r the o utput high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 13-1 summarizes the control signals for the pin value.

Table 13-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z) 0 1 0 Input Yes Pxn will source current if ext. pulled low.

PUD

(in MCUCR) I/O Pull-up Comment

0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source)

13.2.4 Reading the Pin Value

Independent of the setting of Data Direction b it DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 13-2, t he PINxn Regist er bit a nd th e prece ding latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also intro duces a delay. Fi gure 13-3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are deno te d t

pd,max

and t

respectively.

pd,min

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ATmega164P/324P/644P

Figure 13-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

XXX in r17, PINx

XXX

SYNC LATCH

PINxn

r17

0x00 0xFF

pd, max

pd, min

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 13-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 13-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

INSTRUCTIONS

out PORTx, r16 nop in r17, PINx

0xFF

SYNC LATCH

PINxn

r17

0x00 0xFF

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

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ATmega164P/324P/644P

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

13.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 13-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standb y mode to avoid high power co nsumption if some input signals are left floating, or have an analog signal level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in ”Alternate Port Functions” on page 78.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the extern al interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

/2.

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13.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure t hat these pins have a defi ned level. Even though most of the digital inputs are disabled in th e deep sleep modes as de scribed above, floating inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output.

ATmega164P/324P/644P

or GND is not recommended, since this may caus e excessiv e currents if t he pin is

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ATmega164P/324P/644P

13.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 13-5 shows how the port pin control signals from the simplified Figure 13-2 on page 73 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

Figure 13-5. Alternate Port Functions

Pxn

(1)

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

SYNCHRONIZER

SET

DLQ

CLR

PINxn

CLR

PORTxn

CLR

RESET

DDxn

PUD

CLR

WDx

RDx

RRx

RPx

clk

I/O

WRx

PTOExn

WPx

DATA BUS

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

8011G–AVR–08/07

I/O

ATmega164P/324P/644P

Table 13-2 summarizes the function of the o verridin g signals. Th e pin and por t indexes f rom Fig- ure 13-5 are not shown in the succeeding tables. The overriding signals ar e gen erat ed intern ally

in the modules having the alternate function.

Table 13-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PV OV signal. If PV OE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

PUOE

PUOV

DDOE

DDOV

PVOE

Pull-up Override Enable

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

PVOV

PTOE

DIEOE

DIEOV

DI Digital Input

AIO

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

Digital Input Enable Override Value

Analog Input/Output

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigge r but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bidirectionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

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ATmega164P/324P/644P

13.3.1 Alternate Functions of Port A

The Port A pins with alternate functions are shown in Table 13-3.

Table 13-3. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7

PA6

ADC7 (ADC input channel 7) PCINT7 (Pin Change Interrupt 7)

ADC6 (ADC input channel 6) PCINT6 (Pin Change Interrupt 6)

PA5

PA4

PA3

PA2

PA1

PA0

ADC5 (ADC input channel 5) PCINT5 (Pin Change Interrupt 5)

ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4)

ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3)

ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2)

ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1)

ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0)

• ADC7:0/PCINT7:0 – Port A, Bit 7:0

ADC7:0, Analog to Digital Converter, Channels 7:0

PCINT7:0, Pin Change Interrupt source 7:0: The PA7:0 pins can serve as external interrupt sources.

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ATmega164P/324P/644P

Table 13-4 on page 81 and Table 13-5 on page 81 relates the alternate functions of Port A to the

overriding signals shown in Figure 13-5 on page 78.

Table 13-4. Overriding Signals for Alternate Functions in PA7:PA4

Signal Name

PUOE0000 PUOV0000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE0000 PVOV0000

DIEOE

DIEOV PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0 DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT AIO ADC7 INPUT ADC6 INPUT ADC5 INPUT ADC4 INPUT

PA7/ADC7/ PCINT7

PCINT7 • PCIE0 + ADC7D

PA6/ADC6/ PCINT6

PCINT6 • PCIE0 + ADC6D

PA5/ADC5/ PCINT5

PCINT5 • PCIE0 + ADC5D

PA4/ADC4/ PCINT4

PCINT4 • PCIE0 + ADC4D

Table 13-5. Overriding Signals for Alternate Functions in PA3:PA0

Signal Name

PUOE0000 PUOV0000

PA3/ADC3/ PCINT3

PA2/ADC2/ PCINT2

PA1/ADC1/ PCINT1

PA0/ADC0/ PCINT0

DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE0000 PVOV0000

DIEOE

DIEOV PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT1 • PCIE0 PCINT0 • PCIE0 DI PCINT3 INPUT PCINT2 INPUT PCINT1 INPUT PCINT0 INPUT AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

PCINT3 • PCIE0 + ADC3D

PCINT2 • PCIE0 + ADC2D

PCINT1 • PCIE0 + ADC1D

PCINT0 • PCIE0 + ADC0D

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ATmega164P/324P/644P

13.3.2 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 13-6.

Table 13-6. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

SCK (SPI Bus Master clock input) PCINT15 (Pin Change Interrupt 15)

MISO (SPI Bus Master Input/Slave Output) PCINT14 (Pin Change Interrupt 14)

MOSI (SPI Bus Master Output/Slave Input) PCINT13 (Pin Change Interrupt 13)

(SPI Slave Select input)

SS OC0B (Timer/Conter 0 Output Compare Match B Output) PCINT12 (Pin Change Interrupt 12)

AIN1 (Analog Comparator Negative Input) OC0A (Timer/Conter 0 Output Compare Match A Output) PCINT11 (Pin Change Interrupt 11)

AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10)

T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9)

T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8)

The alternate pin configuration is as follows:

• SCK/PCINT15 – Port B, Bit 7

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB7. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB7. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB7 bit.

PCINT15, Pin Change Interrupt source 15: The PB7 pin can serve as an external interrupt source.

• MISO/PCINT14 – Port B, Bit 6

MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB6. When the SPI is enabled as a slave, the data direction of th is pi n is controlled b y DDB6. When the pin is f orced to be an input, the pull-up can still be controlled by the PORTB6 bit.

PCINT14, Pin Change Interrupt source 14: The PB6 pin can serve as an external interrupt source.

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ATmega164P/324P/644P

• MOSI/PCINT13 – Port B, Bit 5

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB5 bit.

PCINT13, Pin Change Interrupt source 13: The PB5 pin can serve as an external interrupt source.

•SS

/OC0B/PCINT12 – Port B, Bit 4

: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB4. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit.

OC0B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter0 Output Compare. Th e pin has to b e co nfigured as an out put ( DDB4 set “on e”) to serve this function. The OC0B pin is also the output pin for the PWM mode timer function.

PCINT12, Pin Change Interrupt source 12: The PB4 pin can serve as an external interrupt source.

• AIN1/OC0A/PCINT11, Bit 3

AIN1, Analog Comparator Negative input. This pin is directly connected to the negative input of the Analog Comparator.

OC0A, Output Compare Match A output: The PB3 pin can serve as an external output for the Timer/Counter0 Output Compare. Th e pin has to b e co nfigured as an out put ( DDB3 set “on e”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

PCINT11, Pin Change Interrupt source 11: The PB3 pin can serve as an external interrupt source.

• AIN0/INT2/PCINT10, Bit 2

AIN0, Analog Comparator Positive input. This pin is directly connected to the positive input of the Analog Comparator.

INT2, External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to the MCU.

PCINT10, Pin Change Interrupt source 10: The PB2 pin can serve as an external interrupt source.

• T1/CLKO/PCINT9, Bit 1

T1, Timer/Counter1 counter source. CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The

divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset.

8011G–AVR–08/07

PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source.

ATmega164P/324P/644P

• T0/XCK0/PCINT8, Bit 0

T0, Timer/Counter0 counter source. XCK0, USART0 External clock. The Data Direction Register (DDB0) controls whether the clock

is output (DDD0 set “one”) or input (DDD0 cleared). The XCK0 pin is active only when the USART0 operates in Synchronous mode.

PCINT8, Pin Change Interrupt source 8: The PB0 pin can serve as an external interrupt source.

Table 13-7 and Table 13-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 13-5 on page 78. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT. .

Table 13-7. Overriding Signals for Alternate Functions in PB7:PB4

Signal Name

PUOE SPE • MSTR PUOV PORTB7 • PUD PORTB14 • PUD PORTB13 • PUD PORTB12 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR DDOV 0 0 0 0 PVOE SPE • MSTR SPE • MSTR

PVOV SCK OUTPUT

DIEOE PCINT15 • PCIE1 PCINT14 • PCIE1 PCINT13 • PCIE1 PCINT12 • PCIE1 DIEOV1111

AIO––––

PB7/SCK/ PCINT15

SCK INPUT PCINT17 INPUT

PB6/MISO/ PCINT14

SPE • MSTR SPE • MSTR SPE • MSTR

SPI SLAVE OUTPUT

SPI MSTR INPUT PCINT14 INPUT

PB5/MOSI/ PCINT13

SPE • MSTR OC0A ENABLE

SPI MSTR OUTPUT OC0A

SPI SLAVE INPUT PCINT13 INPUT

PB4/SS/OC0B/ PCINT12

SPI SS PCINT12 INPUT

Table 13-8. Overriding Signals for Alternate Functions in PB3:PB0

Signal Name

PUOE0000 PUOV0000

PB3/AIN1/OC0B/ PCINT11

PB2/AIN0/INT2/ PCINT10

PB1/T1/CLKO/PCINT9PB0/T0/XCK/

PCINT8

DDOE 0 0 CKOUT 0 DDOV 0 0 CKOUT 0 PVOE OC0B ENABLE 0 CKOUT 0 PVOV OC0B 0 CLK I/O 0

DIEOE PCINT11 • PCIE1

DIEOV 1 1 1 1

DI PCINT11 INPUT

AIO AIN1 INPUT AIN0 INPUT – –

INT2 ENABLE PCINT10 • PCIE1

INT2 INPUT PCINT10 INPUT

PCINT9 • PCIE1 PCINT8 • PCIE1

T1 INPUT PCINT9 INPUT

T0 INPUT PCINT8 INPUT

8011G–AVR–08/07

13.3.3 Alternate Functions of Port C

The Port C pins with alternate functions are shown in Table 13-9.

Table 13-9. Port C Pins Alternate Functions

Port Pin Alternate Function

ATmega164P/324P/644P

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0

TOSC2 (Timer Oscillator pin 2) PCINT23 (Pin Change Interrupt 23)

TOSC1 (Timer Oscillator pin 1) PCINT22 (Pin Change Interrupt 22)

TDI (JTAG Test Data Input) PCINT21 (Pin Change Interrupt 21)

TDO (JTAG Test Data Output) PCINT20 (Pin Change Interrupt 20)

TMS (JTAG Test Mode Select) PCINT19 (Pin Change Interrupt 19)

TCK (JTAG Test Clock) PCINT18 (Pin Change Interrupt 18)

SDA (2-wire Serial Bus Data Input/Output Line) PCINT17 (Pin Change Interrupt 17)

SCL (2-wire Serial Bus Clock Line) PCINT16 (Pin Change Interrupt 16)

• TOSC2/PCINT23 – Port C, Bit7

TOSC2, Timer Oscillator pin 2. The PC7 pin can serve as an external interrupt source to the MCU.

PCINT23, Pin Change Interrupt source 23: The PC7 pin can serve as an external interrupt source.

8011G–AVR–08/07

• TOSC1/PCINT22 – Port C, Bit 6

TOSC1, Timer Oscillator pin 1. The PC6 pin can serve as an external interrupt source to the MCU.

PCINT22, Pin Change Interrupt source 23: The PC6 pin can serve as an external interrupt source.

• TDI/PCINT21 – Port C, Bit 5

TDI, JTAG Test Data Input. PCINT21, Pin Change Interrupt source 21: The PC5 pin can serve as an external interrupt

source.

• TDO/PCINT20 – Port C, Bit 4

TDO, JTAG Test Data Output. PCINT20, Pin Change Interrupt source 20: The PC4 pin can serve as an external interrupt

source.

ATmega164P/324P/644P

• TMS/PCINT19 – Port C, Bit 3

TMS, JTAG Test Mode Select. PCINT19, Pin Change Interrupt source 19: The PC3 pin can serve as an external interrupt

source.

• TCK/PCINT18 – Port C, Bit 2

TCK, JTAG Test Clock. PCINT18, Pin Change Interrupt source 18: The PC2 pin can serve as an external interrupt

source.

• SDA/PCINT17 – Port C, Bit 1

SDA, 2-wire Serial Bus Data Input/Output Line. PCINT17, Pin Change Interrupt source 17: The PC1 pin can serve as an external interrupt

source.

• SCL/PCINT16 – Port C, Bit 0

SCL, 2-wire Serial Busk Clock Line. PCINT23, Pin Change Interrupt source 23: The PC0 pin can serve as an external interrupt

source.

Table 13-10 and Table 13-11 relate the alternate functions of Port C to the overriding signals

shown in Figure 13-5 on page 78.

Table 13-10. Overriding Signals for Alternate Functions in PC7:PC4

Signal Name

PUOE AS2 • EXCLK PUOV0 011 DDOE AS2 • EXCLK

DDOV 0 0 0

PVOE0 00JTAGEN PVOV0 00TDO

DIEOE

DIEOV AS2 DI PCINT23 INPUT PCINT22 INPUT PCINT21 INPUT PCINT20 INPUT

AIO T/C2 OSC OUTPUT

PC7/TOSC2/ PCINT23

AS2 • EXCLK PCINT23 • PCIE2

PC6/TOSC1/ PCINT22

AS2 JTAGEN JTAGEN

AS2 + PCINT22 • PCIE2

EXCLK + AS2 JTAGEN JTAGEN

T/C2 OSC INPUT

PC5/TDI/ PCINT21

JTAGEN + PCINT21 • PCIE2

TDI INPUT –

PC4/TDO/ PCINT20

SHIFT_IR + SHIFT_DR

JTAGEN + PCINT20 • PCIE2

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ATmega164P/324P/644P

Table 13-11. Overriding Signals for Alternate Functions in PC3:PC0

Signal Name

PUOE JTAGEN JTAGEN TWEN TWEN PUOV 1 1 PORTC1 • PUD PORTC0 • PUD DDOEJTAGENJTAGENTWEN TWEN DDOV 0 0 0 0 PVOE 0 0 TWEN TWEN PVOV 0 0 SDA OUT SCL OUT

DIEOE

DIEOV JTAGEN DI PCINT19 INPUT PCINT18 INPUT PCINT17 INPUT PCINT16 INPUT AIO TMS INPUT TCK INPUT SDA INPUT SCL INPUT

PC3/TMS/ PCINT19

JTAGEN + PCINT19 • PCIE2

13.3.4 Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 13-12.

Table 13-12. Port D Pins Alternate Functions

PC2/TCK/ PCINT18

JTAGEN + PCINT18 • PCIE2

JTAGEN 11

PC1/SDA/ PCINT17

PCINT17 • PCIE2 PCINT16 • PCIE2

PC0/SCL/ PCINT16

Port Pin Alternate Function

PD7

PD6

PD5

PD4

PD3

PD2

PD1

PD0

OC2A (Timer/Counter2 Output Compare Match A Output) PCINT31 (Pin Change Interrupt 31)

ICP1 (Timer/Counter1 Input Capture Trigger) OC2B (Timer/Counter2 Output Compare Match B Output) PCINT30 (Pin Change Interrupt 30)

OC1A (Timer/Counter1 Output Compare Match A Output) PCINT29 (Pin Change Interrupt 29)

OC1B (Timer/Counter1 Output Compare Match B Output) XCK1 (USART1 External Clock Input/Output) PCINT28 (Pin Change Interrupt 28)

INT1 (External Interrupt1 Input) TXD1 (USART1 Transmit Pin) PCINT27 (Pin Change Interrupt 27)

INT0 (External Interrupt0 Input) RXD1 (USART1 Receive Pin) PCINT26 (Pin Change Interrupt 26)

TXD0 (USART0 Transmit Pin) PCINT25 (Pin Change Interrupt 25)

RXD0 (USART0 Receive Pin) PCINT24 (Pin Change Interrupt 24)

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ATmega164P/324P/644P

The alternate pin configuration is as follows:

• OC2A/PCINT31 – Port D, Bit 7

OC2A, Output Compare Match A output: The PD7 pin can serve as an external output for the Timer/Counter2 Output Compare A. The pin has to be configured as an outpu t (DDD7 set (one )) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT31, Pin Change Interrupt Source 31:The PD7 pin can serve as an external interrupt source.

• ICP1/OC2B/PCINT30 – Port D, Bit 6

ICP1, Input Capture Pin 1: The PD6 pin can act as an input capture pin for Timer /Counter1. OC2B, Output Compare Match B output: The PD6 pin can serve as an external output for the

Timer/Counter2 Output Compare B. The pin has to be configured as an outpu t (DDD6 set (one )) to serve this function. The OC2B pin is also the output pin for the PWM mode timer function.

PCINT30, Pin Change Interrupt Source 30: The PD6 pin can serve as a n external interrupt source.

• OC1A/PCINT29 – Port D, Bit 5

OC1A, Output Compare Match A output: The PD5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an outpu t (DDD5 set (one )) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT29, Pin Change Interrupt Source 29: The PD5 pin can serve as a n external interrupt source.

• OC1B/XCK1/PCINT28 – Port D, Bit 4

OC1B, Output Compare Match B output: The PB4 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an outpu t (DDD4 set (one )) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

XCK1, USART1 External clock. The Data Direction Register (DDB4) controls whether the clock is output (DDD4 set “one”) or input (DDD4 cleared). The XCK4 pin is active only when the USART1 operates in Synchronous mode.

PCINT28, Pin Change Interrupt Source 28: The PD4 pin can serve as a n external interrupt source.

• INT1/TXD1/PCINT27 – Port D, Bit 3

INT1, External Interrupt source 1. The PD3 pin can serve as an external interrupt source to the MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.

PCINT27, Pin Change Interrupt Source 27: The PD3 pin can serve as a n external interrupt source.

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ATmega164P/324P/644P

• INT0/RXD1/PCINT26 – Port D, Bit 2

INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the MCU.

RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as a n external interrupt source.

• TXD0/PCINT25 – Port D, Bit 1

TXD0, Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD1.

PCINT25, Pin Change Interrupt Source 25: The PD1 pin can serve as a n external interrupt source.

• RXD0/PCINT24 – Port D, Bit 0

RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled this pin is configured as an input regardless of the value of DDD0. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD0 bit.

PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as a n external interrupt source.

Table 13-13 on page 89 and Table 13-14 on page 90 relates the alternate functions of Port D to

the overriding signals shown in Figure 13-5 on page 78.

Table 13-13. Overriding Signals for Alternate Functions PD7:PD4

PD6/ICP1/

PD7/OC2A/

Signal Name

PUOE0000 PUOV0000 DDOE0000 DDOV0000 PVOE OC2A ENABLE OC2B ENABLE OC1A ENABLE OC1B ENABLE PVOV OCA2A OC2B OC1A OC1B DIEOE PCINT31 • PCIE3 PCINT30 • PCIE3 PCINT29 • PCIE3 PCINT28 • PCIE3

PCINT31

OC2B/ PCINT30

PD5/OC1A/ PCINT29

PD4/OC1B/XCK1/ PCINT28

8011G–AVR–08/07

DIEOV1111

DI PCINT31 INPUT

AIO––––

ICP1 INPUT PCINT30 INPUT

PCINT29 INPUT PCINT28 INPUT

ATmega164P/324P/644P

Table 13-14. Overriding Signals for Alternate Functions in PD3:PD0

(1)

Signal Name

PD3/INT1/TXD1/ PCINT27

PD2/INT0/RXD1/ PCINT26

PD1/TXD0/ PCINT25

PD0/RXD0/ PCINT27

PUOE TXEN1 RXEN1 TXEN0 RXEN1 PUOV 0 PORTD2 • PUD 0PORTD0 • PUD DDOE TXEN1 RXEN1 TXEN0 RXEN1 DDOV 1 0 1 0 PVOE TXEN1 0 TXEN0 0 PVOV TXD1 0 TXD0 0

DIEOE

INT1 ENABLE PCINT27 • PCIE3

INT2 ENABLE PCINT26 • PCIE3

PCINT25 • PCIE3 PCINT24 • PCIE3

DIEOV1111

INT0 INPUT RXD1 PCINT26 INPUT

PCINT25 INPUT

RXD0 PCINT24 INPUT

INT1 INPUT PCINT27 INPUT

AIO––––

Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0

and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.

8011G–AVR–08/07

Register Description

13.3.5 MCUCR – MCU Control Register

Bit 7 6 5 4 3 2 1 0 0x35 (0x55) Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See ”Con-

figuring the Pin” on page 73 for more details about this feature.

13.3.6 PORTA – Port A Data Register

Bit 76543210 0x02 (0x22) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

13.3.7 DDRA – Port A Data Direction Register

JTD BODS BODSE PUD – – IVSEL IVCE MCUCR

PORTA7 PORTA6 PORTA5 PORTA4 PORTA3 PORTA2 PORTA1 PORTA0

ATmega164P/324P/644P

PORTA

Bit 76543210 0x01 (0x21) DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.3.8 PINA – Port A Input Pins Address

Bit 76543210 0x00 (0x20) PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.3.9 PORTB – Port B Data Register

Bit 76543210 0x05 (0x25) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 PORTB

13.3.10 DDRB – Port B Data Direction Register

Bit 76543210 0x04 (0x24) DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.3.11 PINB – Port B Input Pins Address

8011G–AVR–08/07

Bit 76543210 0x03 (0x23) PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

ATmega164P/324P/644P

13.3.12 PORTC – Port C Data Register

Bit 76543210 0x08 (0x28) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTC7 PORTC6 PORTC5 PORTC4 PORTC3 PORTC2 PORTC1 PORTC0 PORTC

13.3.13 DDRC – Port C Data Direction Register

Bit 76543210 0x07 (0x27) DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.3.14 PINC – Port C Input Pins Address

Bit 76543210 0x06 (0x26) PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

13.3.15 PORTD – Port D Data Register

Bit 76543210 0x0B (0x2B) Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 PORTD

13.3.16 DDRD – Port D Data Direction Register

Bit 76543210 0x0A (0x2A) DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

13.3.17 PIND – Port D Input Pins Address

Bit 76543210 0x09 (0x29) PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

8011G–AVR–08/07

14. 8-bit Timer/Counter0 with PWM

14.1 Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

14.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output Compare Units, and with PWM support. It allows accurate progr am execution timing (event management) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 14-1. For the actual placement of I/O pins, see ”Pin Configu rations” on page 2. CPU accessible I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the ”Register Description” on page 104.

ATmega164P/324P/644P

14.2.1 Registers

Figure 14-1. 8-bit Timer/Counter Block Diagram

Count

Clear

Control Logic

Direction

TOP BOT TOM

Timer/Counter

TCNTn

OCRnA

DATA BUS

OCRnB

TCCRnA TCCRnB

clk

Fixed TOP

Val ue

TOVn

(Int.Req.)

Clock Select

Edge

Detector

( From Prescaler )

OCnA

(Int.Req.)

Wavefor m

Generation

OCnB

(Int.Req.)

Wavefor m

Generation

OCnA

OCnB

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A an d OCR0B) are 8-bit registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the Timer Interrupt Flag Register (TIFR0). All interr upts are individ ually masked with the Timer Inte rrupt Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.

8011G–AVR–08/07

The Timer/Counter can be clocked internally, via th e prescaler, or b y an external clo ck source on the T0 pin. The Clock Select logic block controls which clock source a nd edge the Tim er/Counter

ATmega164P/324P/644P

14.2.2 Definitions

TOVn

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source is selected. The output from the Clock Select logic is referred to as the timer clock (clk

The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and OC0B). See Section “14.5” on page 95. for details. The Compare Match event will also set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt request.

Many register and bit references in this section are written in genera l form. A lower case “n” replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Compare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing Timer/Counter0 counter value and so on.

The definitions in Table 14-1 are also used extensively throughout the document. Table 14-1. Definitions

BOTTOM The counter reaches the BOTTOM when it becomes 0x00. MAX The counter reaches its MAXimum when it becomes 0xFF (decimal 255). TOP The counter reaches the TOP when it beco mes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Re gister. The assignment is dependent on the mode of operation.

14.3 Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits located in the Timer/Counter Control Register (TCCR0B) . For details o n clock sources and p rescaler, see ”Timer/Counter Prescaler” on page 152.

14.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surroundings.

Figure 14-2. Counter Unit Block Diagram

DATA BUS

TCNTn Control Logic

Signal description (internal signals):

count

clear

direction

bottom

top

(Int.Req.)

clk

Clock Select

Edge

Detector

( From Prescaler )

8011G–AVR–08/07

ATmega164P/324P/644P

count Increment or decrement TCNT0 by 1. direction Select between increment and decrement. clear Clear TCNT0 (set all bits to zero). clk top Signalize that TCNT0 has reached maximum value. bottom Signalize that TCNT0 has reached minimum value (zero).

Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of whether clk count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter Control Register B (TCCR0B). There are close connections between how the counter behaves (counts) and how waveforms are generated on the Output Compare outputs OC0A and OC0B. For more details about advanced counting sequences and waveform generation, see ”Modes of

Operation” on page 98.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by the WGM02:0 bits. TOV0 can be used for generating a CPU interrupt.

14.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers (OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output Compare interrupt. The Output Compare Flag is aut om atica lly cleare d wh en the int errup t is executed. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit location. The Waveform Generator uses the match signal to generate an output according to operating mode set by the WGM02:0 bits and Compa re Outpu t mode (COM0x1:0) bits. The max and bottom signals are used by the Waveform Generator for handling the special cases of the extreme values in some modes of operation (”Modes of Operation” on page 98).

is present or not. A CPU write overrides (has priority over) all counter clear or

Timer/Counter clock, referred to as clkT0 in the following.

). clkT0 can be generated from an external or internal clock source,

8011G–AVR–08/07

Figure 14-3 shows a block diagram of the Output Compare unit.

ATmega164P/324P/644P

Figure 14-3. Output Compare Unit, Block Diagram

DATA BUS

WGMn1:0

COMnX1:0

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

The OCR0x Registers are double buffered when using any o f the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Comp are (CTC) mode s of oper ation, the do uble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare Registers to either top or bottom of the counting sequence. The synchronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the doub le buffering is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is disabled the CPU will access the OCR0x directly.

Waveform Generator

OCnx

14.5.1 Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or toggled).

14.5.2 Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initialized to the same value as TCNT0 without triggering an inte rrupt when the Timer/Counte r clock is enabled.

14.5.3 Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare Unit, independently of whether the Timer/Counter is running or not. If the va lue written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

8011G–AVR–08/07

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC0x value is to use the Force Output Compare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their valu es even when changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value. Changing the COM0x1:0 bits will take effect immediately.

14.6 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two funct ions. The Wavefor m Generato r uses the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match. Also, the COM0x1:0 bits control the OC0x pin output source. Figure 14-4 shows a simplified schematic of the logic affected by the COM0x 1:0 bit setting. Th e I/O Registe rs, I/O bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers (DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset occur, the OC0x Register is reset to “0”.

ATmega164P/324P/644P

Figure 14-4. Compare Match Output Unit, Schematic

COMnx1

COMnx0 FOCn

clk

I/O

Waveform Generator

OCnx

PORT

DATA BU S

DDR

OCnx

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visible on the pin. The port override function is independen t of the Waveform Generation mode.

8011G–AVR–08/07

The design of the Output Compare pin logic allows initialization of the OC0x state befor e the output is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. See Section “14.9” on page 104.

ATmega164P/324P/644P

14.6.1 Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits diff erently in Nor mal, CTC, and PWM modes. For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the OC0x Register is to be performed on the next Compare Match. For compare output actions in the non-PWM modes refer to Table 14-2 on page 104. For fast PWM mode, refer to Table 14-3

on page 104, and for phase correct PWM refer to Table 14-4 on page 105.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are written. For non-PWM modes, the action can be forced to have immediate effect by using the FOC0x strobe bits.

14.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is defined by the combination of the Waveform Gen eration mode (WGM02:0) and Comp are Output mode (COM0x1:0) bits. The Compare Output mode bits do no t affect the counting sequence, while the Waveform Generation mode bits do. The COM0x1: 0 bits control wheth er the PWM output generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare Match (See Section “15.8” on page 122.).

For detailed timing information see ”Timer/Counter Timing Diagrams” on page 102.

14.7.1 Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting direction is always up (incrementing), and no counter clear is performed. The counter simply overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bottom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt that automatically clears the TOV0 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Normal mode, a new counter value can be written anytime.

The Output Compare Unit can be used to ge nerate int errupts at some given time . Using the Output Compare to generate waveforms in Normal mode is not recommended, since this will occupy too much of the CPU time.

14.7.2 Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to manipulate the counter resolution. In CTC mode the counter is cleared to zero wh en the counter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence also its resolution. This mode allows greater control of the Compare Match output frequency. It also simplifies the operation of counting exte rn al ev en ts.

The timing diagram for the CTC mode is shown in Figure 14-5. The counter value (TCNT0) increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared.

8011G–AVR–08/07

Figure 14-5. CTC Mode, Timing Diagram

O (

--- -

CNTn

ATmega164P/324P/644P

OCnx Interrupt Flag Set

Toggle)

eriod

1 4

2 3

(COMnx1:0 = 1)

An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to a value close to BOTTOM when the counter is running with none or a low prescaler value must be done with care since the CTC mode does not have the double buffering feature. If the new value written to OCR0A is lower than the current value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the Co mpare Match can occur.

For generating a waveform output in CT C mod e, the O C0A outp ut can be set to t oggle it s logica l level on each Compare Match by setting the Compare Output mode bits to toggle mode (COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for the pin is set to output. The waveform generated will have a maximum frequency of f f

/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

clk_I/O

OC0

equation:

OCnx

----------------------------------------------

2 N 1 OCRnx+()⋅⋅

clk_I/O

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). As for the Normal mode of operation, the TOV0 Flag is set in the same tim er clock cycle tha t the

counter counts from MAX to 0x00.

14.7.3 Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM option by its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOTTOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7. In non inverting Compare Output mode, the Out put Compare (OC0x) is cleared on the Compare Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode, the output is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mo de can be twice as high as the phase co rrect PWM mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited for power regulation, rectification, and DAC applications. High frequency allows physically small sized external components (coils, capacitors), and therefore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

8011G–AVR–08/07

ATmega164P/324P/644P

PWM mode is shown in Figure 14-6. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation . The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Se

OCRnx Update and TOVn Interrupt Flag Set

CNTn

Cnx

eriod

2 3

4 5 6 7

(COMnx1:0 = 2)

(COMnx1:0 = 3)

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the interrupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This op tion is no t ava ilable for the OC0B pin (See Table 14-3 on page 104). The actual OC0x value will only be visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is generated by setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

OCnxPWM

clk_I/O

----------------- -=

N 256⋅

The N variable represents the prescale factor (1, 8, 64, 256, or 1024). The extreme values for the OCR0A Regis ter represe nts specia l cases when generat ing a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by setting OC0x to toggle its logical level on each C ompare Match (COM 0x1:0 = 1). The wavefo rm generated will have a maximum frequency of f

100

OC0

= f

/2 when OCR0A is set to zero. This

clk_I/O

8011G–AVR–08/07

ATMEL ATmega164P, ATmega164PV, ATmega324P, ATmega324PV, ATmega644P User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

2. Overview

2.1 Block Diagram

2.2 Comparison Between ATmega164P, ATmega324P and ATmega644P

2.3 Pin Descriptions

2.3.1 VCC

2.3.2 GND

2.3.3 Port A (PA7:PA0)

2.3.4 Port B (PB7:PB0)

2.3.5 Port C (PC7:PC0)

2.3.6 Port D (PD7:PD0)

2.3.7 RESET

2.3.8 XTAL1

2.3.9 XTAL2

2.3.10 AVCC

2.3.11 AREF

3. Resources

4. About Code Examples

5. Data Retention

6. AVR CPU Core

6.1 Overview

6.3 Status Register

6.4 General Purpose Register File

6.4.1 The X-register, Y-register, and Z-register

6.5 Stack Pointer

6.6 Instruction Execution Timing

6.7 Reset and Interrupt Handling

6.7.1 Interrupt Response Time

7. AVR Memories

7.1 Overview

7.2 In-System Reprogrammable Flash Program Memory

7.3 SRAM Data Memory

7.3.1 Data Memory Access Times

7.4 EEPROM Data Memory

7.4.1 EEPROM Read/Write Access

7.4.2 Preventing EEPROM Corruption

7.5 I/O Memory

7.6 Register Description

8. System Clock and Clock Options

8.1 Clock Systems and their Distribution

8.2 Clock Sources

8.2.1 Default Clock Source

8.2.2 Clock Startup Sequence

8.2.3 Clock Source Connections

8.3 Low Power Crystal Oscillator

8.4 Full Swing Crystal Oscillator

8.5 Low Frequency Crystal Oscillator

8.6 Calibrated Internal RC Oscillator

8.7 128 kHz Internal Oscillator

8.8 External Clock

8.9 Timer/Counter Oscillator

8.10 Clock Output Buffer

8.11 System Clock Prescaler

8.12 Register Description

9. Power Management and Sleep Modes

9.1 Overview

9.2 Sleep Modes

9.3 BOD Disable

9.4 Idle Mode

9.5 ADC Noise Reduction Mode

9.6 Power-down Mode

9.7 Power-save Mode

9.8 Standby Mode

9.9 Extended Standby Mode

9.10 Power Reduction Register

9.11 Minimizing Power Consumption

9.11.1 Analog to Digital Converter

9.11.2 Analog Comparator

9.11.3 Brown-out Detector

9.11.4 Internal Voltage Reference

9.11.5 Watchdog Timer

9.11.6 Port Pins

9.11.7 On-chip Debug System

9.12 Register Description

10. System Control and Reset