ATMEL ATF2500C-15JC, ATF2500C-20PI, ATF2500C-20PC, ATF2500C-20JC Datasheet

Features

• High-perf ormance, High-density, Electrically-erasable Programmable Logic Device

• Fully Connected Logic Arr ay with 416 Product Terms

• 15 ns Maximum Pin-to-pin Delay for 5V Operation

• 24 Flexible Output Macrocells

– 48 Flip-flop s – Two per Macrocell
–72 Sum Terms
– All Flip-flops, I/O Pins Feed i n Independently

• D- or T-type Flip -flops

• Product Term or Direct Input Pin Clocking

• Registered or Combinatorial Internal Feedback

• Backwar d Com patible with ATV2500B/BQ and ATV2500H Software

• Advanced Electrically-erasable Technology

– Reprogrammable
– 100 % Tested

• 44-lead Surface Mount Package and DIP Pac kage

• Flexible D es i g n: Up to 48 B urie d Fl ip -flops and 24 Combina to r ia l O u tp u ts

Simultaneously

• 8 Synchronous Product Terms

• Individual Asyn chronous Reset per Macr ocell

• OE Control per Macr ocell

• Functionali ty Equi valent to ATV2500B/BQ and ATV2500H

• 2000V ESD Protection

• Security Fuse Feature to Protect the Code

• Commercial and Industrial Temperature Range Offered

• 10 Y ear Data Retention

• Pin Keeper Option

• 200 mA Latch-up Immunity

ATF2500C
CPLD Family
Datasheet

ATF2500C

Block Diagram

Pin Configurations

Pin Name Function

IN Logic Inp uts
CLK/IN Pin Clo ck and Input
I/O Bi-directio na l Buf fers
I/O 0,2,4... “Even” I/O Buffers
I/O 1,3,5... “Odd” I/O Buffers
GND Ground
VCC +5V Supply

PLCC/LCC/JLCC

I/O1

I/O0

65432

7

I/O2

8

I/O3

9

I/O4

10

I/O5

11

VCC

12

VCC

13

I/O17

14

I/O16

15

I/O15

16

I/O14

17

I/O13

1819202122232425262728

INININININININ

I/O12

GNDININ

CLK/INININININ
1

4443424140

GND

I/O18

I/O6

39
38
37
36
35
34
33
32
31
30
29

I/O19

I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20

CLK/IN

VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12

DIP

1

40

2

IN

3

IN

4

I/O0

5

I/O1

6

I/O2

7

I/O3

8

I/O4

9

I/O5

10
11
12
13
14
15
16
17

IN

18

IN

19

IN

20

IN

IN

39

IN

38

IN

37

IN

36

I/O6

35

I/O7

34

I/O8

33

I/O9

32

I/O10

31

I/O11

30

GND

29

I/O23

28

I/O22

27

I/O21

26

I/O20

25

I/O19

24

I/O18

23

IN

22

IN

21

IN

Note: (PLCC/LCC/JLCC packages) pin 4 and pin 26

GND connections are not required, but are rec­ommended for im proved noise immunity.

Rev. 0777I–PLD–4/03

1

Description The ATF2500C is the highest-density PLD available in a 44-pin package. With its fully con-

nected logic array and flexible macrocell structure, high gate utilization is easily obtainable.
The ATF2500 C is a high-pe rformance CM OS (electric ally-erasable) pro grammab le logic
device (PLD) that utilizes Atmel’s proven electrically-erasable technology.

The ATF2500C is organized around a single universal array. All pins and feedback terms are
always available to every macrocell. Each of the 38 logic pins are array inputs, as are the out­puts of each flip-flop.

In the ATF250 0C, four p rod uct term s are inpu t to each sum t erm. Fu rthermore , each macro­cell’s three sum terms can be combi ned to provide up t o 12 product terms per sum term with
no performance penalty. Each flip-flop is individually selectable to be either D- or T-type, pro­viding further logic compac tion. Also, 24 of the flip-flo ps may be bypasse d to provide interna l
combinatorial feedback to the logic array.

Product terms provid e individua l clocks and async hronous resets for e ach flip-flop. Th e flip­flops may also be ind ividually c onfigured to have direct input pin cl ocking. Ea ch out put has its
own enable product term. Eight synchronous preset product terms serve local groups of either
four or eight flip-flops. Register preload functions are provided to simplify testing. All registers
automatically reset upon power-up.

Using the
ATF2500C
Family’s Many
Advanced
Features

The ATF2500Cs advanced flexibility packs more usable gates into 44 leads than other PLDs.
Some of the ATF2500Cs key features are:

• Fully Connected Logic Array – Each array input is always available to every product
term. This makes logic placement a breeze.

• Selectable D- and T-Type Registers – Each ATF2500C flip-flop can be individually
configured as either D- or T-type. Using the T-type configuration, JK and SR flip-flops are
also easily created. These options allow more efficient product term usage.

• Buried Combinatorial Feedback – Each macrocell’s Q2 register may be bypassed to
feed its input (D/T2) directly back to the logic array. This provides further logic expansion
capability without using precious pin res ourc es.

• Selectable Synchronous/Asynchronous Clocking – Each of the ATF2500Cs flip-flops
has a dedicated clock product term. This removes the constraint that all registers use the
same clock. Buried state machines, counters and registers can all coexist in one device
while running on separate clocks. Individual flip-flop clock source selection fur ther allows
mixing higher performance pin clocking and flexible product term clocking within one
design.

• A Total of 48 Registers – The ATF2500C provides two flip-flops per macrocell – a total of

48. Each register has its own clock and reset terms, as well as its own sum term.

• Independent I/O Pin and Feedback Paths – Each I/O pin on the ATF2500C has a
dedicated input path. Each of the 48 registers has its own feedback term into the array as
well. These features, combined with individual product terms for each I/O’s output enable,
facilitate true bi-directional I/O design.

• Combinable Sum Terms – Each output macrocell’s three sum terms may be combined
into a single term. This provides a fan in of up to 12 product terms per sum term with

speed penalty.

• Programmable Pin-keep er Circuits – These weak feedback latches are useful for bus
interfacing applications. Floating pins can be set to a known state if the Pin-keepers are
enabled.

• User Row (64 bits) – Use to store information such as unit history.

no

2

ATF2500C Family

0777I–PLD–4/03

ATF2500C Family

Power-up Reset The registers in the ATF2500Cs are designed to reset during power-up. At a point delayed

slightly f rom V
depend on the polarity of the output buffer.

crossing V

CC

, all registers will be reset to the low state. The output state will

RST

This feature is critical for state as nature of reset and the uncertainty of how V

actually rises

CC

in the system, the following conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup times must be met before driving the
clock pin or terms high, and

3. The clock pin, and any signals from which clock terms are derived, must remain stable
during t

Parameter Description Typ Max Units

t

PR

V

RST

Power-up Reset Time 600 1000 ns
Power-up Reset Voltage 3.8 4.5 V

PR

.

Level Forced on

Odd I/O Pin during

PRELOAD Cyc le

V

IH/VIL

V

IH/VIL

V

IH/VIL

V

IH/VIL

0777I–PLD–4/03

Q Select Pin

State

Low Low High/Low X X X

High Low X High/Low X X

Low Hi gh X X High/Low X

High High X X X High/Low

Even/Odd

Select

Even Q1 State

after Cycle

Even Q2 State

after Cycle

Odd Q1 State

after Cycle

Odd Q2 State

after Cycle

3

Preload and
Observability of
Registered
Outputs

The ATF2500Cs registers are provided with circuitry to allow loading of each register asyn­chronously w ith either a high or a lo w. This feature w ill simplif y testing since any state can be
forced into the registers to control test sequencing. A V
appropriate register high; a V
tion bit settings.

The PRELOAD state is entered by placing an 10.25V to 10.75V signal on SMP lead 42. When
the preload clock SMP lead 23 is pulsed high, the data on the I/O pins is placed into the 12
registers chosen by the Q select and even/odd select pins.

Register 2 ob ser va bilit y m ode is entered by p lacing an 10. 25V t o 10 .75 V signal on pin/lead 2.
In this m ode , th e cont ents of t he buri ed re gis ter b a nk wi ll a ppe ar on th e as soci ate d ou tpu ts
when the OE control signals are active.

will force it low, independent of the polarity or other configura-

IL

level on the odd I/O pins will force the

IH

Programming
Software
Support

Security Fuse
Usage

Bus-friendly
Pin-keeper
Input and I/O

All family members of the ATF2500C can be designed with Atmel-WinCUPL™. ProC hip
Designer

Additionally, the ATF2500C may be programmed to perform the ATV2500Hs functional subset
(no T-type fl ip-flo ps, pi n clock ing or D/T2 feed back ) using the AT V2 500H JE DE C file. In t his
case, the ATF2500C becomes a direct replacement or speed upgrade for the ATV2500H. The
ATF250 0C ar e d irect re plac em ents for th e ATV 250 0B/BQ a nd the AT V25 00H, includ in g the
lack of extra grounds on P4 and P26.

A single fuse is pro vided to pre vent u nauthori zed copying of AT F2500 C fuse pattern s. On ce
programmed, the outputs will read program m ed dur ing verif y.

The security fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits Preload and Q2 observability.

All ATF2500C family members have programmable internal input and I/O pin-keeper circuits.
The default condition, including when using the AT2500C/CQ family to replace the

AT2500B/BQ or AT2500H, is that the pin-keepers are not activated.
When pin-keepers are active, inputs or I/Os not being driven externally will maintain their last

driven state. This ensures that all logic array inputs and device outputs are known states. Pin­keepers are relatively weak active circuits that can be easily overridden by TTL-compatible
drivers (see input and I/O diagrams below).

®

support is expected soon. Check Atmel’s web site for the latest version of ProChip.

Enabling or disab ling of t he pin-ke eper c ircuits is c ontrolle d by the d evice typ e chose n in the
logic compiler de vice selection menu. P lease refer to the S oftw are Com piler Mod e Select ion
table for more details. Once the pin-keeper circuits are disabled, normal termination proce­dures required for unused inputs and I/Os.

4

ATF2500C Family

0777I–PLD–4/03

Soft ware Compiler Mode Selection

Device Atmel - WinCupL Device Mnemonic Pin-keeper

ATF2500C Family

ATF2500C-DIP

ATF2500C-PLCC

V2500C

V2500CPPK

V2500LCC

V2500CPPKLCC

THIRD PARTY PROGRAMMER SUPPORT

Major Third Party Device Programmers support three types of JEDEC files.

Device Description

V2500 Cross-programming. JEDEC file compatib le with standard V2500

JEDEC file (Total fuses in JEDEC file = 71648). The Progr amm er will

ATF2500C (V2500)

ATF2500C (V2500B)

ATF2500C

automatical ly disable the User row fuses and also disabl e the pin-keeper
feature. The Fuse checksum wil l be the same as the old ATV2500H/L file.
This Device type is recommended for customers that are dir ectly migrating
from an ATV2500H/L device to an ATF2500C device.

V2500B Cross-programming. JEDEC file compatible with standard
V2500B JEDEC file (Total fuses in JEDEC file = 71745). The Programmer

will automatically disable the User row fuses and also disable the pin­keeper feature. The Fuse checksum will be the same as the old
ATV2500B/BQ/BQL/BL file. This Device type is recommended for
customers that are directly migr ati ng from an ATV2500B/BQ/BQL/BL
device to an ATF2500C dev ice.

Programming of User Row bits supported and Pin keeper bit is user ­programmab le. (Total fuses in JEDEC file = 71816). Thi s is the default
device type and is recommended for users that have Re-compiled their
Source Design files to specifically target the ATF2500C device.

Disabled

Enabled

Disabled

Enabled

Input Diagram

Note: The ATF2500C has 71816 Jedec fuses .

PROGRAMMABLE
OPTION

0777I–PLD–4/03

5

I/O Diagram

INPUT

PROGRAMMABLE
OPTION

Functional
Logic Diagram
Description

The ATF2500C functional logic diagram describes the interconnections between the input,
feedback pins and logic cells. All interconnections are routed through the single global bus.

The ATF2500Cs are straightforward and uniform PLDs. The 24 macrocells are numbered 0
through 23. Each macrocell contai ns 17 AND gates. A ll AND gates have 172 inputs. The five
lower product terms provide AR1, CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an out put enabl e. The t op 1 2 produc t t erms a re grouped into
three sum terms, which are used as shown in the macrocell diagrams.

Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share
Preset 0, the next two share Preset 1, and so on, ending with the last two macrocells sharing
Preset 7.

The 14 dedicated in puts and thei r compl em ents use t he num bered positions in the global bus
as shown. E ach m acr ocell prov ide s six inp uts to the glob al bu s: (l eft to r ight ) fe edba ck F 2
true and false, flip-flop Q1 true and false, and the pin true and false. The positions occupied by
these signals in the global bus are the six numbers in the bus diagram next to each macrocell.

Note: 1. Either the flip-fl op input (D/T2) or output (Q2) may be fed bac k in the ATF2500Cs.

(1)

6

ATF2500C Family

0777I–PLD–4/03