ATMEL ATF22V10CZ, ATF22V10CQZ User Manual

Features

• Industry-standard Architecture

• 12 ns Maximum Pin-to-pin Delay

• Zero Power – 25 µA Maximum Standby Power (Input Transition Detection)

• CMOS and TTL Compatible Inputs and Outputs

• Advanced Electrically-erasableTechnology

– Reprogrammable
– 100% Tested

• Latch Feature Holds Inputs to Previous Logic State

• High-reliability CMOS Process

– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity

• Commercial and Industrial Temperature Ranges

• Dual-in-line and Surface Mount Standard Pinouts

• PCI Compliant

• Green Package Options (Pb/Halide-free/RoHS Compliant) Available

1. Desscription

The ATF22V10CZ/CQZ is a high-performance CMOS (electrically-erasable)
programmable logic device (PLD) which utilizes Atmel’s proven electrically-erasable
Flash memory technology. Speeds down to 12 ns with zero standby power dissipation
are offered. All speed ranges are specified over the full 5V ±10% range for industrial
temperature ranges; 5V ±5% for commercial range 5-volt devices. The
ATF22V10CZ/CQZ provides a low voltage and edge-sensing “zero” power CMOS
PLD solution with “zero” standby power (5 µA typical). The ATF22V10CZ/CQZ pro­vides a “zero” power CMOS PLD solution with 5V operating voltages, powering down
automatically to the zero power-mode through Atmel’s patented Input Transition
Detection (ITD) circuitry when the device is idle, offering “zero” (25 µA worst case)
standby power. This feature allows the user to manage total system power to meet
specific application requirements and enhance reliability. Pin “keeper” circuits on input
and output pins eliminate static power consumed by pull-up resistors. The “CQZ” com­bines the low high-frequency I

The ATF22V10CZ/CQZ incorporates a superset of the generic architectures, which
allows direct replacement of the 22V10 family and most 24-pin combinatorial PLDs.
Ten outputs are each allocated 8 to 16 product terms. Three different modes of opera­tion, configured automatically with software, allow highly complex logic functions to be
realized.

of the “Q” design with the “Z” feature.

CC

High­performance
EE PLD

ATF22V10CZ
ATF22V10CQZ

0778J–PLD–11/07

Figure 1-1. Block Diagram

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

CLK/IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

GND

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN

1
2
3
4
5
6
7
8
9
10
11
12

24
23
22
21
20
19
18
17
16
15
14
13

CLK/IN

IN
IN
IN
IN
IN
IN
IN
IN
IN
IN

GND

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IN

5
6
7
8
9
10
11

25
24
23
22
21
20
19

IN
IN
IN

GND*

IN
IN
IN

I/O
I/O
I/O
GND*
I/O
I/O
I/O

432

1

282726

12131415161718

IN

IN

GND

GND*

IN

I/O

I/O

ININCLK/IN

VCC*

VCC

I/O

I/O

2. Pin Configurations

Table 2-1. Pin Configurations (All Pinouts Top View)

Pin Name Function

CLK Clock

IN Logic Inputs

I/O Bi-directional Buffers

VCC +5V Supply

Figure 2-1. TSSOP Figure 2-2. DIP/SOIC

2

Figure 2-3. PLCC

Note: For PLCC, P1, P8, P15 and P22 can be

left unconnected. For superior perfor­mance, connect VCC to pin 1 and GND
to 8, 15, and 22.

ATF22V10C(Q)Z

0778J–PLD–11/07

ATF22V10C(Q)Z

3. Absolute Maximum Ratings*

Temperature Under Bias.................................. -40°C to +85°C

Storage Temperature ..................................... -65°C to +150°C

Voltage on Any Pin with

Respect to Ground .........................................-2.0V to +7.0V

Voltage on Input Pins
with Respect to Ground

During Programming.....................................-2.0V to +14.0V

Programming Voltage with

Respect to Ground .......................................-2.0V to +14.0V

(1)

(1)

(1)

4. DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Ambient) 0°C - 70°C-40°C - 85°C

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is V
which may overshoot to 7.0V for pulses of less
than 20 ns.

+ 0.75V DC,

CC

VCC Power Supply 5V ± 5% 5V ± 10%

0778J–PLD–11/07

3

4.1 DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

I

IH

Input or I/O Low
Leakage Current

Input or I/O High
Leakage Current

0 ≤ VIN ≤ V

IN

≤ V

3.5 ≤ V

(Max)

IL

CC

-10 µA

10 µA

CZ-12, 15 Com 90 150 mA

= Max

V

I

CC

Clocked Power
Supply Current

CC

Outputs Open,
f = 15 MHz

CZ-15 Ind 90 180 mA

CQZ-20 Com 40 60 mA

CQZ-20 Ind 40 80 mA

CZ-12, 15 Com 5 25 µA

= Max

V

I

SB

Power Supply Current,
Standby

CC

= MAX

V

IN

Outputs Open

CZ-15 Ind 5 50 µA

CQZ-20 Com 5 25 µA

CQZ-20 Ind 5 50 µA

(1)

I

OS

V

IL

V

IH

V

OL

Output Short Circuit
Current

V

= 0.5V -130 mA

OUT

Input Low Voltage -0.5 0.8 V

Input High Voltage 2.0 VCC + 0.75 V

V

= VIH or V

Output Low Voltage

IN

VCC = Min,

IL

0.5 V

IOL = 16 mA

V

= VIH or V

V

OH

Output High Voltage

V

IN

CCIO

= Min,

IL

2.4 V

IOH = -4.0 mA

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

4

ATF22V10C(Q)Z

0778J–PLD–11/07

4.2 AC Waveforms

INPUTS, I/O
REG. FEEDBACK
SYNCH. PRESET

CP

ASYNCH. RESET

REGISTERED

OUTPUTS

COMBINATORIAL

OUTPUTS

VALID VALID

VALID

VALID

VALID

VALID

OUTPUT

DISABLED

OUTPUT

DISABLED

tS

tH

tW tW

tP

tAR

tAW

tAPtCO

tPD

tER tEA

tEAtER

ATF22V10C(Q)Z

4.3 AC Characteristics

Symbol Parameter

t

PD

t

CF

t

CO

t

S

t

H

t

W

f

MAX

t

EA

t

ER

t

PZX

t

PXZ

t

AP

t

SP

t

AW

t

AR

t

SPR

Note: 1. See ordering information for valid part numbers.

(1)

-12 -15 -20

UnitsMin Max Min Max Min Max

Input or Feedback to Non-registered Output 3 12 3 15 3 20 ns

Clock to Feedback 6 4.5 8 ns

Clock to Output 2 8 2 8 2 12 ns

Input or Feedback Setup Time 10 10 14 ns

Input Hold Time 0 0 0 ns

Clock Width 6 6 10 ns

External Feedback 1/(tS + tCO)
Internal Feedback 1/(t

+ tCF)

S

No Feedback 1/(tP)

55.5
62

83.3

55.5
69

83.3

38.5

45.5

50.0

MHz
MHz
MHz

Input to Output Enable - Product Term 3 12 3 15 3 20 ns

Input to Output Disable - Product Term 2 15 3 15 3 20 ns

OE Pin to Output Enable 2 12 2 15 2 20 ns

OE Pin to Output Disable 2 15 2 15 2 20 ns

Input or I/O to Asynchronous Reset of
Register

310315322ns

Setup Time, Synchronous Preset 10 10 14 ns

Asynchronous Reset Width 7 8 20 ns

Asynchronous Reset Recovery Time 5 6 20 ns

Synchronous Preset to Clock Recovery
Time

10 10 14 ns

0778J–PLD–11/07

5

4.4 Input Test Waveforms

4.4.1 Input Test Waveforms and Measurement Levels

4.4.2 Output Test Loads

Note: Similar competitors devices are specified with slightly different loads. These load differences may

affect output signals’ delay and slew rate. Atmel devices are tested with sufficient margins to meet
compatible device specification conditions.

4.5 Pin Capacitance

Table 4-1. Pin Capacitance (f = 1 MHz, T = 25C

Typ Max Units Conditions

C

IN

C

I/O

Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100%

tested.

4.6 Power-up Reset

The registers in the ATF22V10CZ/CQZ are designed to reset during power-up. At a point
delayed slightly from V
state will depend on the polarity of the buffer.

This feature is critical for state machine initialization. However, due to the asynchronous nature
of reset and the uncertainty of how V
required:

1. The V

rise must be monotonic and start below 0.7V.

CC

2. The clock must remain stable during T

3. After T

occurs, all input and feedback setup times must be met before driving the

PR

clock pin high.

4.7 Preload of Register Outputs

The ATF22V10CZ/CQZ’s registers are provided with circuitry to allow loading of each register
with either a high or a low. This feature will simplify testing since any state can be forced into the
registers to control test sequencing. A JEDEC file with preload is generated when a source file

(1)

)

810 pF V

810 pF V

crossing V

CC

, all registers will be reset to the low state. The output

RST

actually rises in the system, the following conditions are

CC

.

PR

= 0V; f = 1.0 MHz

IN

= 0V; f = 1.0 MHz

OUT

6

ATF22V10C(Q)Z

0778J–PLD–11/07