ATMEL ATF16V8C-7PC, ATF16V8C-7JI, ATF16V8C-7JC, ATF16V8C-5JC, ATF16V8C-7XI Datasheet

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Features
Industry Standard Architecture
Emulates Many 20-Pin PALs
Low Cost Easy-to-Use Software Tools
High Speed Electrically Erasable Programmable Logic Devices
5 ns Maximum Pin-to-Pin Delay
Low Power - 100 µA Pin-Controlled Power Down Mode Option
CMOS and TTL Compatible Inputs and Outputs
I/O Pin Keeper Circuits
Advanced Flash Tech no lo gy
Reprogrammable 100% Tested
High Reliability CMOS Process
20 Year Data Retention 100 Erase/Write Cyc le s 2,000V ESD Protection 200 mA Latchup Immunity
Commercial and Industrial Temperature Ranges
Dual-in-Line and Surface Mount Packages in Standard Pinouts
Block Diagram
High Performance
2
E
PLD
ATF16V8C
Note: 1. Includes optional PD control pin.
Pin Name Function
CLK Clock I Logic Inputs I/O Bidirectional Buffers OE Output Enable VCC +5V Supply PD Power Down
TSSOP Top View
1
I/CLK
PD/I3
GND
2
I1
3
I2
4 5
I4
6
I5
7
I6
8
I7
9
I8
10
20
VCC
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
I/O
11
I9/OE
DIP/SOIC PLCC
Top view
ATF16V8C
Rev. 0425D/V16FC-D–04/98
Description
The ATF16V8C is a high performance EECMOS Pro­grammable Logic Device that utilizes Atmel’s proven elec­trically erasable Flash memory technology. S peeds down to 5 ns and a 100 µA pin-controlled power down mode op­tion are offered. All speed ranges are specified over the full 5V ± 10% range for industrial temperature ranges; 5V ± 5% for commercial range 5-volt devices.
The ATF16V8C incorporates a superset of the generic ar­chitectures, which allows direct replacement of the 16R8 family and most 20-pin combinatorial PLDs. Eight outputs are each allocated eight product terms. Three different
Absolute Maximum Ratings*
Temperature Under Bias...................-40°C to +85°C
Storage Temperature......................-65°C to +150°C
Voltage on Any Pin with
Respect to Ground.........................-2.0V to +7.0V
Voltage on Input Pins with Respect to Ground
During Programming....................-2.0V to +14.0V
Programming Voltage with
Respect to Ground.......................-2.0V to +14.0V
(1)
(1)
(1)
modes of operation, configured automatically with soft­ware, allow highly complex logic functions to be realized.
The ATF16V8C can significantly reduce total system power, thereby enhancing system reliability and reducing power supply costs. When pin 4 is configured as the power down control pin , supply current drops to less than 100 µA whenever the pin is high. If the power down fea­ture isn’t required for a particular application, pin 4 may be used as a logic input. Also, the pin keeper circuits elimi­nate the need for internal pull-up resistors along with their attendant power consumption.
*NOTICE: Stresses beyond those listed under “Absolute Maxi-
mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or an y ot he r con ditions beyond those indi­cated in the oper ational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Note:
1. Minimum voltage is -0.6V dc, which may undershoot to -
2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75 V dc, whic h may overshoot to 7. 0V for pulses of le ss than 20 ns.
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Case) 0°C - 70°C -40°C - 85°C V
Power Supply 5V ± 5% 5V ± 10%
CC
2
ATF16V8C
ATF16V8C
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
IL
I
IH
I
CC1
I
PD
I
OS
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
Note: 1. All ICC parameters measure d wit h outputs open.
Input or I/O Low Leakage Current
Input or I/O High Leakage Current
Power Supply Current,
(1)
Standby Power Supply Current,
Power Down Mode Output Short Circuit
Current
0 ≤ V
3.5 ≤ V 15 MHz, V
V
≤ VIL(MAX) -10 µA
IN
≤ V
IN
CC
= 0, V
IN
CC,
Open VCC = MAX,
V
= 0, V
V V
IN OUT
CC
CC
= 0.5V;
= 5V; TA = 25°C
CC
= MAX,
Outputs
10 µA
Com. 115 mA Ind. 130 mA Com. 10 100 µA
Ind. 10 105 µA
-150 mA
Input Low Voltage MIN < VCC < MAX -0.5 0.8 V Input High Voltage 2.0 VCC + 1 V
= MIN; All Outputs
V
Output Low Voltage
Output High Voltage
Output Low Current VCC = MIN
CC
I
= 24 mA
OL
= MIN
V
CC
I
= -4.0 mA
OL
Com., Ind. 0.5 V
2.4 V
Com. 24 mA Ind. 12 mA
Output High Current VCC = MIN Com., Ind. -4 mA
AC Waveforms
Note: 1. Timing measuremen t reference is 1.5V. In pu t AC driv in g le ve ls ar e 0. 0V an d 3.0V, unless otherw is e sp ec ified.
(1)
3
AC Characteristics
Symbol Parameter
t
PD
t
CF
t
CO
t
S
t
H
t
P
t
W
F
t
EA
t
ER
t
PZX
t
PXZ
Input or Feedback to Non-Registered Output
Clock to Feedback 3 3 ns Clock to Output 1425ns Input or Feedback Setup Time 3 5 ns Input Hold Time 0 0 ns Clock Period 6 8 ns Clock Width 3 4 ns External Feedback 1/(tS+ tCO) 142 100 MHz
MAX
Internal Feedback 1/(t No Feedback 1/(t Input to Output Enable —
Product Term Input to Output Disable —
Product Term OE pin to Output Enable 2526ns OE pin to Output Disable 1.5 5 1.5 6 ns
-5 -7
Min Max Min Max
Units
1537.5ns
+ tCF) 166 125 MHz
S
) 166 125 MHz
P
2639ns
2529ns
Power Down AC Characteristics
Symbol Parameter
t
IVDH
t
GVDH
t
CVDH
t
DHIX
t
DHGX
t
DHCX
t
DLIV
t
DLGV
t
DLCV
t
DLOV
Notes: 1. Output data is latched an d he ld .
Valid Input Before PD High 5 7.5 ns Valid OE Before PD High 0 0 ns Valid Clock Before PD High 0 0 ns Input Don’t Care After PD High 5 7.5 ns OE Don’t Care After PD High 5 7.5 ns Clock Don’t Care After PD High 5 7.5 ns PD Low to Valid Input 5 7.5 ns PD Low to Valid OE 15 20 ns PD Low to Valid Clock 15 20 ns PD Low to Valid Output 20 25 ns
2. HI-Z outputs remain HI-Z.
(1, 2, 3)
-5 -7
Min Max Min Max
3. Clock and input transitions are ignored.
Units
4
ATF16V8C
ATF16V8C
Input Test Waveforms and Measurement Levels:
tR, tF < 1.5ns (10% to 90%)
Pin Capacitance
C
IN
C
OUT
Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
(f = 1 MHz, T = 25°C)
Typ Max Units Conditions
58pFV 68pFV
(1)
Output Test Loads:
Commercial
= 0V
IN OUT
= 0V
Power Up Reset
The ATF16V8C’s registers are designed to reset during power up. At a point delayed slightly from V
, all registers will be reset to the low state. As a result,
V
RST
the registered output state will always be high on power­up.
This feature is critical for state machine initialization. How­ever, due to the asynchronous nature of reset and the un­certainty of how V lowing conditions are required:
1) The V
2) After reset occurs, all input and feedback setup times must be met before driving the clock term high, and
3) The signals from which the clock is derived must re­main stable during t
rise must be monotonic, from below .7 volts,
CC
actually rises in the system, the fol-
CC
.
PR
crossing
CC
Parameter Description Typ Max Units
t
V
PR
RST
Power-Up Reset Time
Power-Up Reset Voltage
600 1,000 ns
3.8 4.5 V
5
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