ATMEL ATF16V8BQL-25XI, ATF16V8BQL-25XC, ATF16V8BQL-25SI, ATF16V8BQL-25SC, ATF16V8BQL-25PI Datasheet

1

Features

•

Industry Standard Architecture

– Emulates Many 20-Pin PALs

®

– Low Cost Easy-to-Use Software Tools

•

High-Speed Electrically Erasable Programmable Logic Devices

– 7.5 ns Maximum Pin-to-Pin Delay

•

Several Power Saving Options

•

CMOS and TTL Compatible Inputs and Outputs

– Input and I/O Pull-Up Resistors

•

Advanced Flash Technology

– Reprogrammable
– 100% Tested

•

High Reliability CMOS Process

– 20 Year Data Retention
– 100 Erase/Write Cycles
– 2,000V ESD Protection
– 200 mA Latchup Immunity

•

Commercial, and Industrial Temperature Ranges

•

Dual-in-Line and Surface Mount Packages in Standard Pinouts

Block Diagram

Device ICC, Stand-By ICC, Active

ATF16V8B 50 mA 55 mA
ATF16V8BQ 35 mA 40 mA
ATF16V8BQL 5 mA 20 mA

Rev. 0364E–07/98

High­Perf ormance
Flash PLD

ATF16V8B

Pin Configurations

Pin Name Function

CLK Clock
I Logic Inputs
I/O Bidirectional Buffers
OE

Output Enable

V

CC

+5 V Supply

TSSOP Top View

1
2
3
4
5
6
7
8
9
10

20
19
18
17
16
15
14
13
12
11

I/CLK

I1
I2
I3
I4
I5
I6
I7
I8

GND

VCC
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I9/OE

DIP/SOIC PLCC Top View

ATF16V8B

2

Description

The ATF16V8B is a high performance CMOS (Elec trically
Erasable) Programmable Logic Device (PLD) which utilizes
Atmel’s proven electrically erasable Flash memory technol­ogy. Speeds do wn to 7 .5 ns a re offe red. Al l s peed rang es
are specified over the full 5V ± 10% range for industrial
temperature ranges, and 5V ± 5% for commercial tempera­ture ranges.

Several low power options allow selection of the best solu­tion for various types of power-limited applications. Each of

these options significantly reduces total system power and
enhances system reliability.

The ATF16V8Bs incorporate a superset of the generic
architectures, wh ich allows direct repl acemen t of the 16R8
family and most 20-pin combinatorial PLDs. Eight outputs
are each allocated eight pr oduct terms. Three different
modes of operation, configured automatically with soft­ware, allow highly complex logic functions to be realized.

Absolute Maximum Ratings*

Temperature Under Bias.................................-55oC to +125oC

*NOTICE: Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam­age to the dev ice. Th is is a s tress rating only an d
functional oper ati on of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect dev ice
reliability .

Note: 1. Minimum voltage is -0.6V DC, which may under-

shoot to -2.0V for pulses of less than 20 ns. Max­imum output pin voltage is V

CC

+ 0.75V DC,
which may overshoot to 7.0V for pulses of less
than 20 ns.

Storage Temperature......................................-65

o

C to +150oC

Voltage on Any Pin with

Respect to Ground .......................................-2.0 V to +7.0 V

(1)

Voltage on Input Pins
with Respect to Ground

During Programming...................................-2.0 V to +14.0 V

(1)

Programming Voltage with

Respect to Ground .....................................-2.0 V to +14.0 V

(1)

DC and AC Operating Conditions

Commercial Industrial

Operating Temperature (Case) 0

o

C - 70oC-40

o

C - 85oC

V

CC

Power Supply 5V ± 5% 5V ± 10%

ATF16V8B

3

Note: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.

DC Characteristics

Symbol Parameter Condition Min Typ Max Units

I

IL

Input or I/O Low
Leakage Current

0 ≤ V

IN

≤ VIL(MAX) -35 -100 µA

I

IH

Input or I/O High
Leakage Current

3.5 ≤ VIN ≤ V

CC

10 µA

I

CC

Power Supply
Current, Standby

V

CC

= MAX,

V

IN

= MAX,

Outputs Open

B-7, -10

Com. 55 85 mA
Ind. 55 95 mA

B-15, -25

Com. 50 75 mA
Ind. 50 80 mA

BQ-10 Com. 35 55 mA

BQL-15, -25

Com. 5 10 mA
Ind. 5 15 mA

I

CC2

Clocked Power
Supply Current

V

CC

= MAX,
Outputs Open,
f=15 MHz

B-7, -10

Com. 60 90 mA
Ind. 60 100 mA

B-15, -25

Com. 55 85 mA
Ind. 55 95 mA

BQ-10 Com. 40 55 mA

BQL-15, -25

Com. 20 35 mA
Ind. 20 40 mA

I

OS

(1)

Output Short
Circuit Current

V

OUT

= 0.5 V -130 mA

V

IL

Input Low Voltage -0.5 0.8 V

V

IH

Input High Voltage 2.0 VCC+0.75 V

V

OL

Output High Voltage

V

IN=VIH

or VIL,

V

CC

=MIN

I

OL

= -24 mA

Com., Ind.

0.5 V

V

OH

Output High Voltage

V

IN=VIH

or VIL,

V

CC

=MIN

I

OH

= -4.0 mA 2.4 V

ATF16V8B

4

AC Waveforms

(1)

Note: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V 3.0V, unless otherwise specified.

Notes: 1. See ordering information for valid part numbers and speed grades.

2. Recommend ATF16V8C -7.

AC Characteristics

(1)

Symbol Parameter

-7

(2)

-10 -15 -25
UnitsMin Max Min Max Min Max Min Max

t

PD

Input or Feedback to
Non-Registered Output

8 outputs switching 3 7.5 3 10 3 15 3 25 ns
1 output switching 7 ns

t

CF

Clock to Feedback 3 6 8 10 ns

t

CO

Clock to Output 2527210212ns

t

S

Input or Feedback
Setup Time

5 7.5 12 15 ns

t

H

Hold Time 0000ns

t

P

Clock Period 8 121624 ns

t

W

Clock Width 4 6 8 12 ns

F

MAX

External Feedback 1/(tS+tCO) 100 68 45 37 MHz
Internal Feedback 1/(t

S

+ tCF) 125 74 50 40 MHz

No Feedback 1/(t

P

) 125 83 62 41 MHz

t

EA

Input to Output Enable —
Product Term

3 9 3 10 3 15 3 20 ns

t

ER

Input to Output Disable —
Product Term

2 9 2 10 2 15 2 20 ns

t

PZX

OE pin to Output Enable 2 6 2 10 2 15 2 20 ns

t

PXZ

OE pin to Output Disable 1.5 6 1.5 10 1.5 15 1.5 20 ns

ATF16V8B

5

Input Test Waveforms and
Measurement Levels:

tR, tF < 5 ns (10% to 90%)

Output Test Loads:

Commercial

Note: 1. Typical values for nominal supply voltage. This param eter is only sampled and is not 100% tested.

Power Up Reset

The registers in the ATF16V8Bs are design ed to reset dur ­ing power up. At a point delayed slightly from V

CC

crossing

V

RST

, all registers will be re set to th e low state . As a r esult,

the registered output state will always be high on power-up.
This feature is critical for state machine initialization. How-

ever, due to the asynchronous nature of reset and the
uncertainty of h ow V

CC

actually rises in the sys tem, the fo l-

lowing conditions are required:

1) The V

CC

rise must be monotonic,

2) After reset occurs, all input and feedback setup times
must be met before driving the clock pin high, and

3) The clock must remain stable during t

PR

.

Preload of Registered Outputs

The ATF16V8B’s registers are provided with circuitry to
allow loading of each register with either a high or a low.
This feature will simplify testing since an y state can be
forced into the registers to control test seq uencing. A
JEDEC file with preload is generated whe n a source fil e
with vectors is compiled. Once downloaded, the JEDEC file
preload sequence will be done automatically by most of the
approved programmers after the programming.

Security Fuse Usage

A single fuse is provided to prevent unauthoriz ed copying
of the ATF16V8B fuse patterns. Once programmed, fuse
verify and preload are inhibited. However, the 64-bit User
Signature remains accessible.

The security fuse should be programmed last, as its effect
is immediate.

Pin Capacitance

f = 1 MHz, T = 25°C

(1)

T yp Max Units Conditions

C

IN

58 pFV

IN

= 0 V

C

OUT

68 pFV

OUT

= 0 V

Parameter Description Typ Max Units

t

PR

Power-Up
Reset Time

600 1,000 ns

V

RST

Power-Up
Reset Voltage

3.8 4.5 V

ATF16V8B

6

Electronic Signature Word

There are 64 bits of programmable memory that are always
available to the user, even if the device is secured. These
bits can be used for user-specific data.

Programming/Erasing

Programming/erasing is performed using standard PLD
programmers. See

CMOS PLD Programming Hardware

and Software Suppor

t for information on software/program-

ming.

Input and I/O Pull-Ups

All ATF16V8B family members have internal input and I/O
pull-up resistors. Therefore, whenever inputs or I/Os are
not being driven externally, they will float to V

CC

. This
ensures that all logi c array inputs are at kn own states.
These are relatively weak active pull-ups that can easily be
overdriven by TTL-compatible driver s (see input and I/O
diagrams below).

Input Diagram I/O Diagram

Functional Logic Diagram Description

The Logic Option and Fu nctional Diagrams des cribe the
ATF16V8B architec ture. Eig ht configur able ma crocell s can
be configured as a registered output, combinatorial I/O,
combinatorial output, or dedicated input.

The ATF16V8B can b e conf igured in one o f three dif feren t
modes. Each mode makes the ATF16V8B look like a differ­ent device. Most PLD compilers can choose the right
mode automatically. The user can also force the selection
by supplying the compiler with a mode selection. The deter­mining factors would be the usage of register versus com­binatorial ou tputs and dedic ated output s versus outpu ts
with output enable control.

The ATF16V8B universal architectur e can be pro grammed
to emulate many 20-pin PAL devi ces. The se architectu ral

subsets can be found in eac h of the con figuratio n modes
described in the foll owing pages. The user can downl oad
the listed sub set device JEDEC progr amming fil e to the
PLD programmer, and the ATF16V8 B c an be c onfigu re d to
act like the chosen device. Check with your programmer
manufacturer for this capability.

Unused product terms a re automatic ally disabled by the
compiler to decrease power consumption. A Security Fuse,
when programmed, protects the cont ent of the ATF16V8B .
Eight bytes (64 fuses) of User Signature are accessible to
the user for purposes such as storing project name, part
number, revision, or date. The User Signature is accessible
regardless of the state of the Security Fuse.

Note: 1. Only applicable for version 3.4 or lower.

Compiler Mode Selection

Registered Complex Simple Auto Select

ABEL, Atmel-ABEL

P16V8R P16V8C P16V8AS P16V8

CUPL

G16V8MS G16V8MA G16V8AS G16V8

LOG/iC

GAL16V8_R

(1)

GAL16V8_C7

(1)

GAL16V8_C8

(1)

GAL16V8

OrCAD-PLD

“Registered” “Com pl ex” “Simple” GAL16V8A

PLDesigner

P16V8R P16V8C P16V8C P16V8A

Tango-PLD

G16V8R G16V8C G16V8AS G16V8