ATMEL ATF1516ASL-20UI192, ATF1516ASL-20UC192, ATF1516ASL-20QI160, ATF1516ASL-20QHI208, ATF1516ASL-20QHC208 Datasheet

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High
Performance
EE-Based CPLD

ATF1516AS/L
Preliminary

Features

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High Density, High Performance Electrically Erasable Complex
Programmable Logic Device

– 256 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 160, 192, 208-pins
– 10 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 100 MHz
– Enhanced Routing Resources

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Flexible Logic Macrocell

– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output

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Advanced Power Management Features

– Automatic 3 mA Stand-By for “L” Version (Max.)
– Pin-Controlled 4 mA Stand-By Mode (Typical)
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell

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Available in Commercial and Industrial Temperature Ranges

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Available in 160-pin PQFP, 192 PGA and 208-pin RQFP Packages

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Advanced EE Technology

– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cycles
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity

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JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

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Fast In-System Programmability (ISP) via JTAG

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PCI-compliant

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3.3 or 5.0V I/O pins

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Security Fuse Feature

Enhanced Features

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Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

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Output Enable Product Terms

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D - Latch Mode

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Combinatorial Output with Registered Feedback within any Macrocell

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Three Global Clock Pins

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ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

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Fast Registered Input from Product Term

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Programmable “Pin-Keeper” Option

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VCC Power-Up Reset Option

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Pull-Up Option on JTAG Pins TMS and TDI

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Advanced Power Management Features

– Edge Controlled Power Down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O

Rev. 0994A-A–01/98

ATF1516AS/L

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Block Diagram

6 to 12

E

F

G

H

M

N

O

P

L

K

J

I

256

ATF1516AS/L

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Description

The ATF1516AS is a high pe rforman ce, hig h densi ty Com­plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven el ectrical ly erasab le techno logy. W ith 256
logic macrocells and up to 164 inputs, it easily integrates
logic from several TTL, S SI, MSI, LSI and cl assic PLDs.
The ATF1516AS’s enhanced routing switch matrices
increase usable g ate count, and increa se odd s of s uc c es s­ful pin-locked design modifications.

The ATF1516AS has up to 160 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack­age selected. Each dedicated pin can also serve as a glo­bal control signal; registe r clock, r egister reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.

Each of the 256 mac rocells ge nerates a buried feedba ck,
which goes to the globa l bus. Each in put and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus . Casca de logic be tween macroc ells
in the ATF1516AS al lows fas t, effici ent gener ation of com­plex logic functio ns. The ATF15 16AS co ntains eigh t such

logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms

The ATF1516AS macrocel l, shown in F igure 1, is flexible
enough to support hi gh ly comp lex l og ic functions operating
at high speed. The macrocell consists of five sections:
product term s and product term se lect multiplexer;
OR/XOR/CASCADE logic; a flip-flop; output select an d
enable; and logic array inputs.

Unused Macroc ell s are auto mati call y d isa bled by the com­piler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1516AS. Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Signature is
accessible regardless of the state of the Security Fuse.

The ATF1516AS device is an In-System Programmable
(ISP) device. It uses the industry standard 4-pi n JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed witho ut removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.

Figure 1.

ATF1516AS Macrocell

ATF1516AS/L

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Product Terms and Select MUX

Each ATF1516AS macrocell has five product terms. Each
product term recei ve s as i ts inp uts al l s ig nal s f ro m bo th th e
global bus and regional bus.

The product term select multip lexer ( PTMUX ) alloc ates th e
five product terms as needed to the macrocell log ic gates
and control signals. The PTMUX programming is deter­mined by the design c ompiler, which selec ts the opt imum
macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1516AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5­input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.

The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic func tions. O ne input to th e XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato­rial outputs, the fi xed level input allow s polarit y selectio n.
For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1516AS’s flip flop has very flexible data and con­trol functions. The data input can come from either the
XOR gate, from a se parate prod uct term or d irectly fr om
the I/O pin. Selecting the separate product term allows cre­ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple­mented by the fit ter so ftware). I n additi on to D , T, J K and
SR operation, the flip flop can also be configured as a flow­through latch. In this mode, da ta passes th rough whe n the
clock is high and is latched when the clock is low.

The clock itself can eith er be th e Global CLK Si gnal (GC K)
or an individual product term. The flip flop changes state on
the clock’s rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored . The f lip flop’s asynchronous re se t
signal (AR) can be either the Global Clear (G CLEAR), a
product term, or always off. A R can also be a logi c OR of
GCLEAR with a product term. The as ynchronous prese t
(AP) can be a product term or always off.

Output Select and Enable

The ATF1516AS macrocell output can be selected as reg­istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output
enable signals. A ny buffer can b e perman ently enab led for
simple output operation. Buffers ca n also be permanently
disabled to allow use of the pin as an i nput. In this confi gu­ration all the macr oce ll res our ces are s till ava ilab le, i ncl ud­ing the buried feedback, expander and CASCADE logic.
The output enable for each macrocell can be selected as
either of the two dedicated OE input pins as an I/O pin con­figured as an input, or as an individual product term.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well
as the buried fe edback signal from all 256 macr ocells.
The Switch Matrix in ea ch Logic Block receives as its
inputs all signals from the global bus. Under software con­trol, up to 40 of these signals can be selected as inputs to
the Logic Block.

Foldback Bus

Each macrocell a lso generate s a foldbac k product ter m.
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The 16 foldback te rms in eac h
region allows generation of hi gh fan -in su m ter ms (up to 21
product terms) with a small additional delay.