ATMEL ATF1508ASZ-25QI160, ATF1508ASZ-25QI100, ATF1508ASZ-25QC160, ATF1508ASZ-25JI84, ATF1508ASZ-25JC84 Datasheet

Features

•

High Density, High Performance Electrically Erasable Complex
Programmable Logic Device

– 128 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 68, 84, 100, 160-pins
– 7.5 ns Maximum Pin-to-Pin Delay
– Registered Operation Up To 125 MHz
– Enhanced Routing Resources

•

Flexible Logic Macrocell

– D/T/Latch Configurable Flip Flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic utilization by burying a register within a COM output

•

Advanced Power Management Features

– Automatic 100
– Pin-Controlled 100
– Programmable Pin-Keeper Inputs and I/Os
– Reduced-Power Feature Per Macrocell

•

Available in Commercial and Industrial Temperature Ranges

•

Available in 84-pin PLCC and 100-pin PQFP and TQFP and
160-pin PQFP Packages

•

Advanced Flash Technology

– 100% Tested
– Completely Reprogrammable
– 100 Program/Erase Cyc le s
– 20 Year Data Retention
– 2000V ESD Protection
– 200 mA Latch-Up Immunity

•

JTAG Boundary-Scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

•

Fast In-System Programmability (ISP) via JTAG

•

PCI-compliant

•

3.3 or 5.0V I/O pins

•

Security Fuse Feature

µµµµ

A Stand-By for “Z” Version (Max.)

µµµµ

A Stand-By Mode (Typical)

High
Performance
E2 PLD

ATF1508AS/Z

Enhanced Features

•

Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

•

Output Enable Product Terms

•

D - Latch Mode

•

Combinatorial Output with Registered Feedback within any Macrocell

•

Three Global Clock Pins

•

ITD ( Input Transition Detection) Circuits on Global Clocks, Inputs and I/O

•

Fast Registered Input from Product Term

•

Programmable “Pin-Keeper” Option

•

VCC Power-Up Reset Option

•

Pull-Up Option on JTAG Pins TMS and TDI

•

Advanced Power Management Features

– Edge Controlled Power Down “Z”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O for “Z” Parts

Rev. 0784C–4/98

1

I/O/PD1

VCCIO
I/O/TDI

GND

I/O/TMS

VCCIO

GND

84-Lead PLCC

Top View

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

987654321

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I/O

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333435363738394041424344454647484950515253

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I/O

VCCIO

GND

848382818079787776

I/O

I/O

GND

I/O/PD2

VCCINT

I/O/GCLK3

I/O

I/O

I/O

I/O

GND

VCCIO

I/O

100-Lead TQFP

Top View

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

GND

I/O/GCLK3

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

75
74

I/O

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I/O

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GND

71

I/O/TDO

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I/O

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I/O

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I/O

67

I/O

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VCCIO

65

I/O

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I/O

63

I/O

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I/O/TCK

61

I/O

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I/O

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GND

58

I/O

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I/O

56

I/O

55

I/O

54

I/O

I/O

I/O

VCCIO

I/O/PD1

VCCIO
I/O/TDI

GND

I/O/TMS

VCCIO

I/O

I/O
I/O
I/O
I/O
I/O
I/O

I/O
I/O
I/O

I/O
I/O

I/O
I/O
I/O
I/O
I/O
I/O
I/O

9998979695949392919089888786858483828180797877

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26272829303133333435363738394041424344454647484950

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

VCCIO

GND

VCCINT

I/O/PD2

GND

I/O

I/O

I/O

76

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I/O

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GND

73

I/O/TDO

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I/O

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I/O

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I/O

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I/O

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I/O

67

I/O

66

VCCIO

65

I/O

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I/O

63

I/O

62

I/O/TCK

61

I/O

60

I/O

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GND

58

I/O

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I/O

56

I/O

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I/O

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I/O

53

I/O

52

I/O

51

VCCIO

I/O

I/O

I/O

I/O

I/O

I/O/PD1

VCCIO
I/O/TDI

GND

I/O/TMS

VCCIO

GND

100-Lead PQFP

Top View

I/O

I/O

I/O

GND

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

99989796959493929190898887868584838281

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I/O

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I/O

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31323334353637383940414243444546474849

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

VCCIO

INPUT/OE1

INPUT/GCLK1

GND

I/O

I/O/PD2

VCCINT

I/O/GCLK3

I/O

I/O

I/O

I/O

GND

VCCIO

I/O

160-Lead PQFP

Top View

I/O

I/O/PD2

I/O

N/C

N/C

N/C

N/C

I/O

I/O

I/O

I/O

I/O

GND

I/O

I/O

I/O

I/O

VCCINT

INPUT/OE2/GCLK2

INPUT/GCLR

INPUT/OE1

INPUT/GCLK1

GND

I/O/GCLK3

I/O

I/O

I/O

VCCIO

I/O

I/O

I/O

I/O

I/O

N/C

N/C

N/C

N/C

I/O

I/O

I/O

I/O

I/O

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VCCIO
I/O/TDI

GND

I/O/TMS

VCCIO

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I/O

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N/C

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N/C

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N/C

39

N/C

40

N/C

414243444546474849505152535455565758596061626364656667686970717273747576777879

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

I/O

GND

N/C

N/C

N/C

N/C

VCCIO

GND

VCCINT

I/O/PD1

GND

I/O

80

I/O

79

I/O

78

I/O

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I/O

76

GND

75

I/O/TDO

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I/O

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I/O

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I/O

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I/O

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I/O

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I/O

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VCCIO

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I/O

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I/O

65

I/O

64

I/O/TCK

63

I/O

62

I/O

61

GND

60

I/O

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I/O

58

I/O

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I/O

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I/O

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I/O

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I/O

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VCCIO

52

I/O

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I/O

50

I/O

I/O

I/O

127

I/O

I/O

I/O

I/O

I/O

N/C

I/O

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GND

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I/O/TDO

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I/O

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I/O

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I/O

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I/O

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I/O

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I/O

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I/O

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VCCIO

103

I/O

102

I/O

101

I/O

100

I/O

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I/O/TCK

98

I/O

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I/O

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I/O

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GND

94

I/O

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I/O

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I/O

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I/O

90

I/O

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I/O

88

I/O

87

N/C

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N/C

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N/C

84

N/C

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N/C

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N/C

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N/C

80

I/O

I/O

N/C

N/C

N/C

VCCIO

2

ATF1508AS/Z

Block Diagram

6 to 12

ATF1508AS/Z

3

Description

The ATF1508AS is a high pe rforman ce, hig h densi ty Com­plex Programmable Logic Device (CPLD) which utilizes
Atmel’s proven electrically erasable Flash memory technol­ogy. With 128 logic macrocells and up to 100 inputs, it eas­ily integrates logic from several TTL, SSI, MSI, LSI and
classic PLDs. The ATF1508AS’s enhanced routing switch
matrices increa se usable ga te count , and increas e odds of
successful pin-locked design modifications.

The ATF1508AS has up to 96 bi-directional I/O pins and 4
dedicated input pins, depending on the type of device pack­age selected. Each dedicated pin can also serve as a glo­bal control signal; regi ster clock, r egister reset or output
enable. Each of these control signals can be selected for
use individually within each macrocell.

Each of the 128 mac rocells ge nerates a buried fe edback,
which goes to the gl obal bus . Each in put and I/O pin also
feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus.
Each macrocell also generates a foldback logic term, which
goes to a regional bus. Casca de logi c between macro cells
in the ATF1508AS allows fa st, effici ent gen eration of com­plex logic func tions. The ATF15 08AS co ntains eigh t such
logic chains, each capable of creating sum term logic with a
fan in of up to 40 product terms

The ATF1508A S macroc ell, sho wn in Figu re 1, is flex ible
enough to support hi ghl y comp lex l ogi c functions operating
at high speed. The macrocell consists of five sections:
product ter ms and product term select multiplexer ;
OR/XOR/CASCADE logic; a flip-flop; output selec t and
enable; and logic array inputs.

Unused Macrocel ls are a utoma tica lly disa bled by the com­piler to decrease power consumption. A Security Fuse,
when programmed, protects the contents of the
ATF1508AS. Two bytes (16 bits) of User Signature are
accessible to the user for purposes such as storing project
name, part number, revision or date. The User Si gna tur e is
accessible regardless of the state of the Security Fuse.

The ATF1508AS device is an In-System Programmable
(ISP) devic e. It uses the indu stry stand ard 4-pin JTAG
interface (IEEE Std. 1149.1), and is fully compliant with
JTAG’s Boundary Scan Description Language (BSDL). ISP
allows the device to be programmed witho ut removing it
from the printed circuit board. In addition to simplifying the
manufacturing flow, ISP also allows design modifications to
be made in the field via software.

Product Terms and Select MUX

Each ATF1508AS macrocell has five product terms. Each
product term recei ve s a s its inp u ts al l s ig nal s f ro m bo th th e
global bus and regional bus.

The product term select multip lexer ( PTMUX ) alloc ates th e
five product terms as needed to the macrocell logic gates

and control signals. The PTMUX programming is deter­mined by the design c ompiler, whi ch selects the optimu m
macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1508AS’s logic structure is designed to efficiently
support all types of logic. Within a single macrocell, all the
product terms can be routed to the OR gate, creating a 5­input AND/OR sum term. With the addition of the CASIN
from neighboring macrocells, this can be expanded to as
many as 40 product terms with a very small additional
delay.

The macrocell’s XOR gate allows efficient implementation
of compare and arithmetic fun ctions. O ne input to the XOR
comes from the OR sum term. The other XOR input can be
a product term or a fixed high or low level. For combinato­rial outputs, the fixed level input allows polarity selection.
For registered fun ctions, th e fixed leve ls allow D eMorgan
minimization of product terms. The XOR gate is also used
to emulate T- and JK-type flip-flops.

Flip Flop

The ATF1508AS’s flip flop has very flexible data and con­trol functions. The data input can com e from either the
XOR gate, from a separate product term or directly from
the I/O pin. Selecting the separate product term allows cre­ation of a buried registered feedback within a combinatorial
output macrocell. (This feature is automatically imple­mented by the fitter so ftware). I n add ition t o D, T, JK and
SR operation, the flip flop can also be configured as a flow­through latch. In th is mode, da ta passes through whe n the
clock is high and is latched when the clock is low.

The clock itself can either be th e Global CLK Si gnal (G CK)
or an individual product term. The flip flop changes state on
the clock's rising edge. When the GCK signal is used as
the clock, one of the macrocell product terms can be
selected as a clock enable. When the clock enable function
is active and the enable signal (product term) is low, all
clock edges are ignored. The flip flop’s asynchronous reset
signal (AR) can be either the G lobal Clear (GCLEA R), a
product term, or always off. A R can also be a logic OR of
GCLEAR with a prod uct term. The asynchronou s preset
(AP) can be a product term or always off.

Output Select and Enable

The ATF1508AS macrocell output can be selected as reg­istered or combinatorial. The buried feedback signal can be
either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.

The output enable multiplexer (MOE) controls the output
enable signals . Any buffer ca n be perman ently enab led for
simple output operation. Buffers ca n also be permanently
disabled to allow use of the pin as an i nput. In this confi gu­ration all the ma croce ll res our ces are still ava ilab le, i ncl ud-

4

ATF1508AS/Z

ATF1508AS/Z

ing the buried feedback, exp ander and CASCADE log ic.
The output enabl e for each macroce ll can be se lected as
one of the global OUTPU T enabl e signals . The device has
six global OE signals.

Global Bus/Switch Matrix

The global bus contains all input and I/O pin signals as well
as the buried feedback signal from all 128 macrocells.
The Switch Matrix in each Logic Block receives as its inputs
all signals from the global bus. Under software control, up
to 40 of these signals ca n be selected as inpu ts to the
Logic Block.

Foldback Bus

Each macrocell a lso genera tes a foldback product term .
This signal goes to the regional bus and is available to 16
macrocells. The foldback is an inverse polarity of one of the

macrocell’s product terms. The 16 foldback terms in each
region allows generation of hi gh fa n- in sum ter m s (up to 21
product terms) with a small additional delay.

3.3V or 5.0V I/O Operation

The ATF1508AS device has two sets of V

and V

V

CCINT

a 5.0V power supply. V

CCIO

. V

pins must always be connected to

CCINT

pins are for input buffers and

CCINT

are “compatible” with both 3.3V and 5.0V inputs. V

pins viz,

CC

CCIO

pins
are for I/O output drives and can be connected for 3.3/5.0V
power supply.

Open-Collector Output Option

This option enable s the device out put to provide c ontrol
signals such as an i nterrup t that c an be asse rted by any of
the several devices.

5

Figure 1.

ATF1508AS Macrocell

Programmable Pin-Keeper Option
for Inputs and I/Os

The ATF1508AS offers the option of program ming all input
and I/O pins so that “pin keeper” circuits can be utilized.
When any pin is driven high or low and then subsequently
left floating, it will stay at that previous high or low leve l.
This circuitry preve nts unused input and I/O l ines from
floating to intermedi ate volta ge levels , which caus e unnec­essary power consumption and system noise. The keeper
circuits eliminate the need for external pull-up resistors and
eliminate their DC power consumption.

Input Diagram

Speed/Power Management

The ATF1508AS has several built-in speed and power
management features. The ATF1508A S contains circui try
that automatically puts the device into a low power stand­by mode when no logic transitio ns are occur ring. This not
only reduces power consumption during inactive periods,
but also provides a pro portional po wer savings for most
applications running at system speeds below 5 - 10 MHz.

To further reduce power, each ATF1508AS macrocell has
a Reduced Power b it feature. This feature allows in div idual
macrocells to be configured for maximum power savings.
This feature may be selected as a design option.

I/O Diagram

6

ATF1508AS/Z

ATF1508AS/Z

All ATF1508s also have an optional power down mode. In
this mode, cur rent d rops t o below 10 mA. W hen the power
down option is selected, either PD1 or PD2 pins (or both)
can be used to power down the part. The power down
option is selecte d in the de sign so urce file . When ena bled ,
the device goes into power down when either PD1 or PD2
is high. In the power down mo de, all internal logic signa ls
are latched and held, as are any enabled outputs.

All pin transitions are ignored until the PD pin is brought
low. When the power down feature is enabled, the PD1 or
PD2 pin cannot be used as a logic input or output. How­ever, the pin’s macr ocell m ay st ill be used to gen erate bur ­ied foldback and cascade logic signals.

All Power-Down AC Ch aracteristic parameters are com­puted from external input or I/O pins, with Reduced Power
Bit turned on. For mac rocells in reduced- power mode
(Reduced power bit turned on), the reduced power adder,
tRPA, must be added to the AC param eters, whic h include
the data paths t

LAD

LAC

, tIC, t

ACL

, t

ACH

and t

SEXP

.

, t

Each output also has individua l s lew r ate c on tr ol. Thi s m ay
be used to reduce system noise by slowing down outputs
that do not need to operate at maximum speed. Outputs
default to slow switching , and may be speci fied as fast
switching in the design file.

Design Software Support

ATF1508AS des igns are su pported by s everal thi rd party
tools. Automated fitters allow logic synthesis using a variety
of high level description languages and formats.

Power Up Reset

The ATF1508AS has a power-up reset option at two differ­ent voltage trip levels when the device is being powered
down. Within the fitter, or during a conversion, if the
“power-reset” option is turned “ on” ( which is the defaul t
option), the trip levels during power up or power down is at

2.8V. The user can change this default option from “on” to
“off” (within the fitter or specify it as a switch during conver­sion). When th is is done, the volt age trip level duri ng
power-down changes from 2.8V to 0.7V. This is to ensure a
robust operating environment.

The registers in the A TF1508AS are designed to res et dur ­ing power up. At a point delayed slightl y from V

, all registers will be reset to the low state. The output

V

RST

state will depend on the polarity of the buffer.
This feature is critical for state machi ne ini tiali zation . How-

ever, due to the asynchronous nature of reset and the

crossing

CC

uncertainty of how V

actually rises in the sy stem, th e fol-

CC

lowing conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup times

must be met before driving the clock pin high, and,

3. The clock must remain stable during T

PR

.

Security Fuse Usage

A single fuse is provided to preven t unauthorized copy ing
of the ATF1508AS fuse patterns. Once programmed, fuse
verify is inhibited. However, User Signature and device ID
remains accessible.

Programming

ATF1508AS devices are In-System Programmable (ISP)
devices utilizing the 4-pin JTAG protocol. This capability
eliminates package handling normally r equi red for program
and facilitates rapid design iterations and field changes.

Atmel provides ISP hardware and so ftware to allow pro­gramming of the ATF1508AS via the PC. ISP is perfomed
by using either a downlo ad cab le, or a compar able b oard
tester or a simple microprocessor interface.

To facilitate ISP program ming by the Automated Test
Equipment (ATE) vendors, Serial Vector Format (SVF)
files can be created by Atmel provided Software utilities.

ATF1508AS devices can also be programmed using stan­dard 3rd party programmers. With 3rd party programmer
the JTAG ISP port can be disabled thereby allowing 4 addi­tional I/O pins to be used for logic.

Contact your local Atmel representatives or Atmel PLD
applications for details.

ISP Programming Protection

The ATF1508AS has a special feature which locks the
device and pr events the in puts a nd I/O from drivin g if t he
programming process is interrupted due to any reason. The
inputs and I/O default to high-Z state during such a condi­tion. In addition the pin keep er op tion pres erves the for mer
state during device programming.

All ATF1508AS devices are initially shipped in the erased
state thereby making them ready to use for ISP.

Note: For more information refer to the “Desigining for In-Sys-

tem Programmability with Atmel CPLDs” application
note.

7