ATMEL ATF1504AS, ATF1504ASL User Manual
BDTIC www.bdtic.com/ATMEL
Features
• High-density, High-performance, Electrically-erasable Complex Programmable
Logic Device
– 64 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell
– 44, 68, 84, 100 Pins
– 7.5 ns Maximum Pin-to-pin Delay
– Registered Operation up to 125 MHz
– Enhanced Routing Resources
• In-System Programmability (ISP) via JTAG
• Flexible Logic Macrocell
– D/T/Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output
• Advanced Power Management Features
– Automatic µA Standby for “L” Version
– Pin-controlled 1 mA Standby Mode
– Programmable Pin-keeper Circuits on Inputs and I/Os
– Reduced-power Feature per Macrocell
• Available in Commercial and Industrial Temperature Ranges
• Available in 44-, 68-, and 84-lead PLCC; 44- and 100-lead TQFP; and 100-lead PQFP
• Advanced EE Technology
– 100% Tested
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immunity
• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported
• PCI-compliant
• 3.3V or 5.0V I/O Pins
• Security Fuse Feature
• Green (Pb/Halide-fee/RoHS Compliant) Package Options
Highperformance
Complex
Programmable
Logic Device
ATF1504AS
ATF1504ASL
Enhanced Features
• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)
• Output Enable Product Terms
• Transparent – Latch Mode
• Combinatorial Output with Registered Feedback within Any Macrocell
• Three Global Clock Pins
• ITD (Input Transition Detection) Circuits on Global Clocks, Inputs and I/O
• Fast Registered Input from Product Term
• Programmable “Pin-keeper” Option
• V
Power-up Reset Option
CC
• Pull-up Option on JTAG Pins TMS and TDI
• Advanced Power Management Features
– Edge-controlled Power-down “L”
– Individual Macrocell Power Option
– Disable ITD on Global Clocks, Inputs and I/O
Rev. 0950O–PLD–7/05
1
I/O/TDI
GND
PD1/I/O
TMS/I/O
VCC
44-lead TQFP
Top View
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
I/OE1
GCLK1/I
GND
GCLK3/I/O
I/O
4443424140393837363534
33
1
2
I/O
3
I/O
4
5
6
I/O
7
8
I/O
9
10
I/O
11
I/O
1213141516171819202122
I/O
I/O
I/O
I/O
I/O
I/O
GND
VCC
I/O
PD2/I/O
I/O
32
I/O/TDO
31
I/O
30
I/O
29
VCC
28
I/O
27
I/O
26
I/O/TCK
25
I/O
24
GND
23
I/O
I/O
TDI/I/O
I/O
I/O
GND
PD1/I/O
I/O
I/O/TMS
I/O
VCC
I/O
I/O
44-lead PLCC
Top View
I/O
I/O
I/O
VCC
GCLK2/OE2/I
GCLR/I
OE1/I
GCLK1/I
65432
7
8
9
10
11
12
13
14
15
16
17
1819202122232425262728
I/O
I/O
1
4443424140
I/O
I/O
I/O
VCC
GND
PD2/I/O
GND
GCLK3/I/O
I/O
I/O
I/O
39
I/O
38
I/O/TDO
37
I/O
36
I/O
35
VCC
34
I/O
33
I/O
32
I/O/TCK
31
I/O
30
GND
29
I/O
I/O
VCCIO
I/O/TD1
GND
I/O/PD1
I/O/TMS
VCCIO
GND
68-lead PLCC
Top View
I/O
I/O
I/O
GND
I/O
I/O
VCCINT
GCLK2/OE2/I
GCLR/I
OE1/I
987654321
10
I/O
11
12
13
I/O
14
I/O
15
I/O
16
17
18
I/O
19
20
I/O
21
22
I/O
23
I/O
24
I/O
25
I/O
26
2728293031323334353637383940414243
I/O
I/O
I/O
I/O
I/O
VCCIO
I/O
GND
VCCINT
68676665646362
I/O
GCLK1/I
GND
GND
I/O/PD2
GCLK3/I/O
I/O
VCCIO
I/O
I/O
I/O
I/O
I/O
I/O
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
VCCIO
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O/TCK
I/O
GND
I/O
I/O
I/O
I/O
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
GND
84-lead PLCC
Top View
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
GCLK2/OE2/I
I/GCLR
I/OE1
GCLK1/I
GND
987654321
11
10
12
I/O
13
14
15
I/O
16
I/O
17
I/O
18
I/O
19
20
21
I/O
22
I/O
23
24
I/O
25
I/O
26
27
I/O
28
I/O
29
I/O
30
I/O
31
I/O
32
333435363738394041424344454647484950515253
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
848382818079787776
I/O
I/O
I/O
GND
VCCINT
I/O/PD2
GCLK3/I/O
I/O
I/O
I/O
I/O
GND
VCCIO
1/O
I/O
I/O
I/O
I/O
I/O
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
VCCIO
I/O
I/O
GND
I/O/TDO
I/O
I/O
I/O
I/O
VCCIO
I/O
I/O
I/O
I/O/TCK
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
2
ATF1504AS(L)
0950O–PLD–7/05
ATF1504AS(L)
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
GND
100-lead PQFP
Top View
I/O
I/O
I/O
I/O
I/O
GND
I/O
I/O
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
INPUT/OE1
INPUT/GCLK1
GND
I/O/GCLK3
I/O
I/O
VCCIO
I/O
I/O
I/O
99989796959493929190898887868584838281
100
1
NC
2
NC
3
I/O
4
I/O
5
6
7
NC
8
I/O
9
NC
10
I/O
11
I/O
12
I/O
13
14
15
I/O
16
I/O
17
18
I/O
19
I/O
20
21
I/O
22
I/O
23
I/O
24
NC
25
I/O
26
NC
27
I/O
28
29
NC
30
NC
31323334353637383940414243444546474849
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VCCIO
GND
VCCINT
GND
I/O/PD2
I/O
80
NC
79
NC
78
I/O
77
I/O
76
GND
75
I/O/TDO
74
NC
73
I/O
72
NC
71
I/O
70
I/O
69
I/O
68
VCCIO
67
I/O
66
I/O
65
I/O
64
I/O/TCK
63
I/O
62
I/O
61
GND
60
I/O
59
I/O
58
I/O
57
NC
56
I/O
55
NC
54
I/O
53
VCCIO
52
NC
51
NC
50
I/O
I/O
I/O
VCCIO
I/O/TDI
GND
I/O/PD1
I/O/TMS
VCCIO
NC
1
NC
2
3
4
NC
5
I/O
6
NC
7
I/O
8
I/O
9
I/O
10
11
12
I/O
13
I/O
14
15
I/O
16
I/O
17
18
I/O
19
I/O
20
I/O
21
NC
22
I/O
23
NC
24
I/O
25
I/O
9998979695949392919089888786858483828180797877
100
26272829303132333435363738394041424344454647484950
NC
NC
GND
100-lead TQFP
I/O
I/O
GND
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Top View
I/O
VCCINT
INPUT/OE2/GCLK2
INPUT/GCLR
I/O
I/O
I/O
VCCIO
INPUT/OE1
INPUT/GCLK1
GND
I/O
GND
VCCINT
I/O/GCLK3
I/O
I/O
I/O
GND
I/O/PD2
VCCIO
I/O
I/O
I/O
I/O
I/O
I/ONCNC
I/O
I/O
I/O
76
I/O
75
GND
74
I/O/TDO
73
NC
72
I/O
71
NC
70
I/O
69
I/O
68
I/O
67
VCCIO
66
I/O
65
I/O
64
I/O
63
I/O/TCK
62
I/O
61
I/O
60
GND
59
I/O
58
I/O
57
I/O
56
NC
55
I/O
54
NC
53
I/O
52
VCCIO
51
NC
NC
0950O–PLD–7/05
3
Description The ATF1504AS is a high-performance, high-density complex programmable logic
device (CPLD) that utilizes Atmel’s proven electrically-erasable memory technology.
With 64 logic macrocells and up to 68 inputs, it easily integrates logic from several TTL,
SSI, MSI, LSI and classic PLDs. The ATF1504AS’s enhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modifications.
The ATF1504AS has up to 68 bi-directional I/O pins and four dedicated input pins,
depending on the type of device package selected. Each dedicated pin can also serve
as a global control signal, register clock, register reset or output enable. Each of these
control signals can be selected for use individually within each macrocell.
Each of the 64 macrocells generates a buried feedback that goes to the global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals from the global bus. Each macrocell also generates a foldback logic term that goes to a regional bus. Cascade logic between
macrocells in the ATF1504AS allows fast, efficient generation of complex logic functions. The ATF1504AS contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.
The ATF1504AS macrocell, shown in Figure 1, is flexible enough to support highly-complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.
4
ATF1504AS(L)
0950O–PLD–7/05
Block Diagram
ATF1504AS(L)
I/O (MC64)/GCLK3
Unused product terms are automatically disabled by the compiler to decrease power
consumption. A security fuse, when programmed, protects the contents of the
ATF1504AS. Two bytes (16 bits) of User Signature are accessible to the user for purposes such as storing project name, part number, revision or date. The User Signature
is accessible regardless of the state of the security fuse.
The ATF1504AS device is an in-system programmable (ISP) device. It uses the industry-standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully-compliant with JTAG’s
Boundary-scan Description Language (BSDL). ISP allows the device to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.
0950O–PLD–7/05
5
Product Terms and Select Mux
OR/XOR/CASCADE Logic The ATF1504AS’s logic structure is designed to efficiently support all types of logic.
Flip-flop The ATF1504AS’s flip-flop has very flexible data and control functions. The data input
Each ATF1504AS macrocell has five product terms. Each product term receives as its
possible inputs all signals from both the global bus and regional bus.
The product term select multiplexer (PTMUX) allocates the five product terms as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with a little small additional delay.
The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high- or low-level. For combinatorial outputs, the fixed level
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.
can come from either the XOR gate, from a separate product term or directly from the
I/O pin. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell. (This feature is automatically implemented
by the fitter software). In addition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this mode, data passes through when the clock is
high and is latched when the clock is low.
The clock itself can be either one of the Global CLK Signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on the clock’s rising edge. When the GCK signal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signal (product term) is
low, all clock edges are ignored. The flip-flop’s asynchronous reset signal (AR) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a logic
OR of GCLEAR with a product term. The asynchronous preset (AP) can be a product
term or always off.
Output Select and Enable The ATF1504AS macrocell output can be selected as registered or combinatorial. The
buried feedback signal can be either combinatorial or registered signal regardless of
whether the output is combinatorial or registered.
The output enable multiplexer (MOE) controls the output enable signals. Any buffer can
be permanently enabled for simple output operation. Buffers can also be permanently
disabled to allow use of the pin as an input. In this configuration all the macrocell
resources are still available, including the buried feedback, expander and CASCADE
logic. The output enable for each macrocell can be selected as either of the two dedicated OE input pins as an I/O pin configured as an input, or as an individual product
term.
Global Bus/Switch Matrix The global bus contains all input and I/O pin signals as well as the buried feedback sig-
nal from all 64 macrocells. The switch matrix in each logic block receives as its possible
inputs all signals from the global bus. Under software control, up to 40 of these signals
can be selected as inputs to the logic block.
6
ATF1504AS(L)
0950O–PLD–7/05
ATF1504AS(L)
Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional
bus and is available to four macrocells. The foldback is an inverse polarity of one of the
macrocell’s product terms. The sixteen foldback terms in each region allow generation
of high fan-in sum terms (up to sixteen product terms) with a nominal additional delay.
Figure 1. ATF1504AS Macrocell
0950O–PLD–7/05
7
Programmable Pinkeeper Option for
Inputs and I/Os
Input Diagram
The ATF1504AS offers the option of programming all input and I/O pins so that pinkeeper circuits can be utilized. When any pin is driven high or low and then subsequently left floating, it will stay at that previous high- or low-level. This circuitry prevents
unused input and I/O lines from floating to intermediate voltage levels, which causes
unnecessary power consumption and system noise. The keeper circuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.
Speed/Power Management
I/O Diagram
The ATF1504AS has several built-in speed and power management features. The
ATF1504AS contains circuitry that automatically puts the device into a low-power
standby mode when no logic transitions are occurring. This not only reduces power consumption during inactive periods, but also provides proportional power savings for most
applications running at system speeds below 5 MHz. This feature may be selected as a
device option.
To further reduce power, each ATF1504AS macrocell has a Reduced Power bit feature.
This feature allows individual macrocells to be configured for maximum power savings.
This feature may be selected as a design option.
All ATF1504AS also have an optional power-down mode. In this mode, current drops to
below 10 mA. When the power-down option is selected, either PD1 or PD2 pins (or
both) can be used to power-down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.
8
ATF1504AS(L)
0950O–PLD–7/05
ATF1504AS(L)
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell may still be used to generate buried foldback and cascade logic
signals.
All power-down AC characteristic parameters are computed from external input or I/O
pins, with Reduced Power Bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, tRPA, must be added to the
AC parameters, which include the data paths t
The ATF1504AS macrocell also has an option whereby the power can be reduced on a
per macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned-down, thereby reducing the overall power consumption
of the device.
Each output also has individual slew rate control. This may be used to reduce system
noise by slowing down outputs that do not need to operate at maximum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.
LAD
, t
LAC
, tIC, t
ACL
, t
ACH
and t
SEXP
.
Design Software Support
ATF1504AS designs are supported by several industry-standard third-party tools. Automated fitters allow logic synthesis using a variety of high level description languages
and formats.
Power-up Reset The ATF1504AS is designed with a power-up reset, a feature critical for state machine
initialization. At a point delayed slightly from V
tialized, and the state of each output will depend on the polarity of its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
system, the following conditions are required:
1. The V
rise must be monotonic,
CC
2. After reset occurs, all input and feedback setup times must be met before driving
the clock pin high, and,
3. The clock must remain stable during T
The ATF1504AS has two options for the hysteresis about the reset level, V
and Large. During the fitting process users may configure the device with the Power-up
Reset hysteresis set to Large or Small. Atmel POF2JED users may select the Large
option by including the flag “-power_reset” on the command line after “filename.POF”.
To allow the registers to be properly reinitialized with the Large hysteresis option
selected, the following condition is added:
4. If V
falls below 2.0V, it must shut off completely before the device is turned on
CC
again.
When the Large hysteresis option is active, I
amps as well.
crossing V
CC
.
D
is reduced by several hundred micro-
CC
, all registers will be ini-
RST
actually rises in the
CC
RST
, Small
Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF1504AS fuse pat-
terns. Once programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.
0950O–PLD–7/05
9
Programming ATF1504AS devices are in-system programmable (ISP) devices utilizing the 4-pin JTAG
protocol. This capability eliminates package handling normally required for programming
and facilitates rapid design iterations and field changes.
Atmel provides ISP hardware and software to allow programming of the ATF1504AS via
the PC. ISP is performed by using either a download cable or a comparable board tester
or a simple microprocessor interface.
To facilitate ISP programming by the Automated Test Equipment (ATE) vendors. Serial
Vector Format (SVF) files can be created by Atmel provided software utilities.
ATF1504AS devices can also be programmed using standard third-party programmers.
With third-party programmer, the JTAG ISP port can be disabled thereby allowing
four additional I/O pins to be used for logic.
Contact your local Atmel representatives or Atmel PLD applications for details.
ISP Programming Protection
The ATF1504AS has a special feature that locks the device and prevents the inputs and
I/O from driving if the programming process is interrupted for any reason. The inputs
and I/O default to high-Z state during such a condition. In addition the pin-keeper option
preserves the former state during device programming, if this circuit were previously
programmed on the device. This prevents disturbing the operation of other circuits in the
system while the ATF1504AS is being programmed via ISP.
All ATF1504AS devices are initially shipped in the erased state thereby making them
ready to use for ISP.
Note: For more information refer to the “Designing for In-System Programmability with Atmel
CPLDs” application note.
10
ATF1504AS(L)
0950O–PLD–7/05
ATF1504AS(L)
DC and AC Operating Conditions
Commercial Industrial
Operating Temperature (Ambient) 0°C - 70°C-40°C - 85°C
or V
V
CCINT
(3.3V) Power Supply 3.0V - 3.6V 3.0V - 3.6V
V
CCIO
(5V) Power Supply 5V ± 5% 5V ± 10%
CCIO
DC Characteristics
Symbol Parameter Condition Min Typ Max Units
I
IL
I
IH
I
OZ
I
CC1
I
CC2
(2)
I
CC3
V
CCIO
V
CCIO
V
IL
V
IH
V
OL
V
OH
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input or I/O Low
Leakage Current
Input or I/O High
Leakage Current
Tri-state Output
Off-state Current
Power Supply Current,
Standby
Power Supply Current,
Power-down Mode
Current in Reduced-power
Mode
Supply Voltage 5.0V Device Output
V
IN
= V
CC
-2 -10 µA
210
= VCC or GND -40 40 µA
V
O
Com. 105 mA
Ind. 130 mA
Com. 10 µA
Ind. 10 µA
Com 85 ma
Ind 105
VCC = Max
V
= 0, V
IN
VCC = Max
= 0, V
V
IN
VCC = Max
= 0, VCC
V
IN
Std Mode
CC
“L” Mode
“PD” Mode 1 10 mA
CC
Std Power
Com. 4.75 5.25 V
Ind. 4.5 5.5 V
Supply Voltage 3.3V Device Output 3.0 3.6 V
Input Low Voltage -0.3 0.8 V
Input High Voltage 2.0 V
Output Low Voltage (TTL)
Output Low Voltage (CMOS)
Output High Voltage (TTL)
= VIH or V
V
IN
V
= MIN, IOL = 12 mA
CCIO
= VIH or V
V
IN
IL
IL
VCC = MIN, IOL = 0.1 mA
V
= VIH or V
IN
V
= MIN, IOH = -4.0 mA
CCIO
IL
Com. 0.45 V
Ind.
Com. .2 V
Ind. .2 V
2.4 V
+ 0.3 V
CCIO
2. When macrocell reduced-power feature is enabled.
Pin Capacitance
Typ Max Units Conditions
C
IN
C
I/O
Note: Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
The OGI pin (high-voltage pin during programming) has a maximum capacitance of 12 pF.
0950O–PLD–7/05
810 pF V
810 pF V
IN
OUT
= 0V; f = 1.0 MHz
= 0V; f = 1.0 MHz
11
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