ATMEL ATF1502ASV User Manual

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Features

• High-density, High-performance, Ele ctr ically-erasable Complex Programm able

Logic Device

– 3.0 to 3.6V Operati ng Range
– 32 Macrocells
– 5 Product Terms per Macrocell, Expandable up to 40 per Macr ocell
–44 Pins
– 15 ns Maximum Pin-to-pin Delay
– Registered Operation up to 77 MHz
– Enhanced Routing Resources

• In-System Progr am ma bility (ISP) via JTAG

• Flexible Logic Macrocell

– D/T Latch Configurable Flip-flops
– Global and Individual Register Control Signals
– Global and Individual Output Enable
– Programmable Output Slew Rate
– Programmable Output Open Collector Option
– Maximum Logic Utilization by Burying a Register with a COM Output

• Advanced Power Management Feat ures

– Pin-contr oll ed 0.75 mA Standby Mode
– Programmable Pin-keeper Inputs and I/Os
– Reduced-power Feature per Macrocell

• Avai lable in Commercial and Industrial Temperature Ranges

• Av ailable in 44-lead PLCC and TQFP

• Advanced EEPROM Technology

– 100 % Test ed
– Completely Reprogrammable
– 10,000 Program/Erase Cycles
– 20-year Data Retention
– 2000V ESD Protection
– 200 mA Latch-up Immun ity

• JTAG Boundary-scan Testing to IEEE Std. 1149.1-1990 and 1149.1a-1993 Supported

• PCI-compliant

• Security Fuse Feature

High­performance
EEPROM CPLD

ATF1502ASV

Enhanced Features

• Improved Connectivity (Additional Feedback Routing, Alternate Input Routing)

• Output Enable Product Terms

• D Latch Mode

• Combinatorial Output with Registered Feedback within Any Macrocell

• Three Global Clock Pins

• Fast Registered Input from Product Term

• Programmable “Pin-keeper” Option

• V

Power-up Reset Option

CC

• Pull-up Option on JTAG Pins TMS and TDI

• Advanced Power Management Feat ures

– Individual Macrocell Power Option

Rev. 1615H–PLD–2/04

1

I/O/TDI

GND

PD1/I/O

TMS/I/O

VCC

I/O
I/O

I/O

I/O

I/O
I/O

44-lead TQFP

Top View

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

4443424140393837363534

1
2
3
4
5
6
7
8
9
10
11

1213141516171819202122

I/O

I/O

I/O

I/O

VCC

GND

44-lead PLCC

Top View

I/OE1

I/O

GCLK1/I

GND

I/O

PD2/I/O

GCLK3/I/O

I/O

33
32
31
30
29
28
27
26
25
24
23

I/O

I/O

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

I/O

I/O

I/O

VCC

GCLK2/OE2/I

GCLR/I

OE1/I

GCLK1/I

GND

GCLK3/I/O

I/O

TDI/I/O

I/O
I/O

GND

PD1/I/O

I/O

I/O/TMS

I/O

VCC

I/O
I/O

65432

7
8
9
10
11
12
13
14
15
16
17

1819202122232425262728

I/O

I/O

I/O

I/O

GND

1

VCC

4443424140

I/O

I/O

I/O

PD2/I/O

39
38
37
36
35
34
33
32
31
30
29

I/O

I/O
I/O/TDO
I/O
I/O
VCC
I/O
I/O
I/O/TCK
I/O
GND
I/O

Description The ATF1502ASV is a high-performance, high-density complex programmable logic

device (CPLD) that utilizes A tmel’s proven electrically-erasable technology. With 32
logic macrocells and up to 36 inputs, it easily integrates logic from several TTL, SSI,
MSI, LSI and classic PLDs. The ATF1502ASV’s e nhanced routing switch matrices
increase usable gate count and the odds of successful pin-locked design modificat ions.

The ATF1502ASV has up to 32 bi-directional I/O pins and four dedicated input pins,
depending o n the t ype of d evice pac kage se lected . Eac h dedica ted pi n can also se rve
as a global co ntrol signa l, registe r clock, regi ster reset or output enable . Each of the se
control signals can be selected for use individually within each macrocell.

2

ATF1502ASV

1615H–PLD–2/04

Block Diagram

ATF1502ASV

B

32

Each of the 32 macrocells generates a buried feedback that goes to t he global bus.
Each input and I/O pin also feeds into the global bus. The switch matrix in each logic
block then selects 40 individual signals f rom the glob al bus. Each m acroc ell also gener­ates a foldb ack logic term that goes to a regional bus . Cascade log ic between
macrocells in the ATF1502ASV allows fast, efficient generation of complex logic func­tions. The ATF1502ASV contains four such logic chains, each capable of creating sum
term logic with a fan-in of up to 40 product terms.

The ATF1502ASV macroc ell, shown in Figure 1, is flexible enough to support highly
complex logic functions operating at high speed. The macrocell consists of five sections:
product terms and product term select multiplexer, OR/XOR/CASCADE logic, a flip-flop,
output select and enable, and logic array inputs.

1615H–PLD–2/04

Unused product t erms are automatically disabled by the compiler to decrease power
consum ption. A se curity fus e, when pro grammed , protects the conten ts of the
ATF1502ASV. Two bytes (16 bits) of User Signature are accessible to the user for pur­poses such as storing project name, part number, revision or date. The User Signat ure
is accessible regardless of the state of the security fuse.

The ATF1502ASV device is an in-system programmab le ( ISP) device. It uses the indus­try standard 4-pin JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s

3

Figure 1. ATF1502A SV Ma crocel l

Boundary-scan Description Language (BSDL). ISP allows the device to be programmed
without removing it from the printed circuit board. In addition to simplifying the manufac­turing flow, ISP also allows design modifications to be made in the field via software.

Product Terms and
Select Mux

OR/XOR/
CASCADE Logic

4

ATF1502ASV

Each ATF1502ASV macrocell has five product terms. Each product term receives as its
inputs all signals from both the global bus and regional bus.

The product term select multiplexer (PTMUX) allocates the five product term s as
needed to the macrocell logic gates and control signals. The PTMUX programming is
determined by the design compiler, which selects the optimum macrocell configuration.

The ATF15 02ASV’s lo gic structur e is design ed to effici ently suppo rt all types of logic.
Within a single macrocell, all the product terms can be routed to the OR gate, creating a
5-input AND/OR sum term. With the addition of the CASIN from neighboring macrocells,
this can be expanded to as many as 40 product terms with little additional delay.

The macrocell’s XOR gate allows efficient implementation of compare and arithmetic
functions. One input to the XOR comes from the OR sum term. The other XOR input can
be a product term or a fixed high or low level. For combin atorial outputs, the fixed le vel
input allows polarity selection. For registered functions, the fixed levels allow DeMorgan
minimization of product terms. The XOR gate is also used to emulate T- and JK-type
flip-flops.

1615H–PLD–2/04

ATF1502ASV

Flip-flop The ATF1502A SV’s flip-flop h as very flexibl e data and control func tions. The dat a input

can com e fro m eit her the X OR gate , from a sepa ra te produ ct t erm o r directl y from the
I/O pin. Selecting the separat e product term allows creation of a buried registered feed­back within a combinatorial output macrocell. (This feature is automatically implemented
by the fitter software). In a ddition to D, T, JK and SR operation, the flip-flop can also be
configured as a flow-through latch. In this m ode, da ta p asse s throug h when the clock is
high and is latched when the clock is low.

The clock itself can be either one of the Global CLK signals (GCK[0 : 2]) or an individual
product term. The flip-flop changes state on t he clock’s rising edge. When the GCK sig­nal is used as the clock, one of the macrocell product terms can be selected as a clock
enable. When the clock enable function is active and the enable signa l (product term) is
low, all clock edges a re igno red. T he flip-fl op’s asy nchrono us re set sign al (AR ) can be
either the Global Clear (GCLEAR), a product term, or always off. AR can also be a l ogic
OR of G CLE AR with a p rodu ct ter m. The asy nchro no us pre se t (AP) can be a pr oduc t
term or always off.

Extra Feedback The ATF1502ASV mac rocell output can be selected as registered or combinatorial.The

extra burie d fee dback signa l can be eith er com binato rial or a regist ered s ign al rega rd­less of whether the output is combinatorial or registered. (This enhancement function is
automatically implemented by the fitter software.) Feedback of a buried combinatorial
output allows the creation of a second latch within a macrocell.

I/O Control The output enable multiplexer (MOE) controls the output enable signal. Each I/O can be

individually configured as an input, output or for bi-directional operation. The output
enable for each macrocell can be selected from the true or compliment of the two output
enable pins, a subset of the I/O pins, or a subs et of the I /O macr ocell s. This se lection is
automatically done by the fitter software when the I/O is configured as an input, all mac­rocell resources are still available, including the buried feedback, expander and cascade
logic.

Global Bus/Switch Matrix The global bus cont ains all input and I/O p in sign als as wel l as t he buried feedback sig-

nal from all 32 macrocells. The switch matrix in each logic block receives as its inputs all
signals from the global bus. Under software control, up to 40 of these signals can be
selected as inputs to the logic block.

Foldback Bus Each macrocell also generates a foldback product term. This signal goes to the regional

bus and is availa ble to four m ac roc ells. T he foldback is an inverse pola rity of on e of the
macrocell’s product terms. The four foldback terms in each region allow generation of
high fan-in sum terms (up to nine product terms) with little additional delay.

Prog rammable Pin­keeper Option for
Inputs and I/Os

The ATF1502ASV offers the option of programming all input and I/O pins so that pin­keeper circuits can be utilized. When any pin is driven high or low and then subse­quently left float ing, it will stay at t hat previous high or low le vel. This circui try prev ents
unused input and I/O lines from floating to intermediate voltage levels, whic h causes
unnecessary power consumption and system noise. The keeper c ircuits eliminate the
need for external pull-up resistors and eliminate their DC power consumption.

1615H–PLD–2/04

5

Input Diagram

V

CC

I/O Diagram

INPUT

DATA

OE

ESD

PROTECTION

CIRCUIT

V

CC

100K

PROGRAMMABLE

OPTION

I/O

V

CC

100K

Speed/Power
Management

6

ATF1502ASV

PROGRAMMABLE

OPTION

The ATF1502ASV has several built-in speed and power managem ent features.
To further reduce power, each ATF1502ASV macrocell has a reduced-power bit feature.

To reduce power consumption this feature may be actived (by changing the default
value of OFF to ON) for any or all macrocells.

The ATF1502ASV also has an optional power-down mode. In this mode, current drops
to belo w 15 m A. Wh en t he pow er- down o pti on is se lect ed, e ither PD 1 o r PD2 pins ( or
both) can be used to power down the part. The power-down option is selected in the
design source file. When enabled, the device goes into power-down when either PD1 or
PD2 is high. In the power-down mode, all internal logic signals are latched and held, as
are any enabled outputs.

All pin transitions are ignored until the PD pin is brought low. When the power-down fea­ture is enabled, the PD1 or PD2 pin cannot be used as a logic input or output. However,
the pin’s macrocell m ay still be used to generate buried foldback and cascade logic
signals.

1615H–PLD–2/04

ATF1502ASV

All powe r-d own AC cha rac teristi c pa ramet ers a re co mp uted f rom exte rnal inpu t or I /O
pins, with reduced-power bit turned on. For macrocells in reduced-power mode
(reduced-power bit turned on), the reduced-power adder, t
parameters, which include the data paths t

LAD

, t

LAC

, tIC, t

The ATF1502ASV mac rocell also has an option whereby the po wer can be reduced on
a per-macrocell basis. By enabling this power-down option, macrocells that are not used
in an application can be turned down, thereby reducing the ov erall power cons umptio n
of the device.

Each ou tput a ls o has i ndiv idua l slew ra te cont rol. T his m ay be us ed to redu ce s ystem
noise by slowing down outputs that do not ne ed to op erate at max imum speed. Outputs
default to slow switching, and may be specified as fast switching in the design file.

, must be added to the AC

RPA

, t

ACL

ACH

and t

SEXP

.

Design Software
Support

ATF1502ASV designs are supported by several third-party tools. Automated fitters allow
logic synthesis using a variety of high-level description languages and formats.

Power-up Reset The ATF1502ASV is designed with a power-up reset, a feature critical for state machine

initi aliz atio n. At a p oin t d ela yed sli gh tly fr om V
tialized, an d the stat e of eac h outpu t will dep end on t he pol arity o f its buffer. However,
due to the asynchronous nature of reset and uncertainty of how V
system, the following conditions are required:

1. The V

rise must be monotonic,

CC

2. After reset occurs, all input and feedback setup times must be met before
driving the clock pin high, and,

3. The clock must remain stable during T

The ATF1502ASV has two options for th e hysteresis about the reset level, V
and Large. To ensure a robus t operat ing enviro nment in applicatio ns whe re the devic e
is operated near 3.0V, Atmel recommends that during the fitting process users configure
the device with the Power-up Reset hysteresis set to Large. For conversions, Atmel
POF2JED users should include the flag “-power_reset” on th e command line after “file­name.POF”. To allow the reg isters to be properly rei nitialized with the La rge hysteresis
option selected, the following condition is added:

4. If V

falls below 2.0V, it mu st shut off completely before the device is turned

CC

on again.

When the Large hysteresis option is active, I
amps as well.

crossing V

CC

.

D

is reduced by several hundred micro-

CC

, all reg is ter s wi ll be in i-

RST

actually rises in the

CC

RST

, Small

Security Fuse Usage A single fuse is provided to prevent unauthorized copying of the ATF150 2ASV fuse pat-

terns. Onc e programmed, fuse verify is inhibited. However, the 16-bit User Signature
remains accessible.

Programming ATF1502ASV devices are in-system programmable (ISP) devices utilizing the 4-pin

JTAG protocol. This capability eliminates package handling normally required for pro­gramming and facilitates rapid design iterations and field changes.

Atmel pro vides I SP ha rdware and softwa re to a llow pr ogram ming o f the A TF150 2AS V
via the PC. IS P is performed by using either a download cable, a c omparable board
tester or a simple microprocessor interface.

1615H–PLD–2/04

7