ATMEL ATF1500ABV-12JC, ATF1500ABV-12AC, ATF1500ABVL-25JC, ATF1500ABVL-25AC, ATF1500ABV-15JI Datasheet

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Features

Operates Between 2.7V to 5.5V

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High Density, High-Performance Electrically Erasable Complex

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Programmable Logic Device

– 44-Pin, 32 I/O CPLD – 12 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 90.9 MHz – Fully Connected Input and Feedback Logic Array

Flexible Logic Macrocell

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– D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate

Advanced Power Management Features

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– Automatic 3 mA Stand-By (ATF1500ABVL) – Pin-Controlled 5 – Programmable Pin-Keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

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Available in 44-Pin PLCC and TQFP Pack ages

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Advanced Flash Technology

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– 100% Tested – Completely Reprogrammable – 100 Program/Erase Cyc le s – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity

Supported By Popular 3rd Party Tools

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Security Fuse Feature

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µµµµ

A Stand-By Mode (Typical)

HighPerformance EE PLD

ATF1500ABV ATF1500ABVL ATF1500ABV/L

Description

The ATF1500ABV is a hi gh performance , high density Co mplex PLD. Built on an advanced Flash technology, it has maximum pin to pin delays of 12 ns and supports sequential logic ope ration at speeds up to 90.9 MHz. With 32 logic macr oce lls a nd u p to 36 inputs, it easily integrates logic from several TTL, SS I, MSI and classic PLDs. The ATF1500ABV’s global input a nd feedb ack arc hitectur e simpli fies logic pla cemen t and eliminates pinout changes due to design changes.

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Pin Configurations

1 2 3 4 5 6 7 8 9 10 11

TQFP

Top View

VCC

I/O

I/O/PD

424340

I/O

GCLR/I

OE2/I

VCC

GND

OE1/I

I/O

CLK/I

GND

192021

I/O

30 29

VCC

I/O

GND

I/O

Pin Name Function

CLK Clock I Logic Inputs

I/O

GCLR

OE1, OE2

Bidirectional Buffers

Output Enable (active low)

(+3V to 5.25V) Supply

Power Down (active high)

PLCC

Top View

INDEX CORNER

I/O I/O I/O

GND

I/O I/O I/O I/O

VCC

I/O I/O

Rev. 0723D–6/98

Functional Logic Diagram

(1)

Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.

ATF1500ABV/L

The ATF1500ABV has 32 bi-directional I/O pins and 4 dedicated input pins. Each dedicated input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Each of the 32 logic macrocells generates a buried feedback, which goes to th e global bus. Each in put and I/O pin also feeds into the global bus. Because of this global bussing, each of these signals is always available to all 32 macrocells in the device.

Each macrocell also generates a foldback logic term, which goes to a regional b us . Al l s i gnal s with in a r egional bus are connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500ABV allows fast, efficient generation of complex logic functions. The ATF1500AB V contains 4 such log ic chains, each capable of creatin g sum te rm lo gic wi th a fan in of up to 40 product terms.

Bus Friendly Pin-Keeper Input and I/O’S

All Input and I/O pins on the ATF1500ABV have programmable “data keeper” circui ts. If activated, when any pi n is driven high or low and t hen su bsequently left floating, it will stay at that previous high or low level.

This circuitry prevents un used Input and I/O lines from floating to inter mediat e volt age leve ls, whic h caus e unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

Pin-keeper circuits c an be di sabled. Pr ogramming is co ntrolled in the logic design file. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.

Speed/Power Management

The ATF1500ABV has several built-in s peed and power management features. The ATF1500ABV contains circuitry that automatically puts the device into a low power standby mode when no logic trans itions are oc curring. This not only reduces power consumption during inactive periods, but also prov ides a p roportion al power savings for most applications running at system speeds below 10 MHz.

All ATF1500AB Vs also have an op tional pin-contr olled power down mode. In this mod e, c urre nt d rops to b elo w 10 µA. When the power down op tion i s sel ec ted , the P D pi n i s used to power down the part. The power down option is selected in the design source file. When enab led, the device goes into power down wh en the PD pin i s high. In the power down mode, all internal logic signal s are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD is brou ght low. W hen the po wer down feature is ena bled, the PD c annot be used as a logi c inp ut or output. However, the PD pin's macrocell may still be used to generate buried foldb ack and cascade log ic signals.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

Design Software Support

ATF1500ABV designs are support ed by several 3rd party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.

Input Diagram

INPUT

ESD

PROTECTION

CIRCUIT

100K

PROGRAMMABLE

OPTION

I/O Diagram

DATA

I/O

100K

PROGRAMMABLE

OPTION

ATF1500ABV Macrocell

The ATF1500ABV macrocell is flexib le enough to su pport highly complex logi c functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplex er; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs.

Product Terms and Select Mux

Each ATF1500ABV macrocell has five product terms. Each product term recei v es as its i nputs all signals from both the global bus and regional bus.

The product term selec t multi plex er (PTMU X) allo cates the five product terms as needed to the macrocel l logic g ates and control signals. The PTMUX programming is determined by the design compiler, wh ich sel ects the opti mum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1500ABV macrocell's OR/XOR/CASCADE l ogic structure is designed to efficiently support all types of logic. Within a single mac rocell, all the product terms can be routed to the OR gate, creating a five input AND/OR sum

ATF1500ABV/L

term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay.

The macrocell's XOR gate allows efficient implementation of compare and arithmeti c function s. One inpu t to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows output polarity selection. For regi stered functions, the fixed levels allow De Morgan minimization of the product terms. The XOR gate is also used to emulate JK type flip flops.

Flip Flop

The ATF1500ABV’s flip fl op has very flexible data and control functions. The data input can come from either the XOR gate or from a separate product term. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell.

In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode,

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