ATMEL ATF1500A-15AI, ATF1500A-15AC, ATF1500A-12JI, ATF1500A-12JC, ATF1500A-12AI Datasheet

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Features

High Density, High Performance Electrically Erasable Complex

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Programmable Logi c De vic e

– 44-Pin, 32 I/O CPLD – 7.5 ns Maximum Pin-to-Pin Delay – Registered Operation Up To 125 MHz – Fully Connected Input and Feedback Logic Array – Backward Compatibility with ATF1500/L Software and Hardware

Flexible Logic Macrocell

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D/T/Latch Configurable Flip Flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate

Advanced Power Management Features

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– Automatic 3 mA Stand-By (ATF1500AL) – Pin-Controlled 5 µA Stand-By Mode (Typical) – Programmable Pin-Keeper Inputs and I/Os

Available in Commercial and Industrial Temperature Ranges

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Available in 44-Pin PLCC and TQFP Packages

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Advanced Flash Technology

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– 100% Tested – Completely Reprogrammable – 100 Program/Erase Cycles – 20 Year Data Retention – 2000V ESD Protection – 200 mA Latch-Up Immunity

Supported By Popular 3rd Party Tools

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Security Fuse Feature

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High Performance E PLD

ATF1500A/AL

Description

The ATF1500A is a high performance, high density Complex PLD. Built on an advanced Flash techn ology , it has m aximum pin to pin d elays of 7 .5 ns and suppo rts sequential logic operati on at speeds up to 125 MHz . With 32 logic macrocells and up to 36 inputs, it easily integrates log ic from several TTL, SSI, MSI and classic PLDs. The ATF1500A's global input and feedback architecture simplifies logic placement and eliminates pinout changes due to design changes.

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Pin Configurations

Pin Name Function

CLK Clock I Logic Inputs

I/O

GCLR

OE1, OE2

Bidirectional Buffers

Output Enable (active lo w)

+5V Supply Power Down

(active high)

PLCC

Top View

INDEX CORNER

I/O I/O I/O

GND

I/O I/O I/O I/O

VCC

I/O I/O

1 2 3 4 5 6 7 8 9 10 11

TQFP

VCC

I/O

I/O/PD

424340

I/O

Top View

GCLR/I

OE2/I

VCC

GND

OE1/I

I/O

CLK/I

GND

192021

I/O

30 29

VCC

I/O

GND

I/O

Rev. 0759C–04/98

Functional Logic Diagram

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Note: 1. Arrows connecting macrocells indicate direction and groupings of CASIN/CASOUT data flow.

ATF1500A/AL

The ATF1500A has 32 bi-dir ectional I/O pins and 4 dedicated input pins. Each dedica ted input pin can also serve as a global control signal: register clock, register reset or output enable. Each of these control signals can be selected for use individually within each macrocell.

Each of the 32 logic macrocells generates a buried feedback, which goes to th e global bus. Each in put and I/O pin also feeds into the global bus. Because of this global bussing, each of these signals is always available to all 32 macrocells in the device.

Each macrocell also generates a foldback logic term, which goes to a regional b us . Al l s i gnal s with in a r egional bus are connected to all 16 macrocells within the region.

Cascade logic between macrocells in the ATF1500A allows fast, efficient generation of complex logic fu nctions. The ATF1500A contains 4 such logic chains, each capable of creating sum term logic with a fan in of up to 40 pr oduct terms.

Bus Friendly Pin-Keeper Input and I/O’s

All Input and I/O pins on the ATF1500A have programmable “data keep er” circuit s. If activat ed, when any pin is driven high or low and t hen su bsequently left floating, it will stay at that previous high or low level.

This circuitry prevents un used Input and I/O lines from floating to inter mediat e volt age leve ls, whic h caus e unnecessary power consumption and system noise. The keeper circuits eliminate the need for external pull-up resistors and eliminate their DC power consumption.

Pin-keeper circuits c an be di sabled. Pr ogramming is co ntrolled in the logic design file. Once the pin-keeper circuits are disabled, normal termination procedures are required for unused inputs and I/Os.

Speed/Power Management

The ATF1500A has several built-in sp eed and power man agement features. The ATF1500A contain s circuitry that automaticall y puts t he de vice into a lo w power stand-b y mode when no logic transitions are occurring. This not only reduces power consumption duri ng inactive periods, but also provides a proportional power savings for most applications running at system speeds below 10 MHz.

All ATF1500As also have an optional pin-controlled power down mode. In this mode, current drops to below 10 µA. When the power down option is selected, the PD pin is used to power down the part. The power down option is selected in the design source file. When enab led, the device goes into power down wh en the PD pin i s high. In the power down mode, all internal logic signal s are latched and held, as are any enabled outputs. All pin transitions are ignored until the PD is brou ght low. W hen the po wer down feature is ena bled, the PD c annot be used as a logi c inp ut or output. However, the PD pin's macrocell may still be used to generate buried foldb ack and cascade log ic signals.

Each output also has individual slew rate control. This may be used to reduce system noise by slowing down outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified as fast switching in the design file.

Design Software Support

ATF1500A designs are supported by several 3rd party tools. Automated fitters allow logic synthesis using a variety of high level description languages and formats.

Input Diagram

INPUT

ESD

PROTECTION

CIRCUIT

100K

PROGRAMMABLE

OPTION

I/O Diagram

DATA

I/O

100K

PROGRAMMABLE

OPTION

ATF1500A/AL Macrocell

ATF1500A Macrocell

The ATF1500A macro cell is flexible enoug h to support highly complex logic functions operating at high speed. The macrocell consists of five sections: product terms and product term select multiplexer; OR/XOR/CASCADE logic; a flip flop; output select and enable; and logic array inputs.

Product Terms and Select Mux

Each ATF1500A macrocell has fiv e product terms. Each product term recei v es as its i nputs all signals from both the global bus and regional bus.

The product term selec t multi plex er (PTMU X) allo cates the five product terms as needed to the macrocel l logic g ates and control signals. The PTMUX programming is determined by the design compiler, wh ich sel ects the opti mum macrocell configuration.

OR/XOR/CASCADE Logic

The ATF1500A macrocell's OR/XOR/CASCADE logic structure is designed to efficiently support all types of logic. Within a single mac rocell, all the product terms can be

ATF1500A/AL

routed to the OR gate, creating a five input AND/OR sum term. With the addition of the CASIN from neighboring macrocells, this can be expanded to as many as 40 product terms with a very small additional delay.

The macrocell's XOR gate allows efficient implementation of compare and arithmeti c function s. One inpu t to the XOR comes from the OR sum term. The other XOR input can be a product term or a fixed high or low level. For combinatorial outputs, the fixed level input allows output polarity selection. For registered functions, the fixed levels allow De Morgan minimization of the product terms. The XOR gate is also used to emulate JK type flip flops.

Flip Flop

The ATF1500A's flip flo p has ve ry fl exib le d ata a nd con trol functions. The data input can come from either the XOR gate or from a separate product term. Selecting the separate product term allows creation of a buried registered feedback within a combinatorial output macrocell.

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ATF1500A/AL

In addition to D, T, JK and SR operation, the flip flop can also be configured as a flow-through latch. In this mode, data passes through when the clock is high and is latched when the clock is low.

The clock itself ca n be eit her the gl obal CL K pin or an indi vidual prod uct term. The flip flop chan ges stat e on the clock's rising edge. When the CLK pin is used as the clock, one of the macrocell product terms can be selected as a clock enable. W hen the clock enab le fu nctio n is act ive and the enable sign al (prod uct ter m) is lo w, all cloc k edge s are ignored.

The flip flop's asynchronous reset signal (AR) can be either the pin global clear (GCLR), a product term, or always off. AR can also be a logic O R of GCLR with a p roduct te rm. The asynchronous preset (AP) can be a product term or always off.

Output Select and Enable

The ATF1500A macro cell out put can be selec ted as reg istered or combinatori al. When the output is regis tered, the same registered s ignal is fed ba ck internall y to the global bus. When the output is combinatorial, the buried feedback can be either the same combinatorial signal or it can be the register output if the separate product term is chosen as the flip flop input.

The output enable multiplexer (MOE) controls the output enable signals. Any buf fer can be pe rmanen tly enabled for simple output operation. Buffers c an also be permanently disabled to allow use of the pin as an input. In thi s con figuration all the macroc ell reso urces are still avai lable, in cluding the buried feedback, expander and CASCADE logic.

The output enable for eac h mac rocell can also be s elect ed as either of the two OE pins or as an individual product term.

Global/Regional Busses

The global bus contains all Input and I/O pin signals as well as the buried feed back signal from al l 32 macrocells. Together with the complemen t of eac h s ign al, t his pr ov id es a 68 bit bus as input to every product ter m. Having the entire global bus available to each macrocell eliminates any potential rout ing prob lems. With this arch itecture d esigns can be modified without requiring pinout changes.

Each macrocell also generat es a foldback product term. This signal goes to the regi onal bus , and is a vailabl e to 16 macrocells. The foldback is an inverse polarity of one of the macrocell's product terms. T he 16 foldb ack terms in ea ch region allow generation of high fan-in sum terms (up to 21 product terms) with a small additional delay.

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