Atmel ATA6264 User Manual

Features

• Maximum Supply Voltage 40V

• One Programmable/Adjustable Boost Converter

• Two Programmable Buck Converters

• One Programmable Linear Regulator

• OTP Customer Mode

• 16-bit Serial Interface

• Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality)

• Watchdog

• Various Diagnosis Functions

• 5 Voltage Sources Tailored to Resistor Measurement

• Charge Pump

• Small, 44-pin Package

• ESD Protection Against 2kV and 4kV

1. Description

With the introduction of the ATA6264, Atmel® introduces a new generation of airbag power supplies for future airbag systems tailored to the needs of the automotive industry. It is designed in Atmel’s 0.8 micron BCDMOS technology. ATA6264 contains all the necessary blocks to supply the microcontroller, the firing capacitors, and peripheral components of the airbag system. The power supply specifically fulfills the power requirements of dual-voltage microcontrollers used in modern ECUs. The integrated watchdog and diagnosis blocks additionally support the safety aspects. The 8-MHz 16-bit SPI enables a high communication speed. Despite the high-level functionality, ATA6264 comes in a space-saving QFP44 package.

Airbag Power Supply IC

ATA6264

Preliminary

4929B–AUTO–01/07

Figure 1-1. Block Diagram

SVSAT

VSAT

V

BATT

RESQ

RESQ2

GNDD

TxD1

RxD1

TxD2

RxD2

K1

K2

IASG1

IASG2

IASG3

IASG4

IASG5

ISENS

MOSI

SSQ

MISO

Serial Interface

Watchdog

Reset

ISO9141

IASG

SCLK

CP_OUT

CP Logic

CP

GKEY-

Logic

EVZ-

Regulator

VSAT-

Regulator

VPERI-

Regulator

K15

K30

GEVZ

OCEVZ

GNDB

EVZ

FBEVZ

COMEVZO

SVSAT

COMSATO

COMSATI

VSAT

SVPERI

VPERI

V

VPERI

V

EVZ

VSAT

SVCORE

UZP

GNDA

2

ATA6264 [Preliminary]

UZP

V

BATT

AMUX

USP

Internal Supply

Reference

VINT

IREF

VCORE-

Regulator

VCORE

COMCOI

COMCOO

V

VCORE

4929B–AUTO–01/07

1.1 Block Description

1.1.1 Integrated Boost Converter EVZ

With an external n-channel FET, the integrated boost converter EVZ provides 3 different voltages adjustable via the serial interface for the energy reserve and firing capacitors. Two voltages are fixed values; one voltage can be adjusted using an external resistive divider.

1.1.2 Integrated Buck Converter VSAT

The integrated buck converter VSAT is a fully integrated step-down converter supplied by the boost converter, EVZ, and providing 7.8V, 9.1V, or 10.4V. The user can program the voltage via an OTP system.

1.1.3 Integrated Buck Converter VCORE

The integrated buck converter VCORE is a fully integrated step-down converter supplied either by the boost converter, EVZ, or by the battery, and providing 1.88V, 2.5V, or 5V. The user can program the voltage via an OTP system.

1.1.4 Linear Regulator VPERI

The linear regulator, VPERI, is supplied from the buck converter VSAT and provides an accurate voltage of 3.3V ±3% or 5V ±4% as a supply for sensitive elements such as sensors and ADC references with the current capability of 100 mA. The user can program the voltage via an OTP system. With a sophisticated power-sequencing concept of VCORE and VPERI, ATA6264 supports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference between the two linear regulator voltages never drops below a defined value. This measure guarantees the safe operation of the system.

ATA6264 [Preliminary]

1.1.5 Blocks Included

• A general purpose comparator USP, for, for example, low battery voltage detection

• A band gap as reference for all internal voltages and currents

• Two ISO9141 interfaces, one of which is configurable via OTP in accordance with the LIN specification

• Five constant voltage sources with current-to-voltage mirrors used for resistance measurements, such as buckle switch detection in the range from –0.5 mA to –40 mA

• An AMUX block with push-pull buffer stage provides the output of all analog values such as voltage sources, low voltage detection, or the chip temperature for continuous diagnosis

• A 16-bit serial interface for the communication with the microcontroller which includes a 16-bit shift register, a 16-bit latch, and a decoder-logic block

• A watchdog to monitor the microcontroller and to generate reset signals in the case of failure

• Internal oscillator generates internal clock signals

• GKEY function to control the main switch of the ECU via a logic signal

4929B–AUTO–01/07

3

2. Pin Configuration

Figure 2-1. Pinning QFP44

COMEVZO

GNDB

GEVZ

OCEVZ

FBEVZCPSVCORE

CP-OUT

COMCOO

COMCOI

COMSATO

44 43 42 41 35 343638 373940

1

USP

K30

2

K1

3

K2

4

IASG1 IASG2 IASG3 IASG4 IASG5 ISENS

TxD1

5 6 7 8 9 10 11

12 13 14 15 21 222018 191716

RxD2

RxD1

RESQ

TxD2

MISO

SSQ

Table 2-1. Pin Description

Pin Symbol Function

1 USP Comparator input 2 K30 Continuous connection to the car battery 3 K1 Bus line of 1 4 K2 Bus line of 2 5 IASG1 Output of voltage source 1 6 IASG2 Output of voltage source 2 7 IASG3 Output of voltage source 3 8 IASG4 Output of voltage source 4

9 IASG5 Output of voltage source 5 10 ISENS Output of the current mirror from the IASGx interface 11 TXD1 Data input of the 1 12 RESQ Reset output 13 RXD2 Data output of the 2 14 RXD1 Data output of the 1st ISO9141 interface 15 TXD2 Data input of the 2 16 MISO Data output of the serial interface 17 SSQ Chip select of the serial interface 18 SCLK Clock input of the serial interface 19 MOSI Data input of the serial Interface 20 RESQ2 Redundant reset output 21 IREF Connection for the external reference resistor 22 UZP Analog measurement output

st

ISO9141 interface

nd

ISO9141 interface

st

ISO9141 interface

nd

ISO9141 interface

nd

ISO9141 interface

MOSI

SCLK

IREF

RESQ2

33 32 31 30 29 28 27 26 25 24 23

UZP

K15 EVZ SVSAT VSAT GNDD VINT COMSATI VCORE GNDA SVPERI VPERI

4

ATA6264 [Preliminary]

4929B–AUTO–01/07

Table 2-1. Pin Description

Pin Symbol Function

23 VPERI Input for the VPERI regulator, internally used VPERI supply 24 SVPERI Output of VPERI regulator power transistor 25 GNDA Analog GND 26 VCORE Input for VCORE regulator 27 COMSATI Input of the VSAT externally compensated error amplifier 28 VINT Output of internal supply voltage 29 GNDD Digital GND 30 VSAT Input for VSAT regulator, internally used VSAT supply 31 SVSAT Output of VSAT regulator power transistor 32 EVZ Input for EVZ regulator, internally used EVZ supply 33 K15 Connection to car battery via the ignition key 34 COMSATO Output of the VSAT externally compensated error amplifier 35 COMCOI Input of the VCORE externally compensated error amplifier 36 COMCOO Output of the VCORE externally compensated error amplifier 37 CP-OUT Switchable output of charge pump voltage 38 SVCORE Output of VCORE regulator power transistor 39 CP Charge pump output 40 FBEVZ Input for external resistor divider to adjust EVZ voltage 41 OCEVZ Input for overcurrent measurement of the EVZ regulator 42 GEVZ Gate driver output for the external FET of the EVZ regulator 43 GNDB GND connection of all power stages 44 COMEVZO Output of the EVZ externally compensated error amplifier

ATA6264 [Preliminary]

4929B–AUTO–01/07

5

3. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.

Parameters Remark Minimum Maximum Unit

Any combination of one or more pins

applied with any voltage between the Voltage at pins, connected directly or indirectly to the car battery (K30, K15, USP)

Voltage at pins, connected directly or indirectly to the car battery (K1, K2)

Voltage at pins, connected directly or indirectly to the car battery (IASG1, IASG2, IASG3, IASG4, IASG5)

Voltage at ECU internal pins (FBEVZ, EVZ, VSAT)

Maximum rate of change at pin VSAT 1V/µs

Voltage at ECU internal pins (SVSAT, SVCORE)

Voltage at ECU internal pins (CP, CP-OUT)

Voltage at ECU internal pins (GEVZ, OCEVZ)

Voltage at ECU internal pins (COMEVZO, COMSATO, COMSATI, VPERI, SVPERI, VCORE, COMCOI, COMCOO, IREF, UZP, ISENS, RXD1, TXD1, RXD2, TXD2, RESQ, RESQ2, MISO, MOSI, SSQ, SCLK, VINT)

Current at logic pins

ESD classification at pins connected to devices outside the ECU (K30, K15)

limits

K30 and K15 connected via diode to V

USP connected via minimum 5 kΩ to V

(maximum reverse current 5 mA).

Any combination of one or more pins

applied with any voltage between the

limits

Any combination of one or more pins

applied with any voltage between the

limits

Any combination of one or more pins

applied with any voltage between the

limits

Any combination of one or more pins

applied with any voltage between the

limits

Any combination of one or more pins

applied with any voltage between the

limits

Any combination of one or more pins

applied with any voltage between the

limits

These voltages can be applied in any

combination with any voltage between the

limits

Connected to voltages outside of

maximum voltage ratings via resistor

Batt

–0.3 +45 V

.

–25 +45 V

Voltage

necessary to

drive –40 mA

stored in 20 µH

–0.3 +45 V

–1 +45 V

–0.3 +56 V

–0.3 +10 V

–0.3 +7 V

–3 +3 mA

45 V

Human body model (HBM) HBM

AEC Q100-002

6

ATA6264 [Preliminary]

±4000 V

4929B–AUTO–01/07

ATA6264 [Preliminary]

3. Absolute Maximum Ratings (Continued)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.

Parameters Remark Minimum Maximum Unit

ESD classification at pins connected to devices outside the ECU (IASG1 to IASG5)

Human body model (HBM) HBM

AEC Q100-002 ESD classification at pins connected to

devices outside the ECU (K1 and K2)

Human body model (HBM) HBM

AEC Q100-002 General ESD classification for all other

pins

Human body model (HBM)

Charged device model (CDM) – no corner pins

Charged device model (CDM) – corner pins

HBM

AEC Q100-002

CDM

ESD STM5.3.1-1999

±3000 V

±2500 V

±1500

±500

±750

V

4929B–AUTO–01/07

7

4. Functional Range

Within the functional range, the ATA6264 works as specified. All voltages are referenced to the ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.

At the beginning of each specification table, supply voltage and temperature conditions are described.

Table 4-1. Electrical Characteristics – Functional Range

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

Voltage on pins K30, K15,

1.1 USP

1.1a Voltage on pins K1, K2 –25 +40 V Rate of supply voltage rise

1.2 (K30, K15, K1, K2)

1.3 Supply voltage EVZ –0.3 +40 V

1.4 Supply voltage VSAT –0.3 +14 V Supply voltages VCORE,

1.5 VPERI

1.6 Supply voltage CP, CP-OUT –0.3 +50 V

1.7 Voltage on digital I/O pins –0.3 +5.5 V Voltage on pins SVSAT,

1.8 SVCORE

Voltage on pins UZP, ISENS, COMCOI,

1.9

COMCOO, COMSATO, COMSATI, COMEVZO, FBEVZ, IREF, VINT

Voltage on pins GEVZ,

1.10 OCEVZ

1.11 Voltage on pin SVPERI –0.3 +6 V

Voltage on pins IASGx

1.12 (x = 1 to 5)

Temperatures: Operating ambient temperature range

1.14

Operating junction temperature range Storage ambient/junction temperature range

Thermal resistance junction

1.15 ambient

Substrate current which can be drawn without

1.16 disturbances to upper

defined blocks/functions

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. No substrate current occurs at pins K1, K2 down to V

(1)

, VK2 > –25V

K1

–0.3 +40 V

–0.3 +5.5 V

–1.0 +40 V

–0.3 +5.5 V

–0.3 +10 V

Voltage

necessary to

drive –40 mA

stored in 20 µH

– 40

– 55

–40 mA

+ 90

+150

+105

50 V/µs

40 V

°C

60 K/W

8

ATA6264 [Preliminary]

4929B–AUTO–01/07

4.1 Protection Against Substrate Currents

Due to the fact that the ATA6264 is connected to the wiring harness and to components outside of the ECU, negative voltages at the following pins might occur:

• IASG interface: IASG1, IASG2, IASG3, IASG4, IASG5

• USP comparator: USP

If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the following blocks and functions will happen:

• No disturbance of RESET block.

• No voltage changes of any regulators outside of their tolerances.

• No impact on digital circuitry (for example, changes of latches, status register, etc.)

• No latch up of any circuitry

ATA6264 [Preliminary]

4929B–AUTO–01/07

9

5. Supply Currents

A minimum current has to flow into each pin for proper functioning of the IC.

Table 5-1. Electrical Characteristics – Supply currents

No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*

2.1 Supply current at K30

2.1a Supply current at K30

Standby mode: V

= 3V and KEYLATCH = OFF

K15

Standby mode:

= 3V and KEYLATCH = OFF

V

K15

0V = V

18V < V

Startup mode: 0V < V

2.1b Supply current at K30

2.1c Supply current at K30

2.1d Supply current at K30

V

> 4.15V or KEYLATCH = ON,

K15

V

= 0V, CCP = 47 nF

EVZ

Startup mode:

> 4.15V or KEYLATCH = ON

V

K15

V

= 0V, CCP = 47 nF

EVZ

Normal mode: V

> V

EVZ

K30

0V < V

, V

K15

18V < V

> 4V or KEYLATCH = ON, SVCORE open, AMUX Measurement K30 active

Normal mode: 18V < V V

> V

, V

2.1e Supply current at K30

EVZ

K30

KEYLATCH = ON, SVCORE open,

> 4.15V or

K15

AMUX Measurement K30 active Startup mode: 0V < V

2.2 Supply current at EVZ

V V

SAT K30

= V >5V, V

= V

PERI

CORE

> 4.15V, SVCORE

K15

and SVSAT open Normal mode: 0V < V

2.2a Supply current at EVZ

and V

V

PERI

Threshold, V

= 10V, V

V

SAT

> 4.15V, SVCORE and

V

K15

CORE

EVZ

K30

> Reset

> V

> 5V,

SVSAT open, AMUX Measurement EVZ active

Autonomous mode: 0V < V

EVZ

= 40V, V

> Reset Threshold, V

2.2b Supply current at EVZ

V

= 10V, V

SAT

< 3V, SVCORE and SVSAT

V

K15

< 3.85V,

K30

open, AMUX Measurement EVZ active

2.3 Supply current at VSAT

Supply current at

2.4 VPERI

Supply current at

2.5 VCORE

0V < V AMUX measurement VSAT active

0V < V measurement VPERI active

0V < V measurement VCORE active

= 14V, SVPERI open,

SAT

= 5.3V, AMUX

PERI

= 5.3V, AMUX

CORE

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

= 0V,

K30

PERI

K30

EVZ

,

and V

EVZ

= 18V,

= 40V,

= 18V,

= 40V

= 18V,

= 40V,

CORE

> V

K30

,

K30

K30 I

K30

EVZ

VSAT

VPERI

VCORE

I

K30

I

K30

I

K30

I

K30

I

EVZ

I

EVZ

I

EVZ

I

VSAT

I

VPERI

I

VCORE

050µAA

05mAA

07mAA

010mAA

06.5mAA

010mAA

05mAA

06mAA

010mAA

01.5mAA

–0.2 2.2 mA A

–0.45 1 mA A

10

ATA6264 [Preliminary]

4929B–AUTO–01/07

5.1 Discharger Circuit

e

Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure

5-1) in the power supply to prevent any damage if the wrong polarity is applied to V

nately, this method includes some risk as can be seen in the following description:

ATA6264 [Preliminary]

. Unfortu-

K30

During Standby mode (V I

. Any peaks on the supply voltage (V

K30

K15

capacitor (C1). D1 prevents the capacitor from being discharged via the power supply and the very small quiescent current via the IC can also be neglected. This means that during long periods of Standby mode, the IC’s supply voltage could increase continuously until finally the maximum supply voltage limit would be exceeded and the IC could be damaged. ATA6264 therefore features a discharger circuit which avoids such unwanted effects. If V threshold value of approximately 26.8V, the blocking capacitor is discharged via an integrated resistor until V

again falls below the threshold.

K30

Figure 5-1. Discharger Circuit

5.2 Initial Programming of the ATA6264

The ATA6264 supports different output voltages at the VSAT, VPERI and the VCORE regulators. In addition, different modes at the ISO9141 interfaces can be adjusted at the initial programming (IP). The memory cells are one-time programmable (OTP) and cannot be changed after the IP (default values are “0”). In general, the IP is done after mounting the ATA6264 on the PCB with an in-circuit tester. The programming voltage of 11.7V has to be applied on pin VSAT. It is also possible to use the VSAT regulator as the programming voltage because VSAT is programmed to 11.7V (±0.5V) as long as the Test mode is entered and the lock bit is not set. To ensure proper programming of the ATA6264, at least a 10-µF electrolytic cap and a 100-nF ceramic cap have to be applied at pin VSAT.

< 3V and KEYLATCH = OFF) the IC consumes only a low current,

in Figure 5-1) will gradually charge the blocking

Pulse

exceeds a

K30

C18 kΩ

26.8V

D1

V

Batt

V

Puls

4929B–AUTO–01/07

11

The following settings can be made at the initial programming:

MSBit LSBit

VR1 VR2 VR3 VR4 EXT ISO/LIN Parity Lock bit

Table 5-2. Initial Programming Settings

VR1 VR2 VR3 VR4 VCORE VPERI VSAT

0 0 0 0 All regulators deactivated (default) 0 0 0 1 1.88V 3.3V 7.8V 0 0 1 0 1.88V 3.3V 9.1V 0 0 1 1 1.88V 3.3V 10.4V 0 1 0 0 2.5V 3.3V 7.8V 0 1 0 1 2.5V 3.3V 9.1V 0 1 1 0 2.5V 3.3V 10.4V 0 1 1 1 1.88V 5V 7.8V 1 0 0 0 1.88V 5V 9.1V 1 0 0 1 1.88V 5V 10.4V 1 0 1 0 2.5V 5V 7.8V 1 0 1 1 2.5V 5V 9.1V 1 1 0 0 2.5V 5V 10.4V 1 1 0 1 5V 5V 7.8V 1 1 1 0 5V 5V 9.1V 1 1 1 1 5V 5V 10.4V

12

Set to 0 Set to 1

EXT No external transistor at VPERI (default) External transistor at VPERI applied

Set to 0 Set to 1

ISO/LIN ISO9141 mode is activated at K1 (default) LIN mode is activated at K1

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set, the programming will not be executed.

Figure 5-2. Programming Sequence

Contact pins RESQ, RESQ2

TxD1, TxD2, SSQ, MOSI,

SCLK, VPERI, K15, K30

Apply 12V at K15, K30 and5V

Set RESQ and TxD1 to GND

and RESQ2 and TxD2 to 5V

Transmit IP command A9xx(h)

via SPI to configure ATA6264

at VPERI

Transmit 5A5A(h) via SPI

to Enable Testmode

Wait until VSAT = 11.7V

Wait 1 ms

4929B–AUTO–01/07

Remove all voltages and pinloads

to get out of Test mode

13

5.3 Start-up and Power-down Procedure

E

The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is connected to the ignition key line K15. In order to detect an interruption on one of these pins correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from the backup power supply capacitor hooked up to pin EVZ.

Figure 5-3. Block Diagram Start-up and Power-down Procedure

K15

V

= 3V to 4.15V

K15

(40 mV to 175mV Hysteresis)

Serial interface (KEY - LATCH)

= 3.85V to 5V

V

K30

(50 mV to 150 mV Hysteresis)

V

= 6.1V to 8.1V (ON)

K30

(0.5V to 1V Hysteresis)

V

= 7.5V to 9V (ON)

EVZ

V

= 5.5V to 6.2V (OFF)

EVZ

V

= 6.77V to 7.2V

SAT

(200 mV to 500 mV Hysteresis)

K15GOOD

Comp

K30GOOD

Comp

CORESWAP

Comp

EVZGOOD

Comp

VSATGOOD

Comp

5V

IREF lost

signal

Power

sequencing

VEVZ

K30

CP

VK30

VEVZ driver

IP

VCP

VSAT driver

VEVZ

VPERI

driver

GEVZEVZEN

EVZ

SVSAT

VSAT

SVPER

VPERI

V

CP

V

EVZ

V

VSAT

V

VPERI

14

CORE_EN

V

= 1.25V to 1.7V

PERI

(50 mV to 150 mV Hysteresis)

Comp

ATA6264 [Preliminary]

driver

VCP

K30

EVZ

SVCORE

VCORE

V

VCOR

4929B–AUTO–01/07

IP

VCORE

VCore

ATA6264 [Preliminary]

Depending on the initial programming of the ATA6264, the start-up procedure takes place in different phases.

5.3.1 Start-up Procedure if V

is Programmed to Be 5V or 2.5V

VCORE

Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the

voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via the serial interface.

Phase2: If V

is larger than 7.5V to 9V the VSAT regulator starts operating and the VCORE

EVZ

regulator will be enabled. Phase3: After V

has reached 6.77V to 7.2V, the VPERI regulator starts working. The

VSAT

VCORE regulator starts operating depending on the charge pump voltage.

5.3.2 The Power-down Procedure Takes Place in Different Phases Phase1: If the ignition key is switched off, K15 voltage will vanish at pin K15. If the serial inter-

face command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in Perma- nent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.

Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops to low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending on the charge-pump voltage, the VCORE regulator stops working.

Phase3: When the voltage at the EVZ capacitor gets to be lower than 5.5V to 6.2V, VSAT is switched off.

4929B–AUTO–01/07

15

Figure 5-4. Start-Up and Power-Down Procedure if V

V

K30

V

K15

3V to 4.15V3V to 4.15V

Programmed to Be 5V or 2.5V

VCORE

t

Threshold to enable VCORE regulator

Threshold to start VCORE regulator

5.3.3 Start-up Procedure if V Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15. If, in addi-

tion, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be set by the serial interface.

V

GEVZ

V

EVZ

V

VSAT

V

VPERI

V

VCORE

Programmed to Be 1.88V

VCORE

7.5V to 9V

too low EVZ voltage VSAT goes into On Mode charge pump deactivated

6.77V to 7.2V 7V to 6.27V

t

5.5V to 6.2V

t

16

Phase2: If VEVZ is larger than 7.5V to 9V, the VSAT regulator starts operating. Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working. Phase4: If VVPERI is higher than 1.25V to 1.7V, the VCORE regulator will be enabled.

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

5.3.4 The Power-down Procedure for V Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial

interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Permanent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.

Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops too low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending on the charge-pump voltage, the VCORE regulator stops working. The power sequencing function for the VPERI regulator is still active and guarantees a maximum voltage difference between VPERI and VCORE of 2.8V

Phase3: After VVPERI becomes lower than 1.1V to 1.55V, the VCORE regulator has to stop working.

Phase4: When the voltage at the EVZ capacitor is lower than 5.5V to 6.2V, VSAT is switched off.

Figure 5-5. Start-up and Power-down Procedure if V

V

K30

is Programmed to be 1.88V

VCORE

Programmed to Be 1.88V

VCORE

V

VCORE

V

K15

GEVZ

V

EVZ

VSAT

VPERI

7.5V to 9V

3V to 4.15V3V to 4.15V

too low EVZ voltage VSAT goes into On Mode charge pump deactivated

t

5.5V to 6.2V

t

7V to 6.27V6.77V to 7.2V

t

1.1V to 1.55V1.25V to 1.7V

t

4929B–AUTO–01/07

17

6. Power Supply Sequencing

(Only active when initial programming sets V

In order to meet the requirements of several dual-voltage-supply microcontrollers, a power-sequencing function is implemented. The ATA6264 ensures that the voltage difference VPERI – VCORE will not exceed 2.8V.

The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold. In this case, the VPERI regulator is switched off before reaching this level and switched on again if the voltage difference drops below a hysteresis value.

Figure 6-1. Example for Incorrect Ramp Up

V

VPERI

3.3V

= 1.88V and V

VCORE

VPERI

= 3.3V)

V

VCORE

1.88V

Not allowed area:

- V

V

VPERI

VCORE

>

2.8V

t

Necessary for operation:

t

V

= 0V to 40V, V

EVZ

= 3.7V to 5.47V

INT

Operating conditions of all other supply pins: V

K30

, V

VSAT

, V

VPERI

and V

are within functional range limits, Tj = –40°C to 150°C

VCORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 6-1. Electrical Characteristics – Power Supply Sequencing

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Maximum voltage difference

5.1

5.2a

5.2b

– V

V

VPERI

VCORE

Voltage level V switch off VPERI regulator

Hysteresis for V enable VPERI regulator

VPERI

– V

VCORE

to

VPERI,

VCORE

VPERI,

VCORE

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

V

– V

V

– V

VPERI

VCORE

VPERI

VCORE

V

HYS

02.8VA

2.3 2.8 V A

100 mV A

18

ATA6264 [Preliminary]

4929B–AUTO–01/07

Figure 6-2. Block Diagram Power Supply Sequencing

E

ATA6264 [Preliminary]

K15

V

= 3V to 4.15V

K15

(40 mV to 175mV Hysteresis)

Serial interface (KEY - LATCH)

= 3.85V to 5V

V

K30

(50 mV to 150 mV Hysteresis)

V

= 6.1V to 8.1V (ON)

K30

(0.5V to 1V Hysteresis)

V

= 7.5V to 9V (ON)

EVZ

V

= 5.5V to 6.2V (OFF)

EVZ

V

= 6.77V to 7.2V

SAT

(200 mV to 500 mV Hysteresis)

K15GOOD

Comp

K30GOOD

Comp

CORESWAP

Comp

EVZGOOD

Comp

VSATGOOD

Comp

5V

IREF lost

signal

IP

VEVZ

VEVZ driver

VSAT driver

VPERI

driver

VK30

VCP

VEVZ

K30

CP

GEVZEVZEN

EVZ

SVSAT

VSAT

SVPER

VPERI

V

CP

V

EVZ

V

VSAT

V

VPERI

4929B–AUTO–01/07

Delta

< 2.8V

V

CORE

- Regulator

SVCORE

VCORE

V

VCOR

19

7. Charge Pump

To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs driven by the high charge pump voltage V

to ensure that they can be switched to a low-ohmic

CP

(1)

are

state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be connected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be implemented for proper function of the charge pump. An external series resistor is recommended to suppress spikes during switching of the SVSAT. The CP block is supplied by EVZ and VSAT voltage and starts to operate as soon as the thresholds for VK15, K30 and EVZ are achieved. An additional start-up circuitry is implemented to support the VSAT driver during the start-up phase, thus enabling a reliable system startup.

The charge pump has an output CP-OUT to supply the external circuitry, and can be switched via the SPI. It is capable of 250 µA.

Figure 7-1. Block Diagram Charge Pump

External circuit

CP-Out

Status

register

I = 1.4 mA

CP

Serial

interface

Note: 1. Connected to the drivers (see Figure 5-3)

EVZ

SVSATVSAT

REFREF

Status

register

20

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Necessary for operation: V

= 5.5V to 40V or V

EVZ

Operating conditions of all other supply pins: V

VSAT

, V

VPERI

and V

VCORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 7-1. Electrical Characteristics – Charge Pump

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

6.11 Supply current at pin CP

Time between wrong CP-OUT

6.12

voltage and valid data in status register

Current limitation at pin

6.13 CP-OUT

Voltage difference VCP – V

6.14 for detecting wrong CP

Time between wrong CP

6.15

voltage and valid data in status register

Voltage difference V V

6.16

for detecting wrong

EVZ

CP-OUT

6.17 Voltage at pin CP

6.18 Voltage at pin CP

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

CP off, supply of internal circuitry

Note: Threshold is in

EVZ

the range of 5V to 7V

–

Note: Threshold is in the range of 5V to 7V

= 5.5V to 40V,

V

EVZ

V

< V

K30

ICP+I

EVZ

CP_Out

(current consumption of V

and V

SAT

be added)

= 5.5V to 40V,

V

EVZ

< V

V

K30

ICP+I

EVZ

CP_Out

(current consumption of

and V

V

SAT

be added)

= –100 µA

CORE

= –100 µA

CORE

= 5.5V to 40V, V

K30

> 3V, V

K15

= 3.7V to 5.47V

VINT

are within functional range limits, Tj = –40°C to 150°C

have to

CP I

CP-OUT t

CP-OUT I

CP-OUT

CP V

CP t

CP-OUT V

CP V

CP

d

Diff

d

Diff

CP

050µAA

050µsA

–0.8 –4.2 mA A

050µsA

V

+ 7 V

EVZ

V

+ 7 V

K30

5VA

+ 11 V A

EVZ

+ 11 V A

K30

4929B–AUTO–01/07

21

8. GKEY Function

The GKEY function is used to enable or disable the ECU via a powerless signal. If the voltage at pin K15 is larger than 3V to 4.15V, the charge pump and the EVZ regulator (for correct EVZ function, the K30 pin has to be connected to the battery) will start operating. If the K15 pin is open, an internal pull-down resistor of approximately 220 kΩ discharges the pin. A logical con- nection between the voltage at the K15 pin, a serial-interface-driven latch command, and the K30 voltage determines the EVZ Enable signal. In order to achieve the Switch Function of the GKEY function, a transformer has to be used.

Table 8-1. Overview of the Start-up Conditions

Note: 1. Less than the value shown in number 7.3 of Table 8-2 on page 23

Figure 8-1. Application With Low-current Switch (GKEY Function Used)

Serial-interface-

driven Latch

V

K30

Low High High

1)

2)

V

K15

(Default: “0” = OFF) EVZ Regulator

x x Disabled

3)

High

xEnabled

x1Enabled

2. Greater than the value shown in number 7.3 of Table 8-2 on page 23

3. Greater than the value shown in number 7.1 of Table 8-2 on page 23

V

BATT

GKEY-

Logic

EVZ

K15

COMEVZO

K30

GEVZ

OCEVZ

GNDB

EVZ

FBEVZ

V

EVZ

22

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Figure 8-2. Application With High Current Switch (GKEY Function Not Used)

V

BATT

K15

GKEY-

Logic

EVZ

K30

GEVZ

OCEVZ

GNDB

EVZ

FBEVZ

COMEVZO

Necessary for operation:

= 3V to 40V, V

V

K15

= 3.85V to 40V

K30

Operating conditions of all other supply pins: V

, V

EVZ

SAT

PERI

and V

are within functional range limits, Tj = –40°C to 150°C

CORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

V

EVZ

Table 8-2. Electrical Characteristics – GKEY Function

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Voltage level at K15 to enable

7.1 the EVZ regulator

Hysteresis at K15 to disable the

7.2 EVZ regulator

Voltage level at K30 to enable

7.3 the EVZ regulator

Hysteresis at K30 to disable the

7.4 EVZ regulator

7.5 Pull-down resistor at K15 K15 R

7.6 Pull-down resistor at K30 K30 R

7.7 Current at K15

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

4929B–AUTO–01/07

increasing,

V

K15

V

> 5V

K30

V

increasing,

K30

> 4.15V

V

K15

0V ≤ V

K15

≤ 40V,

AMUX measurement EVZ active

K15 V

K30 V

K15 I

K15

K30

K15

K30

K15

34.15VA

40 175 mV A

3.85 5 V A

50 150 mV A

70 365 kΩ A

320 1700 kΩ A

01.1mAA

23

9. EVZ Step-up Regulator

A boost converter generates the supply voltage for energy reserve and firing capacitors in the system. Using a voltage divider at pin FBEVZ, this voltage can be adjusted between 15V and 40V. Thus, high-voltage charged capacitors will be used to supply the whole system during the stand-alone time (for example, broken K30 line after a crash). The step-up regulator has to start running as soon as a certain threshold voltage at the K15 pin is exceeded. The regulator has to stop running again if the voltage at the K15 pin falls below a voltage level (or voltage at pin K30 is missing, see Section 5.3 ”Start-up and Power-down Procedure” on page 14).

An inductor is PWM-switched by an external n-channel power FET with a fixed frequency of 100 kHz. A driver stage for the external FET is integrated into the ATA6264. The current limitation of the external FET is implemented by using an external resistor in series between the source connection of the external FET and GND, sensing the voltage drop at this resistor via the pins OCEVZ and GNDA.

The reference section provides a reference voltage of 1.24V for the regulation loop. An error amplifier compares the reference voltage with the feedback signal, which is provided either from two different serial-interface-programmable internal dividers (VEVZ1 = 22V, VEVZ2 = 31.5V) or an external voltage divider network (VEVZExt). These dividers determine the output voltage EVZ.

Figure 9-1. EVZ Regulator With External Divider

K30

Bandgap

reference

Sawtooth oscillator

+

-

Error

amp.

SPI

-

SPI

PWM

comp.

SPI

Max. duty-cycle

Low battery

Logic and

driver

EVZ

overvoltage

Overcurrent

GEVZ

OCEVZ

GNDA

EVZ

FBEVZ

COMEVZO

L

R

VZ1

R

C

VZ2

+

24

ATA6264 [Preliminary]

4929B–AUTO–01/07

Figure 9-2. EVZ Regulator With Internal Divider

ATA6264 [Preliminary]

K30

Bandgap

reference

Sawtooth oscillator

+

-

Error amp.

SPI

-

SPI

PWM comp.

SPI

Max. duty-cycle

Low battery

Logic and

driver

EVZ

overvoltage

Overcurrent

GEVZ

OCEVZ

GNDA

EVZ

FBEVZ

COMEVZO

L

C

+

A draft formula for calculating the EVZ voltage, which is programmed by the external voltage divider network at pin FBEVZ, is:

R

+

VZ1RVZ2

V

EVZ

V

REF

--------------------------------

×=

R

VZ2

The pins EVZ and FBEVZ have to be shorted in applications without an external divider in order to ensure a safe operation of the ATA6264 in the case of an EVZ-pin fault. If the voltage at pin FBEVZ is larger than the voltage at pin EVZ, the ATA6264 switches the feedback path automatically to pin FBEVZ. The remaining voltage at FBEVZ causes the regulator to switch off.

The output of the error amplifier is compared with a periodic linear ramp of a saw-tooth generator by the PWM comparator. A logic signal with variable pulse width is generated, which controls the PWM frequency of the external FET. A maximum duty cycle is determined by the duration of the falling ramp of the saw-tooth oscillator. The saw-tooth generator is controlled by the internal 100-kHz oscillator.

4929B–AUTO–01/07

25

Figure 9-3. Functional Principle of the EVZ Regulator

Sawtooth

Error amp. output = f (V

on

PWM

output

off

EVZ

)

t

The output transistor conduction is suppressed immediately if the current through the power FET exceeds a certain level, determined by the voltage drop across an external resistor in the range of 0.2Ω. The ATA6264 itself will see a voltage at the OCEVZ pin. If this voltage exceeds typically 0.5V, the output transistor conduction has to be suppressed.

The external FET also has to be switched off if a low battery voltage at K30 or overvoltage on pin EVZ is detected. Multiple output pulses at pin GEVZ during one oscillator period are suppressed by internal logic.

In the default state - for example, before the minimum input voltage for starting the regulator has been reached - the external transistor is switched off.

During startup, the voltage on pin EVZ is too low and the PWM comparator requires a duty cycle of more than 90%. Due to an increasing inductance current, after several periods the overcurrent sensor becomes active and reduces the maximum duty cycle to improve magnetic energy transfer.

Figure 9-4. Output Current During Start-up

Output current

Current limit

t

A capacitance of 10 mF or more may be applied at pin EVZ. The equivalent series resistance (ESR) should have a value of less than 0.5Ω.

After power-on, the default state of the internal dividers should always be the low EVZ voltage divider.

The voltage at pin GNDA is compared with the voltage at pin GNDD, and if GNDA is not connected, bit b6 of the APACE status register is set. Pin GNDB is also compared with pin GNDD. Pin GNDB not being connected will also result in bit b6 being set, and, additionally, in the EVZ regulator being switched off.

26

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Necessary for operation: V

= 3V to 40V, V

K15

Operating conditions of all other supply pins: V

, V

PERI

and V

SAT

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 9-1. Electrical Characteristics – EVZ Step-up Regulator

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

V

≥ 8V or V

8.1 Switching frequency

8.2 Switching frequency

Voltage level at K15 to start the

8.3 EVZ regulator

Hysteresis at K15 to stop the

8.4 EVZ regulator

Voltage level at K30 to start the

8.5 EVZ regulator

Hysteresis at K30 to stop the

8.6 EVZ regulator

Voltage at pin GEVZ to switch

8.7 through the external driver

Voltage at pin GEVZ to switch

8.8 through the external driver

Driving current at pin GEVZ to

8.9

switch through the external driver

Gate charge delivered to the

8.10 external FET

Gate charge delivered to the

8.11 external FET

8.12 Pull-down resistor at pin GEVZ GEVZ R

of dynamic sinking

R

8.13

8.15

Dson

transistor at GEVZ Voltage between pins OCEVZ

and GND to detect overcurrent

8.16 Maximum switch duty cycle

8.17 Maximum switch duty cycle

8.18 Minimum switch duty cycle GEVZ D Overvoltage at pin EVZ to switch

8.19 off the regulator

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

K30

(after startup) 4V < V

4V < V (after startup)

See number 7.1 of

Table 8-2 on page 23

See number 7.2 of

Table 8-2 on page 23

See number 7.3 of

Table 8-2 on page 23

See number 7.4 of

Table 8-2 on page 23

≥ 3.85V to 5V

V

K30

(ON threshold)

≥ 7V GEVZ V

V

K30

V

GEVZ

V

GEVZ

V

GEVZ

≥ 8V or V

V

K30

(after startup) V

EVZ

4V < V 4V < V (after startup)

V

EVZExt

(via external divider)

= 5V to 40V, C

K30

are within functional range limits, Tj = –40°C to 150°C

CORE

≥ 8V

EVZ

< 8V or

K30

< 8V

EVZ

≤ 5V GEVZ I

= 5V GEVZ Q

= 10V GEVZ Q

≥ 8V

EVZ

= 200 pF to 2 nF, V

GEVZ

GEVZ f

GEVZ V

GEVZ R

OCEVZ V

GEVZ D

GEVZ

OCEVZ

GEVZ

–5% 100 +5% kHz A

–10% 100 +10% kHz A

V

K30

0.5V

610VA

–600 –80 mA A

10 nC D

20 nC D

20 50 kΩ A

0.475 0.525 V A

87.5 90 92.5 % A

≥ 8V

< 8V or

K30

< 8V

EVZ

programmed

GEVZ D

VEVZ V

GEVZ

EVZ

75 90 92.5 % A

40.5 46.2 V A

= 3.7V to 5.47V

INT

–

V

K30

VA

28 Ω A

0%A

A

4929B–AUTO–01/07

27

Table 9-1. Electrical Characteristics (Continued)– EVZ Step-up Regulator

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Overvoltage at pin EVZ to switch

8.19a off the regulator

Overvoltage at pin EVZ to switch

8.19b off the regulator

8.20 Overvoltage switch-off time

8.21 Overcurrent switch-off time

Switch-on delay time for the

8.22 boost converter output stage

Switch-on rise time for the boost

8.23 converter output stage

Switch-off delay time for the

8.24 boost converter output stage

Switch-off fall time for the boost

8.25 converter output stage

8.26 Leakage current at pin OCEVZ OCEVZ I

8.27 Leakage current at pin FBEVZ FBEVZ I

8.28 Switch-on threshold via FBEVZ

8.29 Switch-on threshold via FBEVZ

8.30 V

8.31

8.31a

8.31b

voltage #1 set by SPI

EVZ

V

voltage #2

EVZ

set by SPI

Temperature shutdown activation

Hysteresis for reactivation of GEVZ

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

V

programmed VEVZ V

EVZ1

programmed VEVZ V

V

EVZ2

Time between reaching overvoltage and reaching 90% of the value at numbers 8.7

GEVZ t

and 8.8 of Table 9-1 on

page 27

Time between reaching overcurrent and reaching 90% of the value at numbers 8.7

GEVZ t

and 8.8 of Table 9-1 on

page 27

GEVZ t

Time between 0.5V and

4.5V at GEVZ, =2nF

C

GEVZ

GEVZ t

Time between 4.5V and

0.5V at GEVZ, =2nF

C

GEVZ

Band-gap tolerance included

V

programmed,

EVZ1

Band-gap tolerance

GEVZ t

FBEVZ V

EVZ V

included

programmed,

V

EVZ2

Band-gap tolerance

EVZ V

included

EVZ

offov

offoc

don

ron

doff

foff

OCEVZ

FBEVZ

EVZ1

EVZ2

T

off

T

hys

25 28.5 V A

35 39.5 V A

200 ns D

500 ns A

50 250 ns A

10 200 ns A

50 150 ns A

10 100 ns A

–10 +10 µA A –10 +10 µA A

1.20 1.24 V A

1.24 1.28 V A

20 23 V A

28.6 33 V A

155 185 °C B

525KB

28

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 9-1. Electrical Characteristics (Continued)– EVZ Step-up Regulator

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Error Amplifier

Output current at pin COMEVZO

8.32 sinking to low

Output current at pin COMEVZO

8.33 driving to high

8.34 Input offset voltage –10 +10 mV D

8.35 DC open-loop gain 70 dB D

8.36 Unity-gain bandwidth 2 MHz D Output voltage low on pin

8.37 COMEVZO

Output voltage high on pin

8.38 COMEVZO

I

COMEVZO

I

COMEVZO

= 100 µA COMEVZO V

= –100 µA COMEVZO V

GNDA/GNDB Disconnect

8.40 GNDA lost detection V

GNDA

– V

GNDD

8.41 Delay for GNDA lost detection GNDA td 10 50 µs A

8.42 GNDB lost detection V

GNDB

– V

GNDD

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

COMEVZO I

GNDA V

GNDB V

COMEVZO

GNDA

GNDB

0.4 3 mA A

–1000 –150 µA A

00.2VA

VINT –

0.3V

VINT V A

0.2 0.4 V A

4929B–AUTO–01/07

29

10. VSAT Power Supply

A stabilized VSAT supply is realized by a buck converter. An external inductance is PWM-switched with a frequency of 200 kHz via an internal high-side DMOS power transistor. The VSAT power supply is connected to the boost converter output (EVZ), and uses the stored energy of the boost converter capacitor if the voltage at K30 is missing. The regulator uses both current and voltage feedback. The basis for the regulation loop is a temperature-compensated band-gap reference voltage, which is compared with the internally divided output voltage VSAT. The error amplifier output is applied to the inverting input of a comparator, the current feedback is connected with the positive input. The PWM flip-flop (which is set every 5 µs by the oscillator) is reset if the current feedback reaches the error amplifier level. In order to adjust the compensation of the regulation loop and therefore improve the behavior in case of load changes in continuous-mode operation, pin COMSATO has to be connected to COMSATI via a compensation network. Because of the fact that current-mode-controlled converters exhibit sub-harmonic oscillations when operating at duty cycles higher than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. If the regulator input voltage at pin EVZ is too low, the regulator switches to a duty cycle of 100% (Permanent-on mode).

The VSAT voltage can be programmed via the serial interface to one of three different voltage values during initial programming.

Figure 10-1. Functional Principle of the VSAT Regulator

CP

VSAT

COMSATI

SPI

OTP

COMSATO

EVZ

VSAT

SVSAT

+

Bandgap reference

Slope

compensation

Current

measurement

and leading edge

blanking

+

-

Error amp.

-

Comp.

S

R

OSC

Overcurrent

Logic and

Q

driver

Overvoltage

The duration of the output transistor conduction depends on the VSAT level and current feedback. Conduction is suppressed immediately if the current through the output transistor exceeds 850 mA typically. A logic circuit disables, in the case of short spikes, multiple-pulse operation during one oscillating period. If pin VSAT is open (VSAT loss), an internal current source connected to a higher voltage than VSAT acts as pull-up for this pin, to prevent the VSAT voltage from rising up to EVZ. In order to ensure the gate voltage for the output transistor, the driver stage is supplied by the charge pump (pin CP).

30

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Necessary for operation: V

= 5.5V to 40V, VCP > V

EVZ

Operating conditions of all other supply pins: V

, V

K30

PERI

and V

are within functional range limits, Tj = –40°C to +150°C

CORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 10-1. Electrical Characteristics – VSAT Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

V

voltage for the buck

EVZ

9.1 converter to start running

V

voltage for the buck

EVZ

9.2 converter to stop

Regulator switch-on time via pin

9.3 EVZ

Regulator switch-off time via pin

9.4 EVZ

9.5 Regulator switching frequency V

9.5a Regulator switching frequency 5.5V > V

9.6 Output current limit SVSAT I

9.7 R

9.8

of output transistor SVSAT R

Dson

Output voltage #1 only at

=3.3V

V

PERI

9.9 Output voltage #2

9.10 Output voltage #3

9.11 Output transistor switch-on time

9.12 Output transistor switch-on time

Overvoltage switching off the

9.13 regulator

9.14 Overvoltage switch-on time

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation; sub-harmonics must be prevented

2. The value of the minimum load current must be higher than the internal pull-up current at pin VSAT to ensure proper function of the regulator

EVZ V

≥ 8V SVSAT f

EVZ

≥ 8V SVSAT f

EVZ

Band-gap tolerance included

V

programmed,

VSAT2

Band-gap tolerance included

V

programmed,

VSAT3

Band-gap tolerance included

Time between reaching

0.1 × (V

EVZmax

– V

and

0.9 × (V

EVZmax

– V

Time between reaching

0.9 × (V

EVZmax

– V

and

0.1 × (V

EVZmax

– V

Time between reaching overvoltage and reaching 90% of V

SVSAT

maximum

under on condition

+ 7V, V

EVZ

SVSATmin

INT

EVZ V

SVSAT t

VSAT V

)

VSAT V

SVSAT t

= 3.7V to 5.45V

EVZ

SVSAT

VSAT1

VSAT2

VSAT3

VSAT

SVSAToff

7.5 9 V A

5.5 6.2 V A

020µsA

05µsA

–5% 200 +5% kHz A

–10% 200 +10% kHz A

0.8 1 A A

1 Ω A

–4% 7.8 +4% V A

–4% 9.1 +4% V A

–4% 10.4 +4% V A

150 ns A

1.1 ×

V

SATX

VA

00.4µsA

4929B–AUTO–01/07

31

Table 10-1. Electrical Characteristics (Continued)– VSAT Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Time between reaching

9.15 Overcurrent switch-on time

9.16 Leakage current at pin SVSAT Output transistor off SVSAT I

Error Amplifier

Maximum output current at pin

9.17 COMSATO sinking to low

Maximum output current at pin

9.18 COMSATO sourcing to high

Input impedance at pin

9.19 COMSATI

9.20 Input offset voltage –10 +10 mV D

9.21 DC open-loop gain 70 dB D

9.22 Unity-gain bandwidth 2 MHz D

9.23 Output voltage low I

9.24 Output voltage high I

9.25 Leading-edge blanking time t Slope of artificial ramp for slope

9.26 compensation

9.27 VSAT loss detection threshold

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation; sub-harmonics must be prevented

2. The value of the minimum load current must be higher than the internal pull-up current at pin VSAT to ensure proper function of the regulator

overcurrent and reaching 90% of V

SVSAT

maximum

under on condition

COMSATO

(2)

= 165 µA COMSATO V

= –85 µA COMSATO V

SVSAT t

COMSATO I

COMSATI R

SVSAToff

SVSAT

COMSATO

COMSATI

COMSATO

blank

V

dV/dt 150

I

Load

00.5µsA

–10 +10 µA A

200 3000 µA A

–165 –85 µA A

923kΩ A

00.3VA –

VINT

0.6V

V

VINT

VA

150 200 ns D

(1)

240

(1)

mV/µs D

01.5mAD

32

ATA6264 [Preliminary]

4929B–AUTO–01/07

11. VPERI Power Supply

With the V voltage. This voltage is intended to be used for sensitive components, for example, sensors or reference inputs of A/D converters from microcontrollers. For this reason, a linear regulator is implemented to guarantee high ripple rejection and a precise voltage. The regulator output is short-circuit protected by an overcurrent protection. If pin VPERI is disconnected, the regulator is switched off and RESQ/RESQ2 are set to low.

ATA6264 [Preliminary]

regulator a stabilized and ripple-free voltage is generated out of the VSAT supply

PERI

Figure 11-1. Functional Principle of the V

V

Peripheral

Linear regulator

Peripheral

VSAT

SVPERI

VPERI

Regulator

V

SAT

V

Peripheral

If a higher current capability of the regulator is requested or if the power dissipation of the linear regulator is too high, an external transistor can boost the regulator.

Figure 11-2. Functional Principle of the VPERI Regulator With External Boost Transistor

V

SAT

V

Peripheral

V

Peripheral

Linear regulator

VSAT

SVPERI

VPERI

4929B–AUTO–01/07

The VPERI voltage can be programmed via the serial interface to one of two different voltage values during initial programming.

33

Necessary for operation: V

> 7.5V, V

SAT

= 3.7V to 5.47V, V

INT

CORE

< V

PERI

+ 0.3V

Operating conditions of all other supply pins: V

, V

K30

EVZ

and V

are within functional range limits, Tj = –40°C to 150°C

CORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 11-1. Electrical Characteristics – VPERI Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Voltage level at VSAT to enable

10.1 VPERI regulator

Hysteresis at VSAT to disable

10.2 VPERI regulator

V

programmed,

10.3 Output voltage #1

VPERI1

band-gap tolerance included

programmed,

V

VPERI2

10.4 Output voltage #2

band-gap tolerance included

10.5 Output current V

= 7.5V to 12.5V VPERI I

VSAT

10.6 Short-circuit current VPERI I

= 8V to 12.5V

V

VSAT

I

= –1 mA to –100 mA

10.7 Line regulation

PERI

is constant during

(I

PERI

measurement) V

= 8V to 12.5V (V

10.8 Load regulation

10.10 Supply voltage rejection

SAT

is constant during measurement)

= –1 mA to –100 mA

I

PERI

= –100 mA,

I

PERI

f = 100 kHz – 20 MHz,

= 47 µF + 100 nF

C

PERI

VSAT

(ceramic)

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

VSAT V

VPERI V

VSAT

VPERI

6.77 7.2 V A

0.2 0.5 V A

–3.6% 5 +4% V A

–4% 3.3 +3% V A

–100 mA A –200 –110 mA A

–10 +10 mV A

40 dB D

34

ATA6264 [Preliminary]

4929B–AUTO–01/07

12. VCORE Power Supply

The voltage of the VCORE regulator is generated out of the K30 voltage using a step-down regulator as long as the K30 voltage is available. During times when K30 is not present (power-down or stand-alone time), the VCORE regulator is supplied out of VEVZ. Depending on the initial programming, the supply switch signal is derived from the CORESWAP comparator or the EVZEN comparator. The VCORE voltage can be programmed via the serial interface to 3 different voltage values during initial programming. In the case of short spikes, a logic circuit disables multiple-pulse operation during one oscillating period. The regulator uses both current and voltage feedback. In the following cases, the output transistor of the regulator is switched off at once and may be switched on again with the beginning of the next clock period:

1. If the current through the transistor exceeds the output current limit value, the transistor is switched off immediately.

2. If overvoltage is detected at the pin VCORE, the transistor is switched off immediately.

3. If the feedback voltage at the pin VCORE is missing (disconnected pin), the regulator is switched off.

Figure 12-1. Functional Principle of the VCORE Regulator

Control-

signal

K30/EVZ

ATA6264 [Preliminary]

VCORE

COMCOI

SPI

OTP

COMCOO

K30

VCORE

SVCORE

+

EVZ

CP

Bandgap reference

Slope

compensation

OSC

S

+

-

Error amp.

+

-

Comp.

compensation

Q

R

Slope

Current

measurement

and leading edge

blanking

Overcurrent

Logic and

driver

Overvoltage

Current

measurement

and leading edge

blanking

In order to trim the compensation of the regulation loop and to improve the behavior at load changes, pin COMCOO has to be connected to COMCOI via a compensation network. Because of the fact that current-mode-controlled converters exhibit sub-harmonic oscillations when operating at duty cycles larger than 50%, a slope compensation (which adds an artificial ramp to the comparator) is implemented. If the regulator input voltage at pin EVZ or pin K30 is too low, the regulator switches to a duty cycle of 100% (Permanent-on mode). Backward feeding of EVZ and K30 is avoided. In order to ensure the gate voltage for the output transistors of the regulator, the driver stages are supplied by the charge pump (pin CP).

4929B–AUTO–01/07

35

Necessary for operation: V

= 5.5V to 40V or V

EVZ

V

PERI>VCORE

– 0.3V, V

= 5.5V to 40V, VCP > V

K30

= 3.7V to 5.47V

INT

+ 7V or VCP > V

EVZ

K30

+ 7V,

Operating conditions of all other supply pins: V

is within functional range limits, Tj = –40°C to 150°C

SAT

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 12-1. Electrical Characteristics – VCORE Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

V

voltage for the VCORE

11.1

11.1a

EVZ

regulator to start running V

voltage for the

VPERI

VCORE regulator to start running

V

voltage for the VCORE

11.2

EVZ

regulator to stop running Hysteresis at VPERI for the

11.2a

VCORE regulator to stop running

11.3 Switch-on time via pin EVZ SVCORE t

11.4 Switch-off time via pin EVZ SVCORE t Regulator switching

11.5 frequency

11.6 Output current limit SVCORE I

11.7 R

of output transistor SVCORE R

Dson

11.8 Output voltage #1

11.9 Output voltage #2

11.10 Output voltage #3

11.11

Output transistor switch-on time

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented.

2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper

function of the regulator.

Initial programming: V

VCORE

= 5V or 2.5V

Initial programming:

VCORE

= 1.88V

V

Initial programming: V

VCORE

= 5V or 2.5V

Initial programming:

VCORE

= 1.88V

V

See numbers 8.1 and 8.2 of Table 9-1 on page 27

V

VCORE1

programmed, band-gap tolerance included

VCORE2

programmed,

V band-gap tolerance included

V

VCORE3

programmed, band-gap tolerance included

Time between reaching

0.1 × (V

K30max

– V

VCOREmin

and

0.9 × (V

K30max

– V

VCOREmin

or

0.1 × (V

EVZmax

– V

VCOREmin

and

0.9 × (V

EVZmax

– V

VCOREmin

EVZ V

VPERI V

EVZ V

VPERI V

SVCORE f

VCORE V

)

SVORE t

)

EVZ

VPERI

EVZ

HYS

SVCORE

VCORE1

VCORE2

VCORE3

SVCOREon

7.5 9 V A

1.25 1.7 V A

5.5 6.2 V A

50 150 mV A

020µsA 010µsA

0.7 0.9 A A

1.2 Ω A

–4% 5.0 +4% V A

–4% 2.5 +4% V A

–4% 1.88 +4% V A

150 ns A

A

36

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 12-1. Electrical Characteristics (Continued)– VCORE Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Time between reaching

0.1 × (V and

11.12

Output transistor switch-off time

0.9 × (V or

0.1 × (V and

0.9 × (V

11.13

11.13a

11.13b

Overvoltage at pin VCORE for switching off the regulator and setting pin RESQ to low (VCORE is set to 5V)

Overvoltage at pin VCORE for switching off the regulator and setting pin RESQ to low (VCORE is set to 2.5V)

Overvoltage at pin VCORE for switching off the regulator and setting pin RESQ to low (VCORE is set to 1.8V)

See numbers 14.6 and

14.6a of Table 15-2 on

page 45

See numbers 14.7 and

14.7a of Table 15-2 on

page 45

See numbers 14.8 and

14.8a of Table 15-2 on

page 45

Time between reaching

11.14 Overvoltage switch-off time

overvoltage and reaching 90% of V under on condition

Time between reaching

11.15 Overcurrent switch-off time

overcurrent and reaching 90% of V under on condition

11.16

Leakage current at pin SVCORE

Output transistor off SVCORE I

Error Amplifier

11.17

Maximum output current at pin COMCOO sinking to low

Maximum output current at

11.18

pin COMCOO sourcing to high

11.19

Input impedance at pin COMCOI

V V

CORE CORE

= 1.88V = 2.5V/5V

11.20 Input offset voltage –10 10 mV D

11.21 DC open loop gain 70 dB D

11.22 Unity-gain bandwidth 2 MHz D

11.23

11.24

Output voltage low at pin COMCOO

Output voltage high at pin COMCOO

I

COMCOO

I

COMCOO

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented.

2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator.

K30max

EVZmax

SCORE

– V

VCOREmin

– V

VCOREmin

– V

VCOREmin

– V

VCOREmin

maximum

)

SVCORE t

)

SVORE t

SVCORE t

COMCOO I

COMCOI R

= 165 µA COMSATO V

= –85 µA COMSATO V

SVCOREoff

SVCORE

COMCOO

COMCOI

COMSATO

150 ns A

00.4µsA

00.5µsA

–10 10 µA A

200 3000 µA A

–165 –85 µA A

7.5 13

18 27

kΩ kΩ

00.3VA

VINT –

0.6

VINT V A

A

4929B–AUTO–01/07

37

Table 12-1. Electrical Characteristics (Continued)– VCORE Power Supply

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

11.25 Leading-edge blanking time t

11.26

11.27

Slope of artificial ramp for slope compensation

Voltage level at K30 to switch VCORE supply from EVZ to K30 (V

= 1.8V or 2.5V

VCORE

V

increasing

K30

See number 7.3 of Table

8-2 on page 23

blank

dV/dt 80

programmed) Hysteresis at K30 to switch

V

decreasing

K30

See number 7.4 of Table

8-2 on page 23

11.28

VCORE supply from K30 to EVZ (V

= 1.8V or 2.5V

VCORE

programmed) Voltage level at K30 to switch

11.29

VCORE supply from EVZ to

VCORE

= 5V

K30 (V

increasing K30 V

V

K30

programmed) Hysteresis at K30 to switch

11.30

VCORE supply from K30 to

VCORE

= 5V

EVZ (V

decreasing K30 V

V

K30

programmed) Time to switch VCORE

11.31

supply from EVZ to K30 or

SVCORE t

switch

K30 to EVZ

11.32

VCORE loss-detection threshold

(2)

VCORE I

Load

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. Depending on implementation of slope compensation, sub-harmonics have to be prevented.

2. The value of the minimum load current must be higher than the internal pull-up current at pin VCORE to ensure proper function of the regulator.

150 200 ns D

(1)

150

(1)

mV/µs D

6.1 8.1 V A

0.5 1 V A

07.6µsD

01mAD

A

38

ATA6264 [Preliminary]

4929B–AUTO–01/07

13. USP Comparator for General Purpose

The USP comparator is used for general purposes, for example, low battery detection. An external resistive voltage divider provides the input signal for pin USP. A missing USP connection or V

< 2.44V sets the status register bit b7 to low. During normal operation (V

USP

status register bit b7 stays high.

Figure 13-1. Functional Principle of the USP Comparator

USP

2.44V

GNDA

to AMUX

+

-

ATA6264 [Preliminary]

> 2.44V) the

USP

Status register

Necessary for operation: V

= 5.5V to 40V, V

EVZ

> reset threshold, V

PERI

> reset threshold, V

CORE

= 3.7V to 5.47V

INT

Operating conditions of all other supply pins: V

SAT

and V

are within functional range limits, Tj = –40°C to 150°C

K30

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 13-1. Electrical Characteristics – USP Comparator for General Purpose

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

12.1 Input current at pin USP V

12.2 Input current at pin USP V

= 2.44V USP I

USP

= 0 to 40V USP I

USP

Trigger voltage for status

12.3 Threshold voltage at pin USP

12.4 De-glitching time t

register bit 7= high with increasing V

USP

USP V

USP

deglitch

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

–2.5 +2.5 µA A –2.5 +2.5 µA A

2.44 ±5% V A

20 60 µs D

4929B–AUTO–01/07

39

14. Reference Voltage and Reference Current Generation

The pin IREF is an output derived directly from the chip’s internal reference voltage. This reference source is a band gap. All internally used precise voltages are derived from this band-gap voltage. At pin IREF a reference resistor of 12.4 kΩ has to be applied, providing a reference cur- rent. All internally used precise currents are derived from this current. In case of a missing resistor at IREF, the regulators will stop. The power-sequencing block still operates as specified.

A defect of the band-gap reference source can be detected by a microcontroller by comparing the voltage at IREF with the voltage at pin VINT (Internal 5V supply), because V from a different band gap.

Table 14-1. Truth Table for VINT

K30GOOD

State

(V

>4.2V to 5V)

K30

1Low Low 0 OFF 2High Low 0 OFF 3 Low High 0 OFF 4 High High V

5Low LowV

6High LowV

7 Low High V

8 High High V

K15GOOD

(V

>3Vto4V) V

K15

EVZ

< V

K30

> 5.5V

> V

K30

ON (Supply: EVZ) – only valid if VINT was

is derived

VINT

V

VINT

ON (Supply: K30)

already enabled via state #4

ON (Supply: K30)

Necessary for operation: V

= 5.5V to 40V or V

EVZ

= 3.85V to 40V

K30

Operating conditions of all other supply pins: V

, V

SAT

PERI

and V

are within functional range limits, Tj = –40°C to +150°C

CORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 14-2. Electrical Characteristics – Reference Voltage and Reference Current Generation

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

13.1 Reference voltage V

IREF

13.2 Reference current IREF IREF I > V

V

K30

13.3a Voltage at VINT

13.3b Voltage at VINT V

13.3c Voltage at VINT V

13.3d Voltage at VINT

V

V V

EVZ

= VK30GOOD to 5V

K30

> V

, V

K30

> V

K30

EVZ

= 0V, V

K30

> V

EVZ

K30

= 5V to 6V VINT V

K30

, V

= 6V IREF V

K30

> 6V

EVZ

IREF V

VINT V

IREF V

IREF

VINT

IREF

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

1.24 ± 4% V A 100 ± 4% µA A

3.35 5.47 V A

3.7 5.47 V A

4.2 5.47 V A

40

ATA6264 [Preliminary]

4929B–AUTO–01/07

15. Reset Function (Pin RESQ and Pin RESQ2)

Pins RESQ and RESQ2 are low-active digital outputs of the ATA6264, which provide a digital “low” signal in the case of a missing or incorrect watchdog transmission or in the case of improper VEVZ, VPERI or VCORE voltage.

The voltage at pin RESQ depends on the proper voltages at pins EVZ, VCORE, and VPERI. The RESQ signal will be set to high after a 16-ms delay as soon as the VCORE reset threshold and the VPERI reset threshold and the EVZ reset threshold (signal EVZGOOD = high) have been reached. If the watchdog circuitry does not detect a valid watchdog trigger, the RESQ signal is set to low again. If the watchdog was triggered successfully, RESQ stays high and RESQ2 is also set to high.

In the case that an overvoltage at VCORE or VPERI is detected, the voltages at pins RESQ and RESQ2 are set to low.

Figure 15-1. Functional Principle of RESQ, RESQ2

V

EVZ

is above

EVZ

reset

threshold

ATA6264 [Preliminary]

V

CORE

V

PERI

WD-logic

V

is above

CORE

reset

threshold and

below overvoltage

V

is above

PERI

reset

threshold and

below overvoltage

Watchdog is

triggered

RESQ

RESQ2

4929B–AUTO–01/07

41

Figure 15-2. Functional Principle of RESQ, RESQ2

V

EVZGOOD

"V

-OK"

PERI

"V

-OK"

CORE

RESQ

chip

internal

trigger

window

SPI

communication

16 ms

4 ms4 ms

16 ms WD cyc* WD cyc*

t

42

RESQ2

* Watchdog cycle, see pages 48 and 49

ATA6264 [Preliminary]

prescaler

re-configure

Trg Wdg CMD

Re-configure prescaler while

1 st and 2nd trigger watchdog

Trg Wdg CMD

command

SPI CMD

any different

Trg Wdg CMD

t

4929B–AUTO–01/07

ATA6264 [Preliminary]

The RESQ2 signal results from a logical AND of the Reset signal and an OK signal from the watchdog circuitry, so RESQ2 will go high after the watchdog triggers correctly.

RESQ and RESQ2 have to be set to low if V

VPERI

or V

are below the specified threshold.

EVZ

VCORE is designed as an essential supply for a microcontroller core, and therefore special supervisor circuits for this regulator will affect the signals at pin RESQ and RESQ2 such that both outputs are set to low if the voltage at pin VCORE spends more than 4 regulator cycles in an overvoltage or undervoltage condition at their corresponding switching marks. In addition, a detected overcurrent signal during switch-on gives information about regulator problems, and results in a low-level signal for RESQ/RESQ2.

Figure 15-3. Functional Principle of the Supervisor Circuit for VCORE Monitoring (Values are

Valid for V

EVZ

HIGH: 7.5V to 9V

LOW: 5.5V to 6V

VPERI

3.0V to 3.16V

3.44V to 3.6V

VCORE

1.68V to 1.73V

= 1.88V and V

VCORE

+

-

+

-

+

VPERI

QD

CLK

Regulator ON

CLK

= 3.3V)

QD

CLK

QD

CLK

RESQ

4929B–AUTO–01/07

2.03V to 2.08V

+

-

ON OFF OFF

QD

CLK

Regulator OFF

CLK

QD

CLK

ONON

QD

CLK

Signal overcurrent VCORE at

regulator ON

VCORE

Voltage

If the watchdog is triggered incorrectly, RESQ and RESQ2 are set to low as well. Voltage spikes on EVZ smaller than or equal to 10 µs to 20 µs do not influence the RESQ or RESQ2 pins.

If the ATA6264 internal supply voltage (VINT) is below its proper value, RESQ and RESQ2 are also set to low.

For all voltages at VPERI below the reset threshold, pins RESQ and RESQ2 are switched to low. Both pins deliver a valid low until VPERI goes lower than 1V.

43

Table 15-1. Reset Truth Table

VPERI VCORE VEVZ WATCHDOG RESQ RESQ2

< 1V X X X

1V to V

> V

= OK X X X Low Low

VPERI

V

= Not OK X X Low Low

VCORE

V

VPERI

= OK

VCORE

= OK

EVZGOOD = high

= OK)

(V

EVZ

After startup

(no trigger has occurred)

Correctly triggered

(trigger occurred 1

st

time)

Undefined (low

via resistor)

High Low

High Low -> high

Undefined (low

via resistor)

Correctly triggered High High

Incorrectly triggered High -> low High -> low

X

EVZGOOD = low

= Not OK)

(V

EVZ

Figure 15-4. Application Example

V

EVZ

V

CORE

V

PERI

WD-logic

is above

EVZ

reset

"threshold"

V

is above

CORE

reset

"threshold" and

below overvoltage

V

is above

PERI

reset

"threshold" and

below overvoltage

Watchdog is

triggered

XLowLow

RESQ

RESQ2

Microcontroller

dual voltage

supply

(1.88V, 3.3V)

Safety system

monitoring

microcontroller

(3.3V)

Other

peri

(3.3V)

44

Necessary for operation:

= 5.5V to 40V, V

V

EVZ

= 1V to 5.5V, V

PERI

Operating conditions of all other supply pins: V

, V

K30

SAT

, and V

are within functional range limits, Tj = –40°C to 150°C

CORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

ATA6264 [Preliminary]

= 3.7V to 5.47V

INT

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 15-2. Electrical Characteristics – Reset Function (Pin RESQ and Pin RESQ2)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

I

14.1 RESQ and RESQ2 high level

14.2 RESQ and RESQ2 low level I

14.3 Reset threshold at pin VCORE V

RESQ, IRESQ2

–200 µA to 0 µA

RESQ, IRESQ2

VCORE

Voltage difference

14.3a

V

– reset threshold at

VCORE

V

VCORE

VCORE (see number 14.3)

14.4 Reset threshold at pin VCORE V

VCORE

Voltage difference

14.4a

– reset threshold at

V

VCORE

V

VCORE

VCORE (see number 14.4)

14.5 Reset threshold at pin VCORE V

VCORE

Voltage difference

14.5a

– reset threshold at

V

VCORE

V

VCORE

VCORE (see number 14.5) Overvoltage at pin V

14.6

switch off the regulator and set

CORE

to

V

VCORE

RESQ to low Voltage difference reset

to

V

VCORE

V

VCORE

14.6a

threshold at VCORE (see number 14.6) – V

Overvoltage at pin V

14.7

switch off the regulator and set

VCORE

CORE

RESQ to low Voltage difference reset

14.7a

threshold at VCORE (see number 14.7) – V

VCORE

V

VCORE

Overvoltage at pin VCORE to

14.8

switch off the regulator and set

V

VCORE

RESQ to low Voltage difference reset

14.8a

threshold at VCORE (see number 14.8) – V

VCORE

14.9 Reset threshold at pin VPERI V

14.10 Reset threshold at pin VPERI V Overvoltage at pin VPERI to

14.11 set RESQ to low

Overvoltage at pin VPERI to

14.12 set RESQ to low

Threshold for signal

14.13 EVZGOOD = OK

Threshold for signal

14.14 EVZGOOD = Not OK

V

VCORE

VPERI

V

VPERI

V

VPERI

V

EVZ

V

EVZ

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

=

= 0mAto2mA

RESQ

RESQ2

RESQ

RESQ2

V

is set to 5V VCORE V

is set to 5V VCORE dV

is set to 2.5V VCORE V

is set to 2.5V VCORE dV

is set to 1.88V VCORE V

is set to 1.88V VCORE dV

is set to 5V VCORE V

is set to 5V VCORE dV

is set to 2.5V VCORE V

is set to 2.5V VCORE dV

is set to 1.88V VCORE V

is set to 1.88V VCORE dV

is set to 5V VPERI V is set to 3.3V VPERI V

is set to 5V VPERI V

is set to 3.3V VPERI V

rising EVZ V

falling EVZ V

RESQ

RESQ2

RESQ

RESQ2

VCORE

VPERI

EVZ

V

VPERI

– 0.8

V

VPERI

VA

00.4VA

4.5 5.03 V A

0.17 0.7 V A

2.25 2.5 V A

0.1 0.35 V A

1.68 1.8852 V A

0.07 0.275 V A

4.97 5.5 V A

0.17 0.7 V A

2.5 2.8 V A

0.1 0.35 V A

1.8748 2.11 V A

0.07 0.275 V A

4.5 4.82 V A

2.94 3.16 V A

5.2 5.51 V A

3.4 3.63 V A

7.5 9 V A

5.5 6.2 V A

4929B–AUTO–01/07

45

Table 15-2. Electrical Characteristics (Continued)– Reset Function (Pin RESQ and Pin RESQ2)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Delay time for RESQ and RESQ2 to switch to low after

14.15 reaching the reset threshold of

V

EVZ

RESQ

RESQ2

RESQ is switched to low

14.16 Pull-down current at pin RESQ

Pull-down current at pin

14.17 RESQ2

Pull-down resistor at pin

14.18 RESQ, RESQ2

Output current high side

14.19 RESQ, RESQ2

Output current low side RESQ,

14.20 RESQ2

14.21 Rise time RESQ, RESQ2

14.22 Fall time RESQ, RESQ2

(V

= 0.4V),

RESQ

1V ≤ V

VPERI

<5.5V

RESQ2 is switched to low

= 0.4V),

(V

RESQ

1V ≤ V

VPERI

<5.5V

RESQ, RESQ2 are switched to high, V

RESQ

, V

RESQ2

= 0V

RESQ, RESQ2 are switched to high, V

RESQ

, V

RESQ2

= V

VPERI

30-pF external capacitive load

RESQ I

RESQ2 I

RESQ

RESQ2

RESQ

RESQ2

RESQ

RESQ2

RESQ

RESQ2

RESQ

RESQ2

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

t

RESQ

t

RESQ2

RESQ

RESQ2

R

RESQ

R

RESQ2

I

RESQ

I

RESQ2

I

RESQ

I

RESQ2

t

RESQ

t

RESQ2

t

RESQ

t

RESQ2

10 20 µs A

12mAA

0.5 1.5 MΩ D

–550 –250 µA A

410mAA

4.0 µs A

0.5 µs A

46

ATA6264 [Preliminary]

4929B–AUTO–01/07

16. Watchdog Function

To verify the proper function of the microcontroller, watchdog logic is included. As the ATA6264 is powered up, the RESQ2 signal stays low until the first valid watchdog trigger is detected.

Features:

• Watchdog trigger has to be done via the serial interface

• In case of a watchdog-trigger mismatch, the ATA6264 is set into its default state (latches, MISO status, etc.) and RESQ is set to low.

• Watchdog has to be triggered cyclically (prescaler for repetition time is set via serial interface command). Default: 16-ms repetition time

Figure 16-1. Watchdog Trigger Functional Principle

VCORE

5.0V

4.8V

ATA6264 [Preliminary]

t

RESQ

chip

internal

trigger

window

Serial

interface

communication

16 ms

4 ms4 ms

16 ms WD cyc* WD cyc*

prescaler

re-configure

Trg Wdg CMD

Re-configure prescaler during 1 st and 2nd trigger watchdog

Trg Wdg CMD

command

any different

SPI CMD

t

Trg Wdg CMD

t

4929B–AUTO–01/07

* Watchdog cycle, see pages 48 and 49

47

Requirements for successful trigger:

• Minimum one valid different serial interface command between two trigger watchdog commands is necessary. Exception: First trigger watchdog command need not be preceded by a different serial interface command.

• Cyclic repetition for the trigger watchdog command within ±25% tolerance is necessary.

Incorrect trigger causes RESQ active. The prescaler will be set to its default value with RESQ = low

Initial phase: Timing for the first trigger watchdog is fixed to 16 ms after RESQ changes from low to high (trigger window ±25% means ±4-ms trigger window for first trigger watchdog command). After the first watchdog trigger, the prescaler can be reconfigured within a specified time window (< 1 ms). Only one configuration command is allowed in this time window. For watchdog trigger handling, the Serial Interface Reconfigure command can be chosen as a different serial interface command. Any further configuration inside or outside this time window will cause an immediate reset via RESQ.

Figure 16-2. Reconfiguration Prescaler Functional Principle

RESQ

chip

internal

trigger

window

Serial

interface

communication

Succesful

reconfiguration

Trg Wdg CMD

prescaler

re-configure

inactive

No succesful

reconfiguration

1 ms1 ms

Trg Wdg CMD

prescaler

re-configure

active

t

48

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

The trigger watchdog cycle can be set to the following retrigger times:

•4 ms

•8 ms

• 16 ms (default)

•32 ms

•64 ms

•128 ms

Cyclic phase: Between two trigger commands a different SPI command must be seen by the SPI decoder

Figure 16-3. Watchdog Trigger Functional Principle (Successful Watchdog Trigger)

RESQ

inactive

chip

internal

trigger

window

Serial

interface

communication

t_retrigger

44 44

Trg Wdg CMD

SPI-CMD

Additional

Trg Wdg CMD

SPI-CMD

Additional

t_retrigger

Trg Wdg CMD

SPI-CMD

Additional

Trg Wdg CMD

t

4929B–AUTO–01/07

49

Figure 16-4. Watchdog Trigger Functional Principle (Unsuccessful Watchdog Trigger)

RESQ

inactive inactive

chip

internal

trigger

window

Serial

interface

communication

RESQ

chip

internal

trigger

window

t_retrigger

44

Missing

additional

Trg Wdg CMD

inactive inactive

44

command

serial interface

t_retrigger

Trg Wdg CMD

44

Trg Wdg CMD

t_retrigger

additional

command

serial interface

t_retrigger

activeactive

t

Trg Wdg CMD

t

activeactive

t

50

Serial

interface

communication

ATA6264 [Preliminary]

Trg Wdg CMD

additional

command

serial interface

Trg Wdg CMD

t

Trg Wdg CMD

t

4929B–AUTO–01/07

ATA6264 [Preliminary]

Configuration of watchdog trigger:

For the configuration of the watchdog prescaler, a special serial interface command is necessary.

MSByte LSByte

Description

Configure prescaler 0110000011110abc 60Fx

Note: a, b, and c to be set as defined in Table 16-1

Table 16-1. Watchdog Prescaler Command

Selection Bits

Retrigger Time (ms)abc

0 0 0 Set to default (16 ms) 0014 0108 01116 10032 10164 110128 1 1 1 Set to default (16 ms)

Hex Code7654321076543210

The status of the watchdog prescaler is indicated in the status register.

4929B–AUTO–01/07

51

Necessary for operation: V

> Reset threshold, V

PERI

> Reset threshold

CORE

Operating conditions of all other supply pins: V

, V

K30

EVZ

and V

are within functional range limits, Tj = –40°C to 150°C

VSAT

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 16-2. Electrical Characteristics – Watchdog Function

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

15.1 Oscillator frequency f

os

–5% 100 +5% kHz A

Power-up extension of RESQ

15.2 signal

RESQ t

RESQ

16 16 A

Start of first watchdog trigger

15.3

window after rising edge at

t12 12 A

RESQ

Maximum width of first

15.4 watchdog-trigger window

t8 8 A

Maximum time for prescaler

15.5

configuration after first

t1 1 A

watchdog-trigger command

15.6 Programmed watchdog cycle

Start of programmed watchdog

15.7 window

Max. programmed window

15.8 duration

Time for RESQ = low after

15.9 watchdog timeout

WD

(default 16 ms)

t

WD

75% ×

t

WD

50% ×

t

WD

(Missing watchdog trigger) RESQ t 16 16 A

t

75% ×

t

50% ×

t

as set by prescaler

t

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

WD

100

----------

f

os

100

----------

f

os

100

----------

f

os

100

----------

f

os

100

----------

f

os

A

52

ATA6264 [Preliminary]

4929B–AUTO–01/07

Figure 16-5. Watchdog Trigger

VCC

5.0V

4.75V

RESQ

ATA6264 [Preliminary]

t

chip

internal

trigger

window

Serial

interface

communication

15.2 ms

15.4 ms

15.3 ms 15.6 ms

15.5 ms

re-configure

Trg Wdg CMD

15.8 ms

15.7 ms

prescaler

Re-configure prescaler during 1 st and 2nd trigger watchdog

Trg Wdg CMD

command

any different

serial interface

command

15.9 ms

t

Trg Wdg CMD

t

4929B–AUTO–01/07

53

17. LIN/ISO 9141 Interfaces

The ATA6264 includes two complete ISO 9141 interfaces. Interface #1 is controlled via the pins RxD1 and TxD1, interface #2 is controlled via the pins RxD2 and TxD2. In order to support both ISO9141 and LIN bus requirements, interface #1 can be configured during initial programming. In applications where one or both ISO9141 interfaces are not needed, the output transistors of K1 and K2 may be used as simple low-side transistors, switched on or off by the serial interface. In this mode, a diagnosis of the pins K1 and K2 via the analog multiplexer is possible. The K1 and K2 outputs include an internal current limitation and overtemperature protection circuit.

Figure 17-1. Functional Principle of the LIN/ISO 9141 Interfaces

TXD

Serial

interface

Mode select

Analog

MUX

UZP µC Analog input

K30

K

GNDB

RXD

+

-

Necessary for operation: V

= 9V to 40V, V

EVZ

V

= 3.7V to 5.47V

VINT

= 5.5V to 40V, V

K30

> Reset threshold, V

VPERI

Operating conditions of all other supply pins: V

is within functional range limits, Tj = –40°C to +150°C

VSAT

Other pins: As defined in Section 4. ”Functional Range” on page 8.

0.5 × V

K30

> Reset threshold,

VCORE

54

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 17-1. Electrical Characteristics – LIN/ISO 9141 Interfaces

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

General (Valid for All Modes)

Pull-up current to VPERI at

16.1 pin TxD

16.2 K

16.3 K

16.4 K

16.5 K

16.6 K

16.7 K

16.8 K

16.9 K

x

input receiver low (x = 1, 2) K

x

input receiver high (x = 1, 2) K

x

input receiver threshold (x = 1, 2) K

x

input receiver hysteresis (x = 1, 2) K

x

output sink current

x

output voltage drop

x

output capacitance

x

output current limitation (x = 1, 2) K

x

16.10 Kx leakage current

16.11 RxD

16.12 RxD

16.13

16.14 RxD

16.15 RxD

16.16 RxD

16.17

16.18

16.19 TxD

voltage drop high side

x

voltage drop low side

x

RxDx high-side output current

low-side output current

x

output rise time

x

output fall time

x

TxDx input-voltage high-level threshold

input-voltage high-level

TxD

x

threshold

input-voltage low level

x

16.20 TxDx input-voltage hysteresis (x = 1, 2) TxD

16.21 TxD

16.22 K

16.22a

input capacitance (x = 1, 2) TxD

x

thermal shutdown (x = 1, 2) T

x

thermal-shutdown

K

x

hysteresis

(x = 1, 2) TxD

(x = 1, 2), K output voltage 1.5V

(x = 1, 2), I

= 0 mA to 40 mA

Kx

(x = 1, 2), capacitance between Kx and GNDB

(x = 1, 2), output driver deactivated

(x = 1, 2), with I

= 0 µA to –500 µA

RxDx

(x = 1, 2),

= 0 mA to 1mA

I

RxDx

(x = 1, 2), V

= 0V

RxDx

(x = 1, 2),

= V

V

RxDx

VPERI

(x = 1, 2), 30-pF external load

(V

= 5V),

PERI

(x = 1, 2) (V

= 3.3V),

PERI

(x = 1, 2) (V

= 3.3V),

PERI

(x = 1, 2)

K

RxD

TxD

x

(x=1, 2) DT

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

I

V

I

t

V

V C

TxDx

V

Kx

V

Kx

V

Kx

V

Kx

I

Kx

V

Kx

C

I

Kx

I

Kx

RxDx

TxDx

JKx

–35 –50 –65 µA A

K30

/

0.4 ×

V

K30

V

K30

0

0.6 ×

V

K30

V

2

0.07 ×

V

K30

0.2 ×

V

K30

35 mA A

1.7 V A

Kx

10 pF D

50 100 mA A

–10 +10 µA A

V

VPERI

– 0.8

V

VPERI

00.4VA

–1.1 –0.2 mA A

14mAA

1µsA

0.5 ×

V

VPERI

0.6 × V

PERI

V

VPERI

+ 0.3V

V

PERI

0.3V

0.2 ×

V

VPERI

100 550 mV A

5pF D

155 185 °C B

JKx

525KB

VA

+

VA

4929B–AUTO–01/07

55

Table 17-1. Electrical Characteristics (Continued)– LIN/ISO 9141 Interfaces

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

ISO 9141 Mode

16.23 Maximum baud rate K

x

f

Kx

(x = 1, 2),

x

K30

K

x

t

PDtL

16.24

Propagation delay TxDx= low to Kx=low

measured from TxD H to L to K R

= 510Ω to K30,

Kx

C

= 470 pF to GNDB

Kx

= 0.9 × V

x

(x = 1, 2),

x

K30

K

x

t

PDtH

16.25

Propagation delay

=high to Kx=high

TxD

x

measured from TxD L to H to Kx = 0.1 × V RKx= 510Ω to K30,

= 470 pF to GNDB

C

Kx

(x = 1, 2), measured from

16.26 K

rise time

x

0.1 × V R

Kx

C

Kx

to 0.9 × V

K30

= 510Ω to K30, = 470 pF to GNDB

K30

K

x

t

Krise

(x = 1, 2), measured from

16.27 K

16.28

16.29

16.30

16.31

fall time

x

Propagation delay K to RxD

= low

x

=low

x

Propagation delay Kx=high to RxD

=high

x

Symmetry of transmitter delay

Symmetry of receiver propagation delay

0.9 × V RKx=510Ω to K30, C

Kx

(x = 1, 2), measured from K

x

RxDx=HtoL (x = 1, 2), from

K

x

xDx= L to H (x = 1, 2),

t

SYM_Tx

(t

PDtH+tKrise

(x = 1, 2), t

SYM_Rx=tPDkL–tPDkH

LIN Bus Mode (Necessary for Operation: V

to 0.1 × V

K30

= 470 pF to GNDB

=0.4× V

=0.6× V

=(t

to

K30

to

K30

PDtL+tKfall

)

= 8V to 18V)

K30

) –

K

x

K

x

K

x

K

x

K

x

t

Kfall

t

PDkL

t

PDkH

t

SYM_Tx

t

SYM_Rx

Measured between

K30

,

and

K

1

dVK1/dt 1 3 V/µs A

t

Kx

high level = 0.8 × V low level = 0.2 × V R

=1kΩ to K30,

K1

= 3.3 nF to GNDB

C

K1

16.32

Slew rate for rising and falling edge

16.33 Maximum baud rate K Measured from TxD1

16.34

Propagation delay TxD to K

=low

1

low

1

H-> L to K R

K1

C

K1

= 0.9 × V

1

= 1 kΩ to K30, = 3.3 nF to GNDB

K30

K

1

t

PDtL

Measured from TxD1

16.35

16.36

Propagation delay TxD1 high to K1 = high

Propagation delay K

= low

RxD

1

low to

1

L to H to K1 = 0.1 × V RK1=1kΩ to K30,

= 3.3 nF to GNDB

C

K1

Measured from

=0.4× V

K

1

K30

to

RxD1=HtoL

K30

K

1

K

1

t

PDtH

t

PDkL

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

62.5 kBd A

1µsA

3µsA

4µsA

–1 1 µs A

20 kBd A

2.5 µs A

4µsA

56

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 17-1. Electrical Characteristics (Continued)– LIN/ISO 9141 Interfaces

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Measured from

=0.6× V

K

1

=LtoH

RxD

1

t

SYM_T1=tPDtL–tPDtH

t

SYM_R1=tPDkL–tPDkH

=40mA

I

Kx

=20mA

I

Kx

K30

to

(x = 1, 2), measured from rising edge of SSQ to

= 16.40V, RKx=250Ω to

V

Kx

K30, C

= 3.3 nF to GNDB

Kx

(x = 1, 2), measured from rising edge of SSQ to VKx=0.9× V

= 250Ω to K30,

R

Kx

K30

,

CKx= 3.3 nF to GNDB (x = 1, 2), output driver

deactivated, AMUX measurement activated and deactivated K30 = 5.5V to 15V K30 > 15V to 25V K30 > 25V to 40V

(x = 1, 2), output driver deactivated, AMUX measurement deactivated K30 = 5.5V to 40V

= –25V

K

x

K

1

K

1

K

1

K

x

K

x

K

x

K

x

K

x

t

PDkH

t

SYM_T1

t

SYM_R1

V

Kx

t

Kx

t

Kx

I

Kx

I

Kx

4µsA

–1 1 µs A

1.7

1.2

VA

50 µs A

10 µs A

–10 –10 –10

+100 +160 +260

µA µA µA

–150 +10 µA A

16.37

16.38

16.39

Propagation delay K RxD1=high

Symmetry of transmitter delay

Symmetry of receiver propagation delay

high to

1

LS Driver Mode

16.40 K

16.41 K

output voltage drop

x

switch-on delay

x

16.42 Kx switch-off delay

16.43 Kx leakage current

16.44 Kx leakage current

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

A A A

4929B–AUTO–01/07

Figure 17-2. Timing LIN/ISO 9141 Interface

2

Baudrate

V

TXD

V

RXD

K

t

PDtL

t

PDkL

90%

40%

t

PDtH

10%

60%

t

PDkH

Baudrate =

2

t

+ t

on

off

57

18. Voltage/Current Sources (IASGx Sources)

For a variable resistance measurement and especially for buckle-switch detection, five constant voltage sources, switchable between two different voltages (V1 and V2) are implemented. The current delivered by these voltage sources is mirrored by a factor of 1 / 10 or 1 / 15 to the pin ISENS and causes a voltage drop at the external resistor connected to this pin. This voltage drop can be measured at pin UZP by choosing the corresponding AMUX command. The external resistor at pin IASG

can be calculated using the following formulas:

x

R

ISENS

R

IASGx

------------------

10

R

ISENS

------------------

15

The current through pin IASG –50 mA. If the voltage at pin ISENS becomes higher than V consequently, the current at pin IASG used to reduce the current limitation of pin IASG

V

–

V1VV2

-----------------------------------------------

×=

V

-----------------------------------------------

×=

V

–

ISENS1VISENS2

V

–

V1VV2

–

ISENS1VISENS2

or

is internally limited to a value between I

x

, the voltage at pin IASG and,

VPERI

is reduced until V

x

to values lower than the internal limit by choos-

x

ISENS=VVPERI

= –150 mA and

IASGx

. This function can be

ing an adequate external resistor at pin ISENS. In this case, the maximum current through pin IASG

can be calculated as:

x

V

VPERI

------------------

10

15

×=

R

------------------

×=

R

ISENS

V

VPERI

ISENS

or

I

IASGxlim

I

IASGxlim

For high accuracy, the IASGx current needs to be between 0.5 mA and 40 mA, and the maximum ISENS voltage must be < V ISENS is clamped to V

+ 5%. Calculation of the resistor at pin ISENS:

PERI

– 40%. Under a clamping condition, the voltage at pin

PERI

58

RSENS 0.96 V

×

PERI

--------------------

×=

I

ASGmax

CR1

In applications with one or more unused IASG channels, the IASG pins can be used as measurement inputs. The five IASG pins are connected to the analog multiplexer block via different dividers. Voltages applied to these IASG pins can be measured at the UZP pin, selected via SPI commands.

ATA6264 [Preliminary]

4929B–AUTO–01/07

Figure 18-1. Functional Principle of the IASG Interface

Serial

interface

10

ATA6264 [Preliminary]

Serial

interface

1

Current mirror

15

Short circuit

IASGx

I = f(R)

Resistive

sensor

RIASGx

protection

Current limit

if V

ISENS

>V

V

V1

V

V2

+

-

C > 10 pF

PERI

ISENS

1

I/10 or I/15

R

ISENS

Serial

interface

UZP

Analog

multiplexer

Necessary for operation: V V V

and V

VCORE

and V

VCORE

= 3.7V to 5.47V, VCP > V

INT

> Reset threshold, V

VPERI

> Reset threshold, V

VPERI

EVZ

+ 7V

= 9V to 40V for operation with IASGx switched to 5V

EVZ

= 15V to 40V for operation with IASGx switched to 10V

EVZ

Operating conditions of all other supply pins: V

K30

and V

are within functional range limits, Tj = –40°C to 150°C

VSAT

Other pins: As defined in Section 4. ”Functional Range” on page 8, C 825Ω≥R

ISENS

≥ 5kΩ

IASGx

≥ 10 nF and

4929B–AUTO–01/07

59

Table 18-1. Electrical Characteristics – Voltage/Current Sources (IASGx Sources)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

(x = 1 to 5),

17.1 Output voltage (V1)

–40 mA < I V

= 0.96 × V

ISENS

IASGx

< –0.5 mA

VPERI

(x = 1 to 5),

17.2 Output voltage (V2)

–40 mA < I V

= 0.96 × V

ISENS

IASGx

< –0.5 mA

VPERI

IASGx switched to 5V

> 11V

V

EVZ

(x = 1 to 5),

17.2a Output voltage (V2)

–25 mA < I V

= 0.96 × V

ISENS

IASGx

< –0.5 mA

VPERI

IASGx switched to 5V V

> 9V to 11V

EVZ

Output voltage overshoot at

17.3

IASGx due to regulator characteristic

Maximum duration of voltage

17.4 overshoot at IASGx

Linear range for current mirror

17.5 at IASGx

Internal current limitation at

17.6 IASG

x

(x = 1 to 5) when IASG = 5V when IASG = 10V

(x = 1 to 5), with V R

LOAD

= 10V / 0.5 mA <

IASGx

< V

= 5V / 40 mA

IASGx

(x = 1 to 5), 0V = V

= 0.96 × V

ISENS

PERI

(x = 1 to 5) IASG

(x = 1 to 5),

= I

17.7 Current ratio #1

CR

1x

0V = V –40 mA < I

IASGx

= 0.96 × V

ISENS

IASGx

/ I

ISENS

< –0.5mA

VPERI

(x = 1 to 5),

= I

CR

2x

17.8 Current ratio #2

0V = V –40 mA < I

IASGx/IISENS

= 0.96 × V

ISENS

IASGx

VPERI

< –0.5 mA

(x = 1 to 5),

17.9 Settling time

R

= 250Ω, no capacitive

IASGx

load at IASGx (x = 1 to 5)

Measured from rising edge

17.10 Switch-on delay

of SSQ to

= 0.1 × V

V

IASGx

R

= 250Ω, no

IASGx

capacitive load at IASGx

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

IASG

x

IASG

x

IASG

x

IASG

x

IASG

x

IASG

x

IASG

x

IASG

x

ISENSE t

IASG

x

V1

V2

∆V

t

IASGx

I

IASGx

I

IASGx

CR

ISENSE

t

IASGx

1x

2x

–6% 10 +6% V A

–6% 5 +6% V A

5.9

11.3

V V

30 µs A

–40 –0.5 mA A

–150 –50 mA A

–3% 9.9 +3% A

–3% 14.9 +3% A

050µsA

A A

60

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 18-1. Electrical Characteristics (Continued)– Voltage/Current Sources (IASGx Sources)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

I

>CRY×

IASGx

Output voltage clamping

17.11 (V

ISENS

≤ V

VPERI

)

S

(x = 1 to 5), (Y = 1, 2) (V

ISENS

active)

17.12 ISENS leakage current V

= 0V to 0.96 × V

ISENS

(x = 1 to 5)

17.13 IASGx leakage current

IASGx channel deactivated, 0V < V

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

≤ V

IASGx

V

VPERI

< V

VPERI/RISEN

regulator

VPERI

EVZ

ISENSE V

ISENSE I

IASG

x

ISENSE

I

IASGx

0.96 ×

V

VPERI

1.05 × V

VPERI

VA

–1.6 +1.6 µA A

4929B–AUTO–01/07

61

19. AMUX (Analog Multiplexer for Voltage Measurements)

Various voltages and the chip temperature inside of the ATA6264 can be measured at the analog measurement output UZP. Different voltage dividers ensure that the values of the measured voltages at UZP are in the range of 0V to V face command has to be sent to the ATA6264.

For the list of measurable voltages and temperatures, refer to Section 22. ”Serial Interface Com-

mands” on page 68. The overall accuracy of the measurement part inside the ATA6264 can be

calculated using the following formula:

V

UZP

--------------------------------------------------------

ratio ratio tolerance±

meas

V

±=

UZPoffset

Figure 19-1. AMUX Tolerances

. To select a specific measurement, a serial inter-

PERI

max.

typ.

min.

V

in

V

UZP_offset

V

UZP_max

V

UZP_min

UZP

Vmeas

In order to describe the behavior of the whole measurement properly, the tolerance of the voltage-divider ratio (ratio tolerance) and the offset tolerance of the UZP buffer (V

UZPoffset

) are

defined in separate points. The UZP buffer is defined in the following section.

Necessary for operation: V

= 8V to 40V or VCP = 10V to 50V, V

EVZ

= 3.7V to 5.47V

VINT

Operating conditions of all other supply pins: V

K30

, V

VSAT

, V

VPERI

and V

are within functional range limits, Tj = –40°C to +150°C

VCORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

62

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 19-1. Electrical Characteristics – AMUX (Analog Multiplexer for Voltage Measurements)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Has to be calculated from the

18.1 Output offset error

values of the differential

UZP V

UZPoffset

measurement

18.2 Ratio V

18.2a Ratio V

18.3 Ratio V

18.3a Ratio V

18.4 Ratio V

18.4a Ratio V

18.5 Ratio V

18.5a Ratio V

18.6 Ratio V

18.6a Ratio V

18.7 Ratio V

K15/VUZP

K30/VUZP

EVZ/VUZP

SAT/VUZP

VCORE/VUZP

ISENS/VUZP

18.8 Ratio VK1/V

18.8a Ratio V

K1/VUZP

18.9 Ratio VK2/V

18.9a Ratio V

18.10 Ratio V

18.10a Ratio V

18.11 Ratio V

18.11a Ratio V

18.12 Ratio V

18.12a Ratio V

18.13 Ratio V

18.13a Ratio V

18.14 Ratio V

K2/VUZP

IASG1/VUZP

IASG2/VUZP

IASG3/VUZP

IASG4/VUZP

IASG5/VUZP

UZP

For V For V

For V For V For V

For V For V

For V For V For V V

VPERI

For V For V

For V For V For V

For V For V

For V

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V UZP Ratio 9.9 ± 2.3% A

VPERI

= 3.3V UZP Ratio 14.78 ± 2.6% A

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= V

VPERI

> V

VPERI

–0.2V ≥ V

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V UZP Ratio 10 ± 3% A

VPERI

= 3.3V UZP Ratio 14.75 ± 3% A

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

= 5V UZP Ratio 2 ± 2.3% A

VCORE

≥ 0.2V UZP Ratio 0.992 ± 1% A

ISENS

UZP Ratio

UZP Ratio 0.995 ± 1% A

UZP Ratio

UZP Ratio 0.995 ± 1% A

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

–5 +15 mV A

6.05 ± 4%

6.05 ± 2.3%

9.12 ± 6%

9.12 ± 2.3%

6.04 ± 6%

6.04 ± 2.3%

9.11 ± 6%

9.11 ± 2.3%

6.05 ± 6%

6.05 ± 2.3%

9.12 ± 6%

9.12 ± 2.3%

6.06 ± 3.5%

6.06 ± 2.3%

9.16 ± 3.5%

9.16 ± 2.3%

6.06 ± 3.5%

6.06 ± 2.3%

9.16 ± 3.5%

9.16 ± 2.3%

6.04 ± 6%

6.04 ± 2.3%

9.11 ± 6%

9.11 ± 2.3%

6.04 ± 6%

6.04 ± 2.3%

9.11 ± 6%

9.11± 2.3%

6.04 ± 6%

6.04 ± 2.3%

9.11 ± 6%

9.11 ± 2.3%

A A

4929B–AUTO–01/07

63

Table 19-1. Electrical Characteristics (Continued)– AMUX (Analog Multiplexer for Voltage Measurements)

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

18.15 Ratio V

18.15a Ratio V

USP/VUZP

For V For V

Special Measurement (For Detection of Band-gap Defect)

18.16 Ratio V

18.17

18.18

VINT/VUZP

Voltage 0.9 × V switched to V

UZP

Voltage 0.1 × V switched to V

UZP

VPERI

Input voltage range for

18.19

proper function of 10 or 14.6 divider

Input voltage range for

18.20

proper function of 6 or 9.1 divider

Input voltage range for

18.21

proper function of 4 and 2 divider

Input voltage range for

18.22 proper function of 1 buffer

18.23 Ratio V

REF/VUZP

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

= 5V (1.5V to 3V)

VPERI

= 5V (> 3V to 25V)

VPERI

= 3.3V (1.5V to 3V)

VPERI

= 3.3V (> 3V to 25V)

VPERI

UZP Ratio

6.02 ± 6%

6.02 ± 2.3%

9.07 ± 6%

9.07 ± 2.3%

UZP Ratio 3.99 ± 2.6% A

UZP Ratio (0.9 × V

UZP Ratio (0.1 × V

V

Input

640VA

1.5 25 V A

46VA

0.2

) ± 2% A

VPERI

) ± 2% A

VPERI

V

VPERI

– 0.2

VA

–2% 1 0% A

A A

64

ATA6264 [Preliminary]

4929B–AUTO–01/07

20. UZP Buffer

ATA6264 [Preliminary]

The pin UZP is an analog output pin of the ATA6264. The UZP buffer is realized as a tristate output with the ability to drive to VPERI as well as to GNDA. The selected measurement result is given to the pin UZP as long as no new measurement is selected or the tristate command has been sent. Driver capability is typically 4 mA.

Figure 20-1. Functional Principle of the UZP Buffer

V

Tristate / normal

operating

2 to 8 mA

VPERI

Voltage selected

voltage from

AMUX

Driver

circuitry

Driver

circuitry

2 to 8 mA

GNDA

Necessary for operation: V

> Reset threshold, VCP = 10V to 50V, V

PERI

= 3.7V to 5.47V

VINT

Operating conditions of all other supply pins: V

, V

K30

EVZ

VSAT

and V

are within functional range limits, TJ = –40°C to +150°C

VCORE

Other pins: As defined in Section 4. ”Functional Range” on page 8.

UZP

470 to 2000Ω

1 to 47 nF

4929B–AUTO–01/07

65

Table 20-1. Electrical Characteristics – UZP Buffer

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Output current high side,

19.1

driving current with measurement activated

Output current low side,

19.2

sink current with measurement activated

19.3 Output settling time

19.4 Output settling time

19.5 Output resistance UZP R

19.6 Linear measurement range UZP V

19.7 Maximum output voltage

19.8 Output leakage current

19.9 Output capacitance UZP buffer in tristate mode UZP C

19.10 Time to switch to tristate mode

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

= 0V,

V

UZP

UZP connected to GND

V

= V

UZP

VPERI

UZP connected to GND

Measured from rising edge of SSQ to 90% of V

UZP

, no

load at pin UZP Load 2 kΩ/22 nF low-pass

filter connected to pin UZP, measured from rising edge of SSQ to 90% of V

Low pass filter out

V

switched via AMUX

IASG5

to UZP, V

= 0V to V

V

UZP

IASG5

= 6V

VPERI

, UZP

buffer in tristate mode

Measured from rising edge of SSQ to I

leak

within

tolerance

UZP I

UZP t

UZP V

UZP I

UZP t

UZP

–8 –2 mA A

28mAA

10 µs A

250 µs A

100 Ω A

0.2

V

VPERI

–

50 mV

VPERI

– 0.2

V

VPERI

+

50 mV

VA

V

–5 +5 µA A

010pFD

3µsA

66

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

21. Chip Temperature Measurement

A serial interface command allows measuring a chip-temperature–dependent voltage which is generated by two diodes connected in series. Three 2-diode sensors are connected in parallel and located in the following blocks: VPERI, VCORE, and VSAT. The diodes are supplied by a temperature-constant current source, the voltage drop of the diodes is switched via AMUX to pin UZP. If the overtemperature level is exceeded, bit a7 in the status register is set to “1”.

Necessary for operation: V

= 3.7V to 5.47V

INT

Operating conditions of all other supply pins: V

, V

K30

EVZ

VSAT

, V

Other pins: As defined in Section 4. ”Functional Range” on page 8.

Table 21-1. Electrical Characteristics – Chip Temperature Measurement

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Temperature coefficient of

20.1

chip-temperature sensor Output voltage temperature

20.2

sensor

Threshold overtemperature

20.3

detection

Hysteresis for overtemperature

20.3a detection

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter

Chip temperature switched via AMUX to UZP

Chip temperature switched via AMUX to UZP, TJ=25°C

If overtemperature is detected, voltage drops by 35 mV

VPERI

and V

are within functional range limits, Tj = –40°C to 150°C

VCORE

UZP V

UZP

–4 –3.6 –3.2 mV/K D

1.29 1.54 V A

155 185 °C B

525KB

4929B–AUTO–01/07

67

22. Serial Interface Commands

22.1 Overview

All functions of the ATA6264 are triggered by 16-bit serial interface commands. Some of these commands are latched because their actions have to continue for a longer time. Other commands have to be executed as long as no other command is received via the serial interface.

The pin SSQ (low active) is used to select the ATA6264. If pin SSQ is inactive (high), the output pin MISO is disabled (tristate) and the signals at the pins SCLK and MOSI are ignored and do not affect the data in the serial interface register.

With the falling edge at pin SSQ, the ATA6264 response on the previous command is latched in the ATA6264 status register and, after a short delay time, the signal at pin MISO is valid. With the rising edge at pin SCLK, the data at pin MOSI is shifted into the serial interface input register and the next bit of the status register is shifted to pin MISO. A command received at pin MOSI is valid and will be executed if the number of rising edges at pin SCLK was exactly 16 during data transmission; otherwise, the received signal will be ignored.

The slave select pin, SSQ, allows the individual selection of different slave SPI devices. Slave devices that are not selected do not interfere with SPI bus activities. To ensure deactivation of the device in case of an open SSQ pin, an internal current source is implemented to drive the SSQ pin to high level (VPERI).

All commands, independent of their function, consist of 16 bits. The serial interface includes a 16-bit input shift register, 16-bit latches, and a decoder logic block for the generation of the SPI command signals.

To suppress data transfer errors in the case of spikes or glitches on the clock signal, a 16-clock-cycle counter is provided. Only after 16 clock cycles does the rising edge of SSQ cause an internal signal latch enable, which transfers the data from the shift register to the 16-bit latch. The data word is decoded to address the correct functional block.

Table 22-1. Electrical Characteristics – Serial Interface Commands

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

SSQ to SCLK rising-edge

21.1 isolation

21.2 SSQ lag time SSQ t

21.3 Fall time

21.3a Fall time

(2)

21.4 Rise time

21.4a Rise time

(2)

21.5 Data set-up time MOSI t

21.6 Data hold time MOSI t

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Voltage levels for serial interface timing measurements: High level = 0.7 × V

2. Timing specified with a 100-pF external load at pin MISO

3. System requirement

SCLK t

SSQ, SCLK,

MOSI MISO t

SSQ, SCLK,

MOSI MISO t

iso

lag

t

f

t

r

su

hold

VPERI

100 ns A

20 ns A 20 ns A

, low level = 0.2 × V

20 ns A

VPERI

(3)

68

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 22-1. Electrical Characteristics (Continued)– Serial Interface Commands

No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*

Time from SSQ falling edge to

21.7 MISO MSB valid

Time from SCLK rising edge to

21.8 MISO valid

Time from SSQ rising edge to

21.9 MISO tristate condition

No-data time between serial

21.10 interface commands

21.11 Clock frequency CLK f

21.12 Pull-up current VPERI SSQ R

21.13 Pull-up current VPERI SCLK R

21.14 SCLK high/low time SCLK t

21.15 Input voltage high level

21.16 Input voltage low level

21.17 Input voltage hysteresis SCLK V

21.18 Output voltage high level I

21.19 Output voltage low level I Output current high level driven

21.20 to short circuit

Output current low level sinking

21.21 from VPERI level

21.22 Input capacitance

21.23 Output capacitance Switched-off condition MISO C

21.24 Leakage current Switched-off condition MISO I Number of clock cycles to be

detected between falling and

21.25 rising edge of SSQ, to set error

signal in status register to “0”

*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Note: 1. Voltage levels for serial interface timing measurements: High level = 0.7 × V

2. Timing specified with a 100-pF external load at pin MISO

3. System requirement

(2)

MISO t

SSQ, SCLK,

MOSI

SSQ, SCLK,

MOSI

= –1 mA to 0 mA MISO V

MISO

= 0 mA to 1 mA MISO V

MISO

= 5V MISO I

V

VPERI

V

= 5V MISO I

VPERI

SSQ, SCLK,

MOSI

MISOMSB_V

MISOV

MISOhiZ

t

nodata

SCLK

pu_SSQ

pu_SCLK

CL

V

H

V

L

HYS

H

L

MISO

C

IN

MISO

VPERI

0 400 ns A

040nsA

1.5 µs A

08MHzA –95 –45 µA A –95 –45 µA A

40 ns A

0.5 ×

V

VPERI

0.25 ×

V

VPERI

50 250 mV A

V

VPERI

– 0.8

V

VPERI

VA

00.4VA

–47 –10 mA A

645mAA

10 pF D

–10 +10 µA A

16 16 A

, low level = 0.2 × V

VPERI

(3)

A

4929B–AUTO–01/07

69

Figure 22-1. Timing Serial Interface

SSQ

SCLK

4. (< 20 ns)

5. (> 20 ns) 6. (> 20 ns)

3. (< 20 ns)

10. (> 1.5 µs)

1. (> 100 ns)2. (> 100 ns)

14. (> 40 ns)

#16#1

MOSI

MISO

not defined

7. (< 400 ns)

not

defined

22.2 Set Commands

LSBMSB

8. (< 40 ns)

LSBMSB

9. (< 40 ns)

not

defined

After a reset due to the watchdog or undervoltage, all internal control registers and decoded signals are set to their default values.

Table 22-2. Set of Serial Interface Commands

MSByte LSByte

7654321076543210

Command Latch Hex Description

NOP No 0000 0000000000000000

Key latch Yes 3xxx

Watchdog No 6xxx

Switch commands Yes 9xxx

Initial programming N/A Axxx

Diagnosis No Cxxx

IASG No Fxxx

See Table 22-3 on

page 71

See Table 22-4 on

page 71

See Table 22-5 on

page 71

See Table 22-6 on

page 72

See Table 22-7 on

page 72

See Table 22-8 on

page 73

Test mode 1 No 55AA 0101010110101010 Test mode 2 No AA55 1010101001010101 Test mode 3 No 5500 0101010100000000

Test-mode enable No 5A5A 0101101001011010

Command Option and Data

0011xxxxxxxxxxxx

0110xxxxxxxxxxxx

1001xxxxxxxxxxxx

1010xxxxxxxxxxxx

1100xxxxxxxxxxxx

1111xxxxxxxxxxxx

70

Serial interface commands other than those listed in Table 22-2 on page 70 lead to an interrup- tion of measurements via AMUX, cause pin UZP to be switched to tristate, and IASG sources to be deactivated. The status of the latches does not change.

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 22-3. Key Latch Commands

MSByte LSByte

Description

Key latch set 0011111111111111 3FFF Key latch reset (default) 0011000000000000 3000

Table 22-4. Watchdog Commands

MSByte LSByte

Description

Trigger watchdog 0110101001010101 6A55 Configure prescaler 0110000011110abc 60Fx

Table 22-5. Switch Commands

MSByte LSByte

Description

Enable EVZ switching 1001101001011010 9A5A EVZ switched to 33V 1 0 0 1 0 0 1 1 0 0 0 0 1 1 1 1 930F EVZ switched to 23V

(default) EVZ switched to external

divider CP-OUT switched to

high-ohmic state (default) CP-OUT switched to

low-impedance state K1 interface works as

ISO9141 or LIN interface (depending on ISO/LIN bit of initial programming) (default)

K1 interface works in LS driver mode

K1 switched to high-ohmic state (default)

K1 switched to low-impedance state

K2 interface works as ISO9141 interface (default)

K2 interface works in LS driver mode

K2 switched to high-ohmic state (default)

K2 switched to low-impedance state

1001001111110000 93F0

1001001110010110 9396

1 0 0 1 0 1 1 0 0 0 0 0 1 1 1 1 960F

1001011011110000 96F0

1001100111110000 99F0

1001100111111111 99FF

1001110011110000 9CF0

1001110011111111 9CFF

1001100100000000 9900

1 0 0 1 1 0 0 1 0 0 0 0 1 1 1 1 990F

1001110000000000 9C00

1001110000001111 9C0F

Because the K1 and K2 interfaces are by default switched to ISO (LIN) mode, the commands 9CF0, 9CFF, 9C00, and 9C0F default to invalid commands.

Hex Code7654321076543210

4929B–AUTO–01/07

71

Table 22-6. Initial Programming (IP Command)

MSByte LSByte

Description

Hex Code7654321076543210

Write data to IP register 1 0 1 0 1 0 0 1 x x x x x x x x A9xx

The initial programming command is only available in Test mode. For more information about the programming flow and the register contents, see Section 5.2 ”Initial Programming of the

ATA6264” on page 11.

Table 22-7. Diagnosis Commands

MSByte LSByte

Description

Set UZP to tristate mode and switch off all

1100000000000000 C000

measurements Switch V

UZP Switch V

UZP Switch 90% × V

AMUX to UZP Switch 10% × V

AMUX to UZP Switch V

UZP Switch V

UZP

via AMUX to

EVZ

via AMUX to

VSAT

VPERI

via AMUX to

VCORE

via AMUX to

K15

via AMUX to

K30

via AMUX to

IREF

via AMUX to

IASG1

via AMUX to

IASG2

via AMUX to

IASG3

via AMUX to

IASG4

via AMUX to

IASG5

via AMUX to

USP

via AMUX to

K1

via AMUX to

K2

via

1100101000110001 CA31

1100101000110010 CA32

1100101000110100 CA34

1100101000111000 CA38

1100101001100001 CA61

1100101001100010 CA62

1100101001100100 CA64

1100101001101000 CA68

1100101010010010 CA92

1100101010010100 CA94

1100101010011000 CA98

1100101011000001 CAC1

1100101011000010 CAC2

1100101011000100 CAC4

1100101011001000 CAC8

1100101011100001 CAE1

Note: 1. UZP voltage will be influenced by the USP voltage

Hex Code7654321076543210

72

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

Table 22-7. Diagnosis Commands (Continued)

MSByte LSByte

Description

Switch V UZP

Switch voltage at chip-temperature sensor via AMUX to UZP

Note: 1. UZP voltage will be influenced by the USP voltage

via AMUX to

VINT

1100101011100010 CAE2

1100101011100100 CAE4

Because the diagnosis commands are non-latching commands, any new serial interface commands, except watchdog triggering (6A55) and the Kx switching commands (9Cxx), interrupt the diagnosis.

Table 22-8. IASG Commands

MSByte LSByte

Description

IASGx switched to 10V (mirror factor 10:1)

IASGx switched to 10V (mirror factor 15:1)

IASGx switched to 5V (mirror factor 10:1)

IASGx switched to 5V (mirror factor15:1)

11110abc00110011 Fx33

11110abc00111100 Fx3C

11110abc11000011 FxC3

11110abc11001100 FxCC

Hex Code7654321076543210

(1)

Hex Code7654321076543210

Note: a, b, and c represent the IASG number in binary format; only 001 = IASG1, 010 = IASG2,

011 = IASG3, 100 = IASG4, and 101 = IASG5 are valid commands

Table 22-9. Example

MSByte LSByte

Description

IASG1 switched to 10V (mirror factor 10:1)

IASG5 switched to 5V (mirror factor 15:1)

1111000100110011 F133

1111010111001100 F5CC

Hex Code7654321076543210

Because the IASG commands are non-latching commands, any new serial interface command, except watchdog triggering (6A55) and the Kx switching commands (9Cxx), interrupts the IASG function.

4929B–AUTO–01/07

73

22.3 Serial Interface Status Register

For all serial interface commands except the test-mode commands (55AAh, AA55h, 5500h), the ATA6264 status is available at the MISO line. For the status register a 16-bit structure is used, one bit for each information.

Table 22-10. Status Register

MSBit LSBit MSBit LSBit

a7 a6 a5 a4 a3 a2 a1 a0 b7 b6 b5 b4 b3 b2 b1 b0

Table 22-11. Information Provided by the Itemized Bits of the Status Register

Bit Set To Information

a7 High Chip temperature reports overtemperature

Low Chip temperature reports normal temperature

a6 High Overtemperature at K1 output

Low Normal temperature at K1 output

a5 High Overtemperature at K2 output

Low Normal temperature at K2 output

a4 High Latch for GKEY function is set

Low Latch for GKEY function is not set

a3 High EVZ switched to 33V, EVZ switched to external divider

Low EVZ switched to 23V

a2 High CP-OUT switch is low impedance

Low CP-OUT switch is high ohmic

a1 High CP-OUT voltage too low

Low CP-OUT voltage is in correct voltage range

a0 High CP voltage too low

Low CP voltage is in correct voltage range

b7 High Voltage at pin USP above detection threshold

Low Voltage at pin USP below detection threshold

b6 High GNDA or GNDB disconnected

Low GNDA and GNDB connected

b5 High Previously sent serial interface command was invalid (default after power-on reset)

Low Previously sent serial interface command was valid

b4 High Error during last serial interface transmission (default after power-on reset)

Low No error during last serial interface transmission

b3 High IC is in Test mode

Low IC is in Normal mode b2 Reflects bit b2 of the watchdog prescaler b1 Reflects bit b1 of the watchdog prescaler b0 Reflects bit b0 of the watchdog prescaler

Byte A Byte B

74

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

The overtemperature bits a5, a6 and a7 are latched when overtemperature is detected. These bits will be reset with the next SPI command, unless overtemperature still exists.

In the case of a reset, bits b4 and b5 are not set to their default state. These bits show the status before reset so that the microcontroller can detect whether or not the ATA6264 is in power-up state.

Table 22-12. Test Command Issued via the MISO line as a Result of the Test Mode

Commands

Description Command MISO Answer Hex Code

Test mode 1 55AA 1010101001010101 AA55 Test mode 2 AA55 0101010110101010 55AA Test mode 3 5500 0 0 0 0 0 0 0 1 a b c d e f g h 01xx

Note: a, b, c, d, e, f, g, h represent the contents of the Initial Programming Register

4929B–AUTO–01/07

75

23. Test Mode

For better testability of the ATA6264, a test mode is implemented. This mode is activated if the pins RESQ and TxD1 are connected to GND, the pins RESQ2 and TxD2 are connected to VPERI, and the serial interface command 5A5Ah is sent to the ATA6264. Test mode is latched as long as the ATA6264 is powered (V

> 4.2V to 5V and V

K30

> 3V to 4V). In Test mode the

K15

watchdog is disabled, which means that RESQ and RESQ2 depend on the voltage levels of the pins VCORE, VPERI and EVZ. In order to provide the programming voltage at VSAT for the initial programming, V

is set to 11.7V (±0.5V) in Test mode if the lock bit is not set.

VSAT

After a reset, Test mode is disabled (default).

The following serial interface commands are used for the ATA6264 supplier test: E6B5(h) and E6BA(h).

Figure 23-1. How to Enable Test Mode

RESQ

TxD1

Enable

testmode

SPI

decoder

RESQ2

TxD2

SSQ

MISO

MOSI

SCLK

V

PERI

5A5A (h)

76

ATA6264 [Preliminary]

4929B–AUTO–01/07

24. Application Circuits

Figure 24-1. Overview of a Typical Airbag System

ATA6264 [Preliminary]

D, L, C

net

K30

GEVZ OCEVZ GNDB EVZ FBEVZ COMEVZ SVSAT COMSATO COMSATI VSAT VPERI

VPERIFB SVCORE VCORE COMCOI COMCOO

Firing ASIC

K15

K15 K1

K1K30 K2 IASG1 to 5

Enable

K2 RESQ2

IASG1 to 5USP IREF

UZP

RxD2

TxD2

RxD1

TxD1

RESQ

GNDD

ISENS

CP-OUTCP

GNDA

Serial

interface

Micro-

controller

Sensor

Safetysystem

monitoring

Firing loops

4929B–AUTO–01/07

77

Figure 24-2. Typical Application Circuit

SSQ

SCLK

Cp

SCLK

SSQ

K30

KL15

K15

USP

FBEVZ

COMEVZ

EVZ (33V)

EVZ

GEVZ

OCEVZ

ATA6264

VSAT

VPERI

SVSAT

VSAT (9V)

VCORE

SVCORE

VCORE (5V)

VPERI (5V)

COMCOO

SVPERI

COMCOI

COMSATI

COMSATO

RESQ

RESQ2

VINT

MISO

MOSI

RxD1

KL30

TxD1

RxD2

TxD2

UZP

K1

K2

IASG2

IASG1

IASG3

IASG4

ISENS

IASG5

CP-OUT

IREF

CP-OUT

GNDB

GNDA

GNDD

78

ATA6264 [Preliminary]

4929B–AUTO–01/07

ATA6264 [Preliminary]

25. Ordering Information

Extended Type Number Package Remarks

ATA6264-ALTW P-TQFP44 Tray ATA6264-ALQW P-TQFP44 Taped and reeled

26. Package Information

Package: P-TQFP 44 (acc. JEDEC OUTLINE No. MO-112)

Dimensions in mm

12±0.2

10±0.05

44 34

1

11

12 22

+0.08

0.37-0.07

Drawing-No.: 6.543-5131.01-4 Issue: 1; 11.05.06

8

33

0.8

23

technical drawings according to DIN specifications

0.6±0.15

0.1±0.05

0.2

1.4±0.05

4929B–AUTO–01/07

79

27. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document.

Revision No. History

4929B-AUTO-01/07

• Put datasheet in a new template

• Section 23 “Test Mode” on page 76 changed

80

ATA6264 [Preliminary]

4929B–AUTO–01/07

28. Table of Contents

1 Description ............................................................................................... 1

2 Pin Configuration ..................................................................................... 4

3 Absolute Maximum Ratings .................................................................... 6

4 Functional Range ..................................................................................... 8

ATA6264 [Preliminary]

Features ..................................................................................................... 1

1.1 Block Description .................................................................................................3

1.1.1 Integrated Boost Converter EVZ .....................................................................3

1.1.2 Integrated Buck Converter VSAT ....................................................................3

1.1.3 Integrated Buck Converter VCORE ................................................................3

1.1.4 Linear Regulator VPERI ..................................................................................3

1.1.5 Blocks Included ...............................................................................................3

4.1 Protection Against Substrate Currents .................................................................9

5 Supply Currents ..................................................................................... 10

5.1 Discharger Circuit ...............................................................................................11

5.2 Initial Programming of the ATA6264 ..................................................................11

5.3 Start-up and Power-down Procedure .................................................................14

5.3.1 Start-up Procedure if VVCORE is Programmed to Be 5V or 2.5V ................15

5.3.2 The Power-down Procedure Takes Place in Different Phases .....................15

5.3.3 Start-up Procedure if VVCORE Programmed to Be 1.88V ...........................16

5.3.4 The Power-down Procedure for VVCORE is Programmed to be 1.88V .......17

6 Power Supply Sequencing .................................................................... 18

7 Charge Pump .......................................................................................... 20

8 GKEY Function ....................................................................................... 22

9 EVZ Step-up Regulator .......................................................................... 24

10 VSAT Power Supply ............................................................................... 30

11 VPERI Power Supply ............................................................................. 33

12 VCORE Power Supply ........................................................................... 35

4929B–AUTO–01/07

13 USP Comparator for General Purpose ................................................. 39

14 Reference Voltage and Reference Current Generation ...................... 40

15 Reset Function (Pin RESQ and Pin RESQ2) ........................................ 41

16 Watchdog Function ............................................................................... 47

81

17 LIN/ISO 9141 Interfaces ......................................................................... 54

18 Voltage/Current Sources (IASGx Sources) ......................................... 58

19 AMUX (Analog Multiplexer for Voltage Measurements) ..................... 62

20 UZP Buffer .............................................................................................. 65

21 Chip Temperature Measurement .......................................................... 67

22 Serial Interface Commands ................................................................... 68

22.1 Overview ............................................................................................................68

22.2 Set Commands ..................................................................................................70

22.3 Serial Interface Status Register .........................................................................74

23 Test Mode ............................................................................................... 76

24 Application Circuits ............................................................................... 77

25 Ordering Information ............................................................................. 79

26 Package Information ............................................................................. 79

27 Revision History ..................................................................................... 80

82

ATA6264 [Preliminary]

4929B–AUTO–01/07

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4929B–AUTO–01/07

Atmel ATA6264 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

1.1 Block Description

1.1.1 Integrated Boost Converter EVZ

1.1.2 Integrated Buck Converter VSAT

1.1.3 Integrated Buck Converter VCORE

1.1.4 Linear Regulator VPERI

1.1.5 Blocks Included

2. Pin Configuration

3. Absolute Maximum Ratings

4. Functional Range

4.1 Protection Against Substrate Currents

5. Supply Currents

5.1 Discharger Circuit

5.2 Initial Programming of the ATA6264

5.3 Start-up and Power-down Procedure

5.3.2 The Power-down Procedure Takes Place in Different Phases Phase1: If the ignition key is switched off, K15 voltage will vanish at pin K15. If the serial inter-

6. Power Supply Sequencing

7. Charge Pump

8. GKEY Function

9. EVZ Step-up Regulator

10. VSAT Power Supply

11. VPERI Power Supply

12. VCORE Power Supply

13. USP Comparator for General Purpose

14. Reference Voltage and Reference Current Generation

15. Reset Function (Pin RESQ and Pin RESQ2)

16. Watchdog Function

17. LIN/ISO 9141 Interfaces

18. Voltage/Current Sources (IASGx Sources)

19. AMUX (Analog Multiplexer for Voltage Measurements)

20. UZP Buffer

21. Chip Temperature Measurement

22. Serial Interface Commands

22.1 Overview

22.2 Set Commands

22.3 Serial Interface Status Register

23. Test Mode

24. Application Circuits

25. Ordering Information

26. Package Information

27. Revision History

28. Table of Contents