Atmel ATA6264 User Manual
Features
• Maximum Supply Voltage 40V
• One Programmable/Adjustable Boost Converter
• Two Programmable Buck Converters
• One Programmable Linear Regulator
• OTP Customer Mode
• 16-bit Serial Interface
• Two ISO9141 Interfaces (One Interface Programmable to LIN Functionality)
• Watchdog
• Various Diagnosis Functions
• 5 Voltage Sources Tailored to Resistor Measurement
• Charge Pump
• Small, 44-pin Package
• ESD Protection Against 2kV and 4kV
1. Description
With the introduction of the ATA6264, Atmel® introduces a new generation of airbag
power supplies for future airbag systems tailored to the needs of the automotive
industry. It is designed in Atmel’s 0.8 micron BCDMOS technology. ATA6264 contains
all the necessary blocks to supply the microcontroller, the firing capacitors, and
peripheral components of the airbag system. The power supply specifically fulfills the
power requirements of dual-voltage microcontrollers used in modern ECUs. The integrated watchdog and diagnosis blocks additionally support the safety aspects. The
8-MHz 16-bit SPI enables a high communication speed. Despite the high-level functionality, ATA6264 comes in a space-saving QFP44 package.
Airbag Power
Supply IC
ATA6264
Preliminary
4929B–AUTO–01/07
Figure 1-1. Block Diagram
SVSAT
VSAT
V
BATT
RESQ
RESQ2
GNDD
TxD1
RxD1
TxD2
RxD2
K1
K2
IASG1
IASG2
IASG3
IASG4
IASG5
ISENS
MOSI
SSQ
MISO
Serial Interface
Watchdog
Reset
ISO9141
IASG
SCLK
CP_OUT
CP Logic
CP
GKEY-
Logic
EVZ-
Regulator
VSAT-
Regulator
VPERI-
Regulator
K15
K30
GEVZ
OCEVZ
GNDB
EVZ
FBEVZ
COMEVZO
SVSAT
COMSATO
COMSATI
VSAT
SVPERI
VPERI
V
VPERI
V
V
EVZ
VSAT
SVCORE
UZP
GNDA
2
ATA6264 [Preliminary]
UZP
V
BATT
AMUX
USP
USP
Internal Supply
Reference
VINT
IREF
VCORE-
Regulator
VCORE
COMCOI
COMCOO
V
VCORE
4929B–AUTO–01/07
1.1 Block Description
1.1.1 Integrated Boost Converter EVZ
With an external n-channel FET, the integrated boost converter EVZ provides 3 different voltages adjustable via the serial interface for the energy reserve and firing capacitors. Two
voltages are fixed values; one voltage can be adjusted using an external resistive divider.
1.1.2 Integrated Buck Converter VSAT
The integrated buck converter VSAT is a fully integrated step-down converter supplied by the
boost converter, EVZ, and providing 7.8V, 9.1V, or 10.4V. The user can program the voltage via
an OTP system.
1.1.3 Integrated Buck Converter VCORE
The integrated buck converter VCORE is a fully integrated step-down converter supplied either
by the boost converter, EVZ, or by the battery, and providing 1.88V, 2.5V, or 5V. The user can
program the voltage via an OTP system.
1.1.4 Linear Regulator VPERI
The linear regulator, VPERI, is supplied from the buck converter VSAT and provides an accurate
voltage of 3.3V ±3% or 5V ±4% as a supply for sensitive elements such as sensors and ADC
references with the current capability of 100 mA. The user can program the voltage via an OTP
system. With a sophisticated power-sequencing concept of VCORE and VPERI, ATA6264 supports dual-voltage-supply microcontrollers, so that under all conditions the voltage difference
between the two linear regulator voltages never drops below a defined value. This measure
guarantees the safe operation of the system.
ATA6264 [Preliminary]
1.1.5 Blocks Included
• A general purpose comparator USP, for, for example, low battery voltage detection
• A band gap as reference for all internal voltages and currents
• Two ISO9141 interfaces, one of which is configurable via OTP in accordance with the LIN
specification
• Five constant voltage sources with current-to-voltage mirrors used for resistance
measurements, such as buckle switch detection in the range from –0.5 mA to –40 mA
• An AMUX block with push-pull buffer stage provides the output of all analog values such as
voltage sources, low voltage detection, or the chip temperature for continuous diagnosis
• A 16-bit serial interface for the communication with the microcontroller which includes a 16-bit
shift register, a 16-bit latch, and a decoder-logic block
• A watchdog to monitor the microcontroller and to generate reset signals in the case of failure
• Internal oscillator generates internal clock signals
• GKEY function to control the main switch of the ECU via a logic signal
4929B–AUTO–01/07
3
2. Pin Configuration
Figure 2-1. Pinning QFP44
COMEVZO
GNDB
GEVZ
OCEVZ
FBEVZCPSVCORE
CP-OUT
COMCOO
COMCOI
COMSATO
44 43 42 41 35 343638 373940
1
USP
K30
2
K1
3
K2
4
IASG1
IASG2
IASG3
IASG4
IASG5
ISENS
TxD1
5
6
7
8
9
10
11
12 13 14 15 21 222018 191716
RxD2
RxD1
RESQ
TxD2
MISO
SSQ
Table 2-1. Pin Description
Pin Symbol Function
1 USP Comparator input
2 K30 Continuous connection to the car battery
3 K1 Bus line of 1
4 K2 Bus line of 2
5 IASG1 Output of voltage source 1
6 IASG2 Output of voltage source 2
7 IASG3 Output of voltage source 3
8 IASG4 Output of voltage source 4
9 IASG5 Output of voltage source 5
10 ISENS Output of the current mirror from the IASGx interface
11 TXD1 Data input of the 1
12 RESQ Reset output
13 RXD2 Data output of the 2
14 RXD1 Data output of the 1st ISO9141 interface
15 TXD2 Data input of the 2
16 MISO Data output of the serial interface
17 SSQ Chip select of the serial interface
18 SCLK Clock input of the serial interface
19 MOSI Data input of the serial Interface
20 RESQ2 Redundant reset output
21 IREF Connection for the external reference resistor
22 UZP Analog measurement output
st
ISO9141 interface
nd
ISO9141 interface
st
ISO9141 interface
nd
ISO9141 interface
nd
ISO9141 interface
MOSI
SCLK
IREF
RESQ2
33
32
31
30
29
28
27
26
25
24
23
UZP
K15
EVZ
SVSAT
VSAT
GNDD
VINT
COMSATI
VCORE
GNDA
SVPERI
VPERI
4
ATA6264 [Preliminary]
4929B–AUTO–01/07
Table 2-1. Pin Description
Pin Symbol Function
23 VPERI Input for the VPERI regulator, internally used VPERI supply
24 SVPERI Output of VPERI regulator power transistor
25 GNDA Analog GND
26 VCORE Input for VCORE regulator
27 COMSATI Input of the VSAT externally compensated error amplifier
28 VINT Output of internal supply voltage
29 GNDD Digital GND
30 VSAT Input for VSAT regulator, internally used VSAT supply
31 SVSAT Output of VSAT regulator power transistor
32 EVZ Input for EVZ regulator, internally used EVZ supply
33 K15 Connection to car battery via the ignition key
34 COMSATO Output of the VSAT externally compensated error amplifier
35 COMCOI Input of the VCORE externally compensated error amplifier
36 COMCOO Output of the VCORE externally compensated error amplifier
37 CP-OUT Switchable output of charge pump voltage
38 SVCORE Output of VCORE regulator power transistor
39 CP Charge pump output
40 FBEVZ Input for external resistor divider to adjust EVZ voltage
41 OCEVZ Input for overcurrent measurement of the EVZ regulator
42 GEVZ Gate driver output for the external FET of the EVZ regulator
43 GNDB GND connection of all power stages
44 COMEVZO Output of the EVZ externally compensated error amplifier
ATA6264 [Preliminary]
4929B–AUTO–01/07
5
3. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
Parameters Remark Minimum Maximum Unit
Any combination of one or more pins
applied with any voltage between the
Voltage at pins, connected directly or
indirectly to the car battery
(K30, K15, USP)
Voltage at pins, connected directly or
indirectly to the car battery (K1, K2)
Voltage at pins, connected directly or
indirectly to the car battery (IASG1,
IASG2, IASG3, IASG4, IASG5)
Voltage at ECU internal pins (FBEVZ,
EVZ, VSAT)
Maximum rate of change at pin VSAT 1V/µs
Voltage at ECU internal pins (SVSAT,
SVCORE)
Voltage at ECU internal pins (CP,
CP-OUT)
Voltage at ECU internal pins (GEVZ,
OCEVZ)
Voltage at ECU internal pins (COMEVZO,
COMSATO, COMSATI, VPERI, SVPERI,
VCORE, COMCOI, COMCOO, IREF, UZP,
ISENS, RXD1, TXD1, RXD2, TXD2,
RESQ, RESQ2, MISO, MOSI, SSQ,
SCLK, VINT)
Current at logic pins
ESD classification at pins connected to
devices outside the ECU (K30, K15)
limits
K30 and K15 connected via diode to V
USP connected via minimum 5 kΩ to V
(maximum reverse current 5 mA).
Any combination of one or more pins
applied with any voltage between the
limits
Any combination of one or more pins
applied with any voltage between the
limits
Any combination of one or more pins
applied with any voltage between the
limits
Any combination of one or more pins
applied with any voltage between the
limits
Any combination of one or more pins
applied with any voltage between the
limits
Any combination of one or more pins
applied with any voltage between the
limits
These voltages can be applied in any
combination with any voltage between the
limits
Connected to voltages outside of
maximum voltage ratings via resistor
Batt
Batt
–0.3 +45 V
.
–25 +45 V
Voltage
necessary to
drive –40 mA
stored in 20 µH
–0.3 +45 V
–1 +45 V
–0.3 +56 V
–0.3 +10 V
–0.3 +7 V
–3 +3 mA
45 V
Human body model (HBM) HBM
AEC Q100-002
6
ATA6264 [Preliminary]
±4000 V
4929B–AUTO–01/07
ATA6264 [Preliminary]
3. Absolute Maximum Ratings (Continued)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referenced to an ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
Parameters Remark Minimum Maximum Unit
ESD classification at pins connected to
devices outside the ECU (IASG1 to
IASG5)
Human body model (HBM) HBM
AEC Q100-002
ESD classification at pins connected to
devices outside the ECU (K1 and K2)
Human body model (HBM) HBM
AEC Q100-002
General ESD classification for all other
pins
Human body model (HBM)
Charged device model (CDM) – no corner
pins
Charged device model (CDM) – corner
pins
HBM
AEC Q100-002
CDM
ESD STM5.3.1-1999
±3000 V
±2500 V
±1500
±500
±750
V
V
V
4929B–AUTO–01/07
7
4. Functional Range
Within the functional range, the ATA6264 works as specified. All voltages are referenced to the
ideal ground level of an ECU connected to the GNDA, GNDB and GNDD pins.
At the beginning of each specification table, supply voltage and temperature conditions are
described.
Table 4-1. Electrical Characteristics – Functional Range
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
Voltage on pins K30, K15,
1.1
USP
1.1a Voltage on pins K1, K2 –25 +40 V
Rate of supply voltage rise
1.2
(K30, K15, K1, K2)
1.3 Supply voltage EVZ –0.3 +40 V
1.4 Supply voltage VSAT –0.3 +14 V
Supply voltages VCORE,
1.5
VPERI
1.6 Supply voltage CP, CP-OUT –0.3 +50 V
1.7 Voltage on digital I/O pins –0.3 +5.5 V
Voltage on pins SVSAT,
1.8
SVCORE
Voltage on pins UZP,
ISENS, COMCOI,
1.9
COMCOO, COMSATO,
COMSATI, COMEVZO,
FBEVZ, IREF, VINT
Voltage on pins GEVZ,
1.10
OCEVZ
1.11 Voltage on pin SVPERI –0.3 +6 V
Voltage on pins IASGx
1.12
(x = 1 to 5)
Temperatures:
Operating ambient
temperature range
1.14
Operating junction
temperature range
Storage ambient/junction
temperature range
Thermal resistance junction
1.15
ambient
Substrate current which can
be drawn without
1.16
disturbances to upper
defined blocks/functions
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. No substrate current occurs at pins K1, K2 down to V
(1)
, VK2 > –25V
K1
–0.3 +40 V
–0.3 +5.5 V
–1.0 +40 V
–0.3 +5.5 V
–0.3 +10 V
Voltage
necessary to
drive –40 mA
stored in 20 µH
– 40
– 40
– 55
–40 mA
+ 90
+150
+105
50 V/µs
40 V
°C
°C
°C
60 K/W
8
ATA6264 [Preliminary]
4929B–AUTO–01/07
4.1 Protection Against Substrate Currents
Due to the fact that the ATA6264 is connected to the wiring harness and to components outside
of the ECU, negative voltages at the following pins might occur:
• IASG interface: IASG1, IASG2, IASG3, IASG4, IASG5
• USP comparator: USP
If substrate currents occur, it is guaranteed by design that no disturbance and malfunction of the
following blocks and functions will happen:
• No disturbance of RESET block.
• No voltage changes of any regulators outside of their tolerances.
• No impact on digital circuitry (for example, changes of latches, status register, etc.)
• No latch up of any circuitry
ATA6264 [Preliminary]
4929B–AUTO–01/07
9
5. Supply Currents
A minimum current has to flow into each pin for proper functioning of the IC.
Table 5-1. Electrical Characteristics – Supply currents
No. Parameters Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
2.1 Supply current at K30
2.1a Supply current at K30
Standby mode:
V
= 3V and KEYLATCH = OFF
K15
Standby mode:
= 3V and KEYLATCH = OFF
V
K15
0V = V
18V < V
Startup mode: 0V < V
2.1b Supply current at K30
2.1c Supply current at K30
2.1d Supply current at K30
V
> 4.15V or KEYLATCH = ON,
K15
V
= 0V, CCP = 47 nF
EVZ
Startup mode:
> 4.15V or KEYLATCH = ON
V
K15
V
= 0V, CCP = 47 nF
EVZ
Normal mode:
V
> V
EVZ
K30
0V < V
, V
K15
18V < V
> 4V or
KEYLATCH = ON, SVCORE open,
AMUX Measurement K30 active
Normal mode: 18V < V
V
> V
, V
2.1e Supply current at K30
EVZ
K30
KEYLATCH = ON, SVCORE open,
> 4.15V or
K15
AMUX Measurement K30 active
Startup mode: 0V < V
2.2 Supply current at EVZ
V
V
SAT
K30
= V
>5V, V
= V
PERI
CORE
> 4.15V, SVCORE
K15
and SVSAT open
Normal mode: 0V < V
2.2a Supply current at EVZ
and V
V
PERI
Threshold, V
= 10V, V
V
SAT
> 4.15V, SVCORE and
V
K15
CORE
EVZ
K30
> Reset
> V
> 5V,
SVSAT open, AMUX Measurement
EVZ active
Autonomous mode:
0V < V
EVZ
= 40V, V
> Reset Threshold, V
2.2b Supply current at EVZ
V
= 10V, V
SAT
< 3V, SVCORE and SVSAT
V
K15
< 3.85V,
K30
open, AMUX Measurement EVZ
active
2.3 Supply current at VSAT
Supply current at
2.4
VPERI
Supply current at
2.5
VCORE
0V < V
AMUX measurement VSAT active
0V < V
measurement VPERI active
0V < V
measurement VCORE active
= 14V, SVPERI open,
SAT
= 5.3V, AMUX
PERI
= 5.3V, AMUX
CORE
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
= 0V,
K30
PERI
K30
K30
K30
K30
K30
K30
EVZ
EVZ
,
and V
EVZ
= 18V,
= 40V,
= 18V,
= 40V
= 18V,
= 40V,
= 40V,
= 40V,
CORE
> V
K30
,
K30
K30
K30 I
K30 I
K30
K30
EVZ
EVZ
EVZ
VSAT
VPERI
VCORE
I
K30
I
K30
K30
K30
I
K30
I
K30
I
EVZ
I
EVZ
I
EVZ
I
VSAT
I
VPERI
I
VCORE
050µAA
05mAA
07mAA
010mAA
06.5mAA
010mAA
05mAA
06mAA
010mAA
01.5mAA
–0.2 2.2 mA A
–0.45 1 mA A
10
ATA6264 [Preliminary]
4929B–AUTO–01/07
5.1 Discharger Circuit
e
Applications using the ATA6264 usually use a reverse polarity protection diode (D1 in Figure
5-1) in the power supply to prevent any damage if the wrong polarity is applied to V
nately, this method includes some risk as can be seen in the following description:
ATA6264 [Preliminary]
. Unfortu-
K30
During Standby mode (V
I
. Any peaks on the supply voltage (V
K30
K15
capacitor (C1). D1 prevents the capacitor from being discharged via the power supply and the
very small quiescent current via the IC can also be neglected. This means that during long periods of Standby mode, the IC’s supply voltage could increase continuously until finally the
maximum supply voltage limit would be exceeded and the IC could be damaged. ATA6264
therefore features a discharger circuit which avoids such unwanted effects. If V
threshold value of approximately 26.8V, the blocking capacitor is discharged via an integrated
resistor until V
again falls below the threshold.
K30
Figure 5-1. Discharger Circuit
5.2 Initial Programming of the ATA6264
The ATA6264 supports different output voltages at the VSAT, VPERI and the VCORE regulators. In addition, different modes at the ISO9141 interfaces can be adjusted at the initial
programming (IP). The memory cells are one-time programmable (OTP) and cannot be changed
after the IP (default values are “0”). In general, the IP is done after mounting the ATA6264 on the
PCB with an in-circuit tester. The programming voltage of 11.7V has to be applied on pin VSAT.
It is also possible to use the VSAT regulator as the programming voltage because VSAT is programmed to 11.7V (±0.5V) as long as the Test mode is entered and the lock bit is not set. To
ensure proper programming of the ATA6264, at least a 10-µF electrolytic cap and a 100-nF
ceramic cap have to be applied at pin VSAT.
< 3V and KEYLATCH = OFF) the IC consumes only a low current,
in Figure 5-1) will gradually charge the blocking
Pulse
exceeds a
K30
K30
C18 kΩ
26.8V
D1
V
Batt
V
Puls
4929B–AUTO–01/07
11
The following settings can be made at the initial programming:
MSBit LSBit
VR1 VR2 VR3 VR4 EXT ISO/LIN Parity Lock bit
Table 5-2. Initial Programming Settings
VR1 VR2 VR3 VR4 VCORE VPERI VSAT
0 0 0 0 All regulators deactivated (default)
0 0 0 1 1.88V 3.3V 7.8V
0 0 1 0 1.88V 3.3V 9.1V
0 0 1 1 1.88V 3.3V 10.4V
0 1 0 0 2.5V 3.3V 7.8V
0 1 0 1 2.5V 3.3V 9.1V
0 1 1 0 2.5V 3.3V 10.4V
0 1 1 1 1.88V 5V 7.8V
1 0 0 0 1.88V 5V 9.1V
1 0 0 1 1.88V 5V 10.4V
1 0 1 0 2.5V 5V 7.8V
1 0 1 1 2.5V 5V 9.1V
1 1 0 0 2.5V 5V 10.4V
1 1 0 1 5V 5V 7.8V
1 1 1 0 5V 5V 9.1V
1 1 1 1 5V 5V 10.4V
12
Set to 0 Set to 1
EXT No external transistor at VPERI (default) External transistor at VPERI applied
Set to 0 Set to 1
ISO/LIN ISO9141 mode is activated at K1 (default) LIN mode is activated at K1
ATA6264 [Preliminary]
4929B–AUTO–01/07
ATA6264 [Preliminary]
The IP data is valid only if the parity is odd. If the IP data is not valid, or if the lock bit is not set,
the programming will not be executed.
Figure 5-2. Programming Sequence
Contact pins RESQ, RESQ2
TxD1, TxD2, SSQ, MOSI,
SCLK, VPERI, K15, K30
Apply 12V at K15, K30 and5V
Set RESQ and TxD1 to GND
and RESQ2 and TxD2 to 5V
Transmit IP command A9xx(h)
via SPI to configure ATA6264
at VPERI
Transmit 5A5A(h) via SPI
to Enable Testmode
Wait until VSAT = 11.7V
Wait 1 ms
4929B–AUTO–01/07
Remove all voltages and pinloads
to get out of Test mode
13
5.3 Start-up and Power-down Procedure
E
The ATA6264 is powered via the pin K30 (battery voltage) and via a diode or a resistor it is connected to the ignition key line K15. In order to detect an interruption on one of these pins
correctly, resistors are implemented at these pins. Normally, the main supply pin of ATA6264 is
pin K30. In the case of a missing or a too-low voltage at pin K30, the whole IC is supplied from
the backup power supply capacitor hooked up to pin EVZ.
Figure 5-3. Block Diagram Start-up and Power-down Procedure
K15
V
= 3V to 4.15V
K15
(40 mV to 175mV Hysteresis)
Serial interface
(KEY - LATCH)
= 3.85V to 5V
V
K30
(50 mV to 150 mV Hysteresis)
V
= 6.1V to 8.1V (ON)
K30
(0.5V to 1V Hysteresis)
V
= 7.5V to 9V (ON)
EVZ
V
= 5.5V to 6.2V (OFF)
EVZ
V
= 6.77V to 7.2V
SAT
(200 mV to 500 mV Hysteresis)
K15GOOD
Comp
K30GOOD
Comp
CORESWAP
Comp
EVZGOOD
Comp
VSATGOOD
Comp
5V
IREF lost
signal
Power
sequencing
VEVZ
K30
CP
VK30
VEVZ
driver
IP
VCP
VSAT
driver
VEVZ
VPERI
driver
GEVZEVZEN
EVZ
SVSAT
VSAT
SVPER
VPERI
V
CP
V
EVZ
V
VSAT
V
VPERI
14
CORE_EN
V
= 1.25V to 1.7V
PERI
(50 mV to 150 mV Hysteresis)
Comp
ATA6264 [Preliminary]
driver
driver
VCP
VCP
K30
EVZ
SVCORE
VCORE
V
VCOR
4929B–AUTO–01/07
IP
VCORE
VCore
ATA6264 [Preliminary]
Depending on the initial programming of the ATA6264, the start-up procedure takes place in different phases.
5.3.1 Start-up Procedure if V
is Programmed to Be 5V or 2.5V
VCORE
Phase1: After switching on the ignition key, K15 voltage will apply at pin K15. If, in addition, the
voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The signal
K15GOOD can be replaced by the serial interface command KEYLATCH which can be set via
the serial interface.
Phase2: If V
is larger than 7.5V to 9V the VSAT regulator starts operating and the VCORE
EVZ
regulator will be enabled.
Phase3: After V
has reached 6.77V to 7.2V, the VPERI regulator starts working. The
VSAT
VCORE regulator starts operating depending on the charge pump voltage.
5.3.2 The Power-down Procedure Takes Place in Different Phases Phase1: If the ignition key is switched off, K15 voltage will vanish at pin K15. If the serial inter-
face command KEYLATCH is not set, the EVZ regulator stops working. The external charge
pump is still working because EVZ is above VSAT and the VSAT regulator is not in Perma-
nent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE
regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.
Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops to
low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on mode,
the external charge pump stops working and the VSAT voltage falls analog to the EVZ voltage. If
the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off. Depending
on the charge-pump voltage, the VCORE regulator stops working.
Phase3: When the voltage at the EVZ capacitor gets to be lower than 5.5V to 6.2V, VSAT is
switched off.
4929B–AUTO–01/07
15
Figure 5-4. Start-Up and Power-Down Procedure if V
V
K30
V
K15
3V to 4.15V3V to 4.15V
Programmed to Be 5V or 2.5V
VCORE
t
Threshold to enable
VCORE regulator
Threshold to start
VCORE regulator
5.3.3 Start-up Procedure if V
Phase1: After switching on the ignition key, the K15 voltage will appear at pin K15. If, in addi-
tion, the voltage at pin K30 is larger than 3.85V to 5V, the EVZ regulator will be enabled. The
signal K15GOOD can be replaced by the serial interface command KEYLATCH which can be
set by the serial interface.
V
GEVZ
V
EVZ
V
VSAT
V
VPERI
V
VCORE
Programmed to Be 1.88V
VCORE
7.5V to 9V
too low EVZ voltage
VSAT goes into On Mode
charge pump deactivated
6.77V to 7.2V 7V to 6.27V
t
t
5.5V to 6.2V
t
t
t
t
16
Phase2: If VEVZ is larger than 7.5V to 9V, the VSAT regulator starts operating.
Phase3: After VVSAT has reached 6.77V to 7.2V, the VPERI regulator starts working.
Phase4: If VVPERI is higher than 1.25V to 1.7V, the VCORE regulator will be enabled.
ATA6264 [Preliminary]
4929B–AUTO–01/07
ATA6264 [Preliminary]
5.3.4 The Power-down Procedure for V
Phase1: If the ignition key is switched off, the K15 voltage will vanish at pin K15. If the serial
interface command KEYLATCH is not set, the EVZ regulator stops working. The external charge
pump is still working because EVZ is above VSAT and the VSAT regulator is not in the Permanent-on mode. The charge-pump voltage still supplies the VSAT regulator and the VCORE
regulator. Because the EVZ regulator stops working, VCORE will be switched to EVZ.
Phase2: The EVZ capacitor will be discharged, and as soon as the voltage at pin VSAT drops
too low, the VSAT regulator will go into Permanent-on mode. If VSAT reaches Permanent-on
mode, the external charge pump stops working and the VSAT voltage falls analog to the EVZ
voltage. If the voltage at VSAT is below 6.27V to 7V, the VPERI regulator will be switched off.
Depending on the charge-pump voltage, the VCORE regulator stops working. The power
sequencing function for the VPERI regulator is still active and guarantees a maximum voltage
difference between VPERI and VCORE of 2.8V
Phase3: After VVPERI becomes lower than 1.1V to 1.55V, the VCORE regulator has to stop
working.
Phase4: When the voltage at the EVZ capacitor is lower than 5.5V to 6.2V, VSAT is switched
off.
Figure 5-5. Start-up and Power-down Procedure if V
V
K30
is Programmed to be 1.88V
VCORE
Programmed to Be 1.88V
VCORE
V
V
V
V
VCORE
V
K15
GEVZ
V
EVZ
VSAT
VPERI
7.5V to 9V
3V to 4.15V3V to 4.15V
too low EVZ voltage
VSAT goes into On Mode
charge pump deactivated
t
t
t
5.5V to 6.2V
t
7V to 6.27V6.77V to 7.2V
t
1.1V to 1.55V1.25V to 1.7V
t
t
4929B–AUTO–01/07
17
6. Power Supply Sequencing
(Only active when initial programming sets V
In order to meet the requirements of several dual-voltage-supply microcontrollers, a
power-sequencing function is implemented. The ATA6264 ensures that the voltage difference
VPERI – VCORE will not exceed 2.8V.
The voltage difference between VPERI and VCORE is monitored. In error cases, for example, if
the VCORE regulator does not start to work, the difference may rise above the 2.8V threshold. In
this case, the VPERI regulator is switched off before reaching this level and switched on again if
the voltage difference drops below a hysteresis value.
Figure 6-1. Example for Incorrect Ramp Up
V
VPERI
3.3V
= 1.88V and V
VCORE
VPERI
= 3.3V)
V
VCORE
1.88V
Not allowed area:
- V
V
VPERI
VCORE
>
2.8V
t
Necessary for operation:
t
V
= 0V to 40V, V
EVZ
= 3.7V to 5.47V
INT
Operating conditions of all other supply pins:
V
K30
, V
VSAT
, V
VPERI
and V
are within functional range limits, Tj = –40°C to 150°C
VCORE
Other pins:
As defined in Section 4. ”Functional Range” on page 8.
Table 6-1. Electrical Characteristics – Power Supply Sequencing
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
Maximum voltage difference
5.1
5.2a
5.2b
– V
V
VPERI
VCORE
Voltage level V
switch off VPERI regulator
Hysteresis for V
enable VPERI regulator
VPERI
VPERI
– V
– V
VCORE
VCORE
to
to
VPERI,
VCORE
VPERI,
VCORE
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
V
– V
V
– V
VPERI
VCORE
VPERI
VCORE
V
HYS
02.8VA
2.3 2.8 V A
100 mV A
18
ATA6264 [Preliminary]
4929B–AUTO–01/07
Figure 6-2. Block Diagram Power Supply Sequencing
E
ATA6264 [Preliminary]
K15
V
= 3V to 4.15V
K15
(40 mV to 175mV Hysteresis)
Serial interface
(KEY - LATCH)
= 3.85V to 5V
V
K30
(50 mV to 150 mV Hysteresis)
V
= 6.1V to 8.1V (ON)
K30
(0.5V to 1V Hysteresis)
V
= 7.5V to 9V (ON)
EVZ
V
= 5.5V to 6.2V (OFF)
EVZ
V
= 6.77V to 7.2V
SAT
(200 mV to 500 mV Hysteresis)
K15GOOD
Comp
K30GOOD
Comp
CORESWAP
Comp
EVZGOOD
Comp
VSATGOOD
Comp
5V
IREF lost
signal
IP
IP
VEVZ
VEVZ
driver
VSAT
driver
VPERI
driver
VK30
VCP
VEVZ
K30
CP
GEVZEVZEN
EVZ
SVSAT
VSAT
SVPER
VPERI
V
CP
V
EVZ
V
VSAT
V
VPERI
4929B–AUTO–01/07
Delta
< 2.8V
V
CORE
- Regulator
SVCORE
VCORE
V
VCOR
19
7. Charge Pump
To supply the VSAT and VCORE drivers, an external charge pump is provided. Both FETs
driven by the high charge pump voltage V
to ensure that they can be switched to a low-ohmic
CP
(1)
are
state. For correct function of the charge pump, an external capacitor of C = 47 nF has to be connected to pin SVSAT, and another of C = 100 nF to pin CP. A double diode has to be
implemented for proper function of the charge pump. An external series resistor is recommended to suppress spikes during switching of the SVSAT. The CP block is supplied by EVZ
and VSAT voltage and starts to operate as soon as the thresholds for VK15, K30 and EVZ are
achieved. An additional start-up circuitry is implemented to support the VSAT driver during the
start-up phase, thus enabling a reliable system startup.
The charge pump has an output CP-OUT to supply the external circuitry, and can be switched
via the SPI. It is capable of 250 µA.
Figure 7-1. Block Diagram Charge Pump
External circuit
CP-Out
Status
register
I = 1.4 mA
CP
Serial
interface
Note: 1. Connected to the drivers (see Figure 5-3)
EVZ
SVSATVSAT
REFREF
Status
register
20
ATA6264 [Preliminary]
4929B–AUTO–01/07
ATA6264 [Preliminary]
Necessary for operation:
V
= 5.5V to 40V or V
EVZ
Operating conditions of all other supply pins:
V
VSAT
, V
VPERI
and V
VCORE
Other pins:
As defined in Section 4. ”Functional Range” on page 8.
Table 7-1. Electrical Characteristics – Charge Pump
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
6.11 Supply current at pin CP
Time between wrong CP-OUT
6.12
voltage and valid data in status
register
Current limitation at pin
6.13
CP-OUT
Voltage difference VCP – V
6.14
for detecting wrong CP
Time between wrong CP
6.15
voltage and valid data in status
register
Voltage difference V
V
6.16
for detecting wrong
EVZ
CP-OUT
CP-OUT
6.17 Voltage at pin CP
6.18 Voltage at pin CP
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
CP off, supply of
internal circuitry
Note: Threshold is in
EVZ
the range of 5V to 7V
–
Note: Threshold is in
the range of 5V to 7V
= 5.5V to 40V,
V
EVZ
V
< V
K30
ICP+I
EVZ
CP_Out
(current consumption of
V
and V
SAT
be added)
= 5.5V to 40V,
V
EVZ
< V
V
K30
ICP+I
EVZ
CP_Out
(current consumption of
and V
V
SAT
be added)
= –100 µA
CORE
= –100 µA
CORE
= 5.5V to 40V, V
K30
> 3V, V
K15
= 3.7V to 5.47V
VINT
are within functional range limits, Tj = –40°C to 150°C
have to
have to
CP I
CP-OUT t
CP-OUT I
CP-OUT
CP V
CP t
CP-OUT V
CP V
CP V
CP
d
Diff
d
Diff
CP
CP
050µAA
050µsA
–0.8 –4.2 mA A
050µsA
V
+ 7 V
EVZ
V
+ 7 V
K30
5VA
5VA
+ 11 V A
EVZ
+ 11 V A
K30
4929B–AUTO–01/07
21
8. GKEY Function
The GKEY function is used to enable or disable the ECU via a powerless signal. If the voltage at
pin K15 is larger than 3V to 4.15V, the charge pump and the EVZ regulator (for correct EVZ
function, the K30 pin has to be connected to the battery) will start operating. If the K15 pin is
open, an internal pull-down resistor of approximately 220 kΩ discharges the pin. A logical con-
nection between the voltage at the K15 pin, a serial-interface-driven latch command, and the
K30 voltage determines the EVZ Enable signal. In order to achieve the Switch Function of the
GKEY function, a transformer has to be used.
Table 8-1. Overview of the Start-up Conditions
Note: 1. Less than the value shown in number 7.3 of Table 8-2 on page 23
Figure 8-1. Application With Low-current Switch (GKEY Function Used)
Serial-interface-
driven Latch
V
K30
Low
High
High
1)
2)
2)
V
K15
(Default: “0” = OFF) EVZ Regulator
x x Disabled
3)
High
xEnabled
x1Enabled
2. Greater than the value shown in number 7.3 of Table 8-2 on page 23
3. Greater than the value shown in number 7.1 of Table 8-2 on page 23
V
BATT
GKEY-
Logic
EVZ
K15
COMEVZO
K30
GEVZ
OCEVZ
GNDB
EVZ
FBEVZ
V
EVZ
22
ATA6264 [Preliminary]
4929B–AUTO–01/07
ATA6264 [Preliminary]
Figure 8-2. Application With High Current Switch (GKEY Function Not Used)
V
BATT
K15
GKEY-
Logic
EVZ
K30
GEVZ
OCEVZ
GNDB
EVZ
FBEVZ
COMEVZO
Necessary for operation:
= 3V to 40V, V
V
K15
= 3.85V to 40V
K30
Operating conditions of all other supply pins:
V
, V
, V
EVZ
SAT
PERI
and V
are within functional range limits, Tj = –40°C to 150°C
CORE
Other pins:
As defined in Section 4. ”Functional Range” on page 8.
V
EVZ
Table 8-2. Electrical Characteristics – GKEY Function
No. Parameters Test Conditions Pin Symbol Min Typ. Max. Unit Type*
Voltage level at K15 to enable
7.1
the EVZ regulator
Hysteresis at K15 to disable the
7.2
EVZ regulator
Voltage level at K30 to enable
7.3
the EVZ regulator
Hysteresis at K30 to disable the
7.4
EVZ regulator
7.5 Pull-down resistor at K15 K15 R
7.6 Pull-down resistor at K30 K30 R
7.7 Current at K15
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
4929B–AUTO–01/07
increasing,
V
K15
V
> 5V
K30
V
increasing,
K30
> 4.15V
V
K15
0V ≤ V
K15
≤ 40V,
AMUX measurement
EVZ active
K15 V
K15 V
K30 V
K30 V
K15 I
K15
K15
K30
K30
K15
K30
K15
34.15VA
40 175 mV A
3.85 5 V A
50 150 mV A
70 365 kΩ A
320 1700 kΩ A
01.1mAA
23
9. EVZ Step-up Regulator
A boost converter generates the supply voltage for energy reserve and firing capacitors in the
system. Using a voltage divider at pin FBEVZ, this voltage can be adjusted between 15V and
40V. Thus, high-voltage charged capacitors will be used to supply the whole system during the
stand-alone time (for example, broken K30 line after a crash). The step-up regulator has to start
running as soon as a certain threshold voltage at the K15 pin is exceeded. The regulator has to
stop running again if the voltage at the K15 pin falls below a voltage level (or voltage at pin K30
is missing, see Section 5.3 ”Start-up and Power-down Procedure” on page 14).
An inductor is PWM-switched by an external n-channel power FET with a fixed frequency of
100 kHz. A driver stage for the external FET is integrated into the ATA6264. The current limitation of the external FET is implemented by using an external resistor in series between the
source connection of the external FET and GND, sensing the voltage drop at this resistor via the
pins OCEVZ and GNDA.
The reference section provides a reference voltage of 1.24V for the regulation loop. An error
amplifier compares the reference voltage with the feedback signal, which is provided either from
two different serial-interface-programmable internal dividers (VEVZ1 = 22V, VEVZ2 = 31.5V) or
an external voltage divider network (VEVZExt). These dividers determine the output voltage
EVZ.
Figure 9-1. EVZ Regulator With External Divider
K30
Bandgap
reference
Sawtooth oscillator
+
+
-
Error
amp.
SPI
-
SPI
PWM
comp.
SPI
Max. duty-cycle
Low battery
Logic and
driver
EVZ
overvoltage
Overcurrent
GEVZ
OCEVZ
GNDA
EVZ
FBEVZ
COMEVZO
L
R
VZ1
R
C
VZ2
+
24
ATA6264 [Preliminary]
4929B–AUTO–01/07
Figure 9-2. EVZ Regulator With Internal Divider
ATA6264 [Preliminary]
K30
Bandgap
reference
Sawtooth oscillator
+
+
-
Error
amp.
SPI
-
SPI
PWM
comp.
SPI
Max. duty-cycle
Low battery
Logic and
driver
EVZ
overvoltage
Overcurrent
GEVZ
OCEVZ
GNDA
EVZ
FBEVZ
COMEVZO
L
C
+
A draft formula for calculating the EVZ voltage, which is programmed by the external voltage
divider network at pin FBEVZ, is:
R
+
VZ1RVZ2
V
EVZ
V
REF
--------------------------------
×=
R
VZ2
The pins EVZ and FBEVZ have to be shorted in applications without an external divider in order
to ensure a safe operation of the ATA6264 in the case of an EVZ-pin fault. If the voltage at pin
FBEVZ is larger than the voltage at pin EVZ, the ATA6264 switches the feedback path automatically to pin FBEVZ. The remaining voltage at FBEVZ causes the regulator to switch off.
The output of the error amplifier is compared with a periodic linear ramp of a saw-tooth generator by the PWM comparator. A logic signal with variable pulse width is generated, which controls
the PWM frequency of the external FET. A maximum duty cycle is determined by the duration of
the falling ramp of the saw-tooth oscillator. The saw-tooth generator is controlled by the internal
100-kHz oscillator.
4929B–AUTO–01/07
25
Loading...