– 1K: 128 x 8 or 64 x 16
– 2K: 256 x 8 or 128 x 16
– 4K: 512 x 8 or 256 x 16
• 3-wire Serial Interface
• 2 MHz Clock Rate (5V)
• Self-timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-lead PDIP, 8-lead JEDEC and EIAJ SOIC, and 8-lead TSSOP Packages
= 4.5V to 5.5V)
CC
= 2.7V to 5.5V)
CC
= 2.5V to 5.5V)
CC
= 1.8V to 5.5V)
CC
3-wire Serial
EEPROMs
1K (128 x 8 or 64 x 16)
2K (256 x 8 or 128 x 16)
Description
The AT93C46/56/66 provides 1024/2048/4096 bits of serial electrically erasable programmable read only memory (EEPROM) organized as 64/128/256 words of 16 bits
each, when the ORG pin is connected to VCC and 128/256/512 words of 8 bits each
when it is tied to ground. The device is optimized for use in many industrial and commercial applications where low power and low voltage operations are essential. The
AT93C46/56/66 is available in space-saving 8-lead PDIP and 8-lead JEDEC and EIAJ
SOIC packages.
(continued)
Pin Configurations
CS
SK
DI
DO
1
2
3
4
8-lead TSSOP
1
2
3
4
8-lead PDIP
1
2
3
4
8-lead SOIC
VCC
8
DC
7
ORG
6
GND
5
VCC
8
DC
7
ORG
6
GND
5
8
VCC
7
DC
6
ORG
5
GND
Pin NameFunction
CSChip Select
SKSerial Data Clock
DISerial Data Input
DOSerial Data Output
GNDGround
VCCPower Supply
ORGInternal Organization
DCDon’t Connect
8-lead SOIC
Rotated (R)
(1K JEDEC Only)
DC
VCC
CS
SK
1
2
3
4
ORG
8
GND
7
DO
6
DI
5
CS
SK
DI
DO
CS
SK
DI
DO
4K (512 x 8 or 256 x 16)
AT93C46
AT93C56
AT93C66
Rev. 0172O–08/01
1
The AT93C46/56/66 is enabled through the Chip Select pin (CS), and accessed via a
3-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is completely selftimed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is brought
“high” following the initiation of a WRITE cycle, the DO pin outputs the READY/BUSY
status of the part.
The AT93C46 is available in 4.5V to 5.5V, 2.7V to 5.5V, 2.5V to 5.5V, and 1.8V to 5.5V
versions. The AT93C56/66 is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V
versions.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
Block Diagram
Notes: 1. When the ORG pin is connected to VCC, the x 16 organization is selected. When it is connected to ground, the x 8 orga-
nization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of
the internal 1 Meg ohm pullup, then the x 16 organization is selected. The feature is not available on the 1.8V devices.
2. For the AT93C46, if x 16 organization is the mode of choice and Pin 6 (ORG) is left unconnected, Atmel recommends
using the AT93C46A device. For more details, see the AT93C46A datasheet.
2
AT93C46/56/66
0172O–08/01
AT93C46/56/66
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
SymbolTest ConditionsMaxUnitsConditions
C
OUT
C
IN
Output Capacitance (DO)5pFV
OUT
= 0V
Input Capacitance (CS, SK, DI)5pFVIN = 0V
Note:1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +1.8V to +5.5V,
= 0°C to +70°C, VCC = +1.8V to +5.5V (unless otherwise noted).
T
AC
SymbolParameterTest ConditionMinTypMaxUnit
V
CC1
V
CC2
V
CC3
V
CC4
I
CC
I
SB1
I
SB2
I
SB3
I
SB4
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
(1)
V
IL2
(1)
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note:1. V
Supply Voltage1.85.5V
Supply Voltage2.55.5V
Supply Voltage2.75.5V
Supply Voltage4.55.5V
READ at 1.0 MHz0.52.0mA
Supply CurrentVCC = 5.0V
WRITE at 1.0 MHz0.52.0mA
Standby CurrentVCC = 1.8VCS = 0V00.1µA
Standby CurrentVCC = 2.5VCS = 0V6.010.0µA
Standby CurrentVCC = 2.7VCS = 0V6.010.0µA
Standby CurrentVCC = 5.0VCS = 0V1730µA
Input LeakageVIN = 0V to VCC 0.11.0µA
Output LeakageVIN = 0V to VCC 0.11.0µA
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Output High Voltage
min and VIH max are reference only and are not tested.
IL
4.5V ≤ VCC ≤ 5.5V
1.8V ≤ V
4.5V ≤ V
≤ 2.7V
CC
≤ 5.5V
CC
1.8V ≤ VCC ≤ 2.7V
I
= 2.1 mA0.4V
OL
I
= -0.4 mA2.4V
OH
= 0.15 mA0.2V
I
OL
IOH = -100 µAVCC - 0.2V
-0.6
2.0
-0.6
x 0.7
V
CC
0.8
V
+ 1
CC
V
x 0.3
CC
+ 1
V
CC
V
V
0172O–08/01
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = As Specified,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
SymbolParameterTest ConditionMinTypMaxUnits
≤ V
f
t
t
t
t
t
t
t
t
t
t
SK
SKH
SKL
CS
CSS
DIS
CSH
DIH
PD1
PD0
SV
4.5V
SK Clock
Frequency
2.7V
2.5V
1.8V
4.5V
SK High Time
2.7V
2.5V
1.8V
4.5V
SK Low Time
2.7V
2.5V
1.8V
4.5V
Minimum CS
Low Time
2.7V
2.5V
1.8V
CS Setup TimeRelative to SK
DI Setup TimeRelative to SK
CS Hold TimeRelative to SK0ns
DI Hold TimeRelative to SK
Output Delay to ‘1’AC Test
Output Delay to ‘0’AC Test
CS to Status ValidAC Test
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
4.5V
2.7V
2.5V
1.8V
4.5V
2.7V
2.5V
1.8V
4.5V
2.7V
2.5V
1.8V
4.5V
2.7V
2.5V
1.8V
4.5V
2.7V
2.5V
1.8V
4.5V
2.7V
2.5V
1.8V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
≤ V
4.5V ≤ VCC ≤ 5.5V
t
DF
t
WP
Endurance
CS to DO in High
Impedance
Write Cycle Time
(1)
5.0V, 25°C, Page Mode1MWrite Cycles
AC Test
CS = V
≤ V
2.7V
2.5V
IL
1.8V
4.5V
≤ V
≤ V
≤ V
Note:1. This parameter is characterized and is not 100% tested.
0
0
0
0
250
250
500
1000
250
250
500
1000
250
250
500
1000
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V3ms
CC
50
50
100
200
100
100
200
400
100
100
200
400
2
1
0.5
0.25
250
250
500
1000
250
250
500
1000
250
250
500
1000
100
100
200
400
10ms
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
AT93C46/56/66
0172O–08/01
Instruction Set for the AT93C46
AT93C46/56/66
Op
InstructionSB
Code
READ110A6 - A
AddressData
0
A5 - A
0
Commentsx 8x 16x 8x 16
Reads data stored in memory, at
specified address.
EWEN10011XXXXX11XXXXWrite enable must precede all
programming modes.
ERASE111A
WRITE101A
- A
6
0
- A
6
0
A5 - A
A5 - A
0
0
D7 - D
0
D
- D
15
Erase memory location An - A0.
Writes memory location An - A0.
0
ERAL10010XXXXX10XXXXErases all memory locations. Valid
= 4.5V to 5.5V.
CC
= 4.5V to 5.5V.
CC
WRAL10001XXXXX01XXXXD
only at V
- D
7
0
D
15
- D
Writes all memory locations. Valid
0
only at V
EWDS10000XXXXX00XXXXDisables all programming
instructions.
0172O–08/01
5
Functional
Description
The AT93C46/56/66 is accessed via a simple and versatile 3-wire serial communication
interface. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a Start Bit
(logic “1”) followed by the appropriate Op Code and the desired memory Address
location.
READ (READ): The Read (READ) instruction contains the Address code for the memory location to be read. After the instruction and address are decoded, data from the
selected memory location is available at the serial output pin DO. Output data changes
are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the
Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable
(EWEN) instruction must be executed first before any programming instructions can be
carried out. Please note that once in the Erase/Write Enable state, programming
remains enabled until an Erase/Write Disable (EWDS) instruction is executed or V
CC
power is removed from the part.
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified
memory location to the logical “1” state. The self-timed erase cycle starts once the
ERASE instruction and address are decoded. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
CS
A logic “1” at pin DO indicates that the selected memory location has been erased, and
the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be
written into the specified memory location. The self-timed programming cycle, t
, starts
WP
after the last bit of data is received at serial data input pin DI. The DO pin outputs the
READY/BUSY status of the part if CS is brought high after being kept low for a minimum
of 250 ns (t
). A logic “0” at DO indicates that programming is still in progress. A logic
CS
“1” indicates that the memory location at the specified address has been written with the
data pattern contained in the instruction and the part is ready for further instructions. A
READY/BUSY status cannot be obtained if the CS is brought high after the end of
the self-timed programming cycle, t
WP
.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the mem-
ory array to the logic “1” state and is primarily used for testing purposes. The DO pin
outputs the READY/BUSY status of the part if CS is brought high after being kept low for
a minimum of 250 ns (t
). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
CS
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations
with the data patterns specified in the instruction. The DO pin outputs the READY/BUSY
status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
The WRAL instruction is valid only at V
= 5.0V ± 10%.
CC
CS
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the
Erase/Write Disable (EWDS) instruction disables all programming modes and should be
executed after all programming operations. The operation of the READ instruction is
independent of both the EWEN and EWDS instructions and can be executed at any
time.
).
).
6
AT93C46/56/66
0172O–08/01
Timing Diagrams
Synchronous Data Timing
AT93C46/56/66
Note:1. This is the minimum SK period.
Organization Key for Timing Diagrams
AT93C46 (1K)AT93C56 (2K)AT93C66 (4K)
I/O
A
N
D
N
Notes: 1. A
is a DON’T CARE value, but the extra clock is required.
8
is a DON’T CARE value, but the extra clock is required.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
ATME L® is the registered trademark of Atmel.
Other terms and product names may be the trademarks of others.
Printed on recycled paper.
0172O–08/01/xM
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