How it Works
ATMEL
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AT93C46D
User Manual
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ATMEL AT93C46D User Manual

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Features

• Low-voltage and Standard-voltage Operation
– 1.8 (V
= 1.8V to 5.5V)
CC
• User-selectable Internal Organization
– 1K: 128 x 8 or 64 x 16
• Three-wire Serial Interface
• Self-timed Write Cycle (5 ms max)
• High Reliability
– Endurance: 1 Million Write Cycles – Data Retention: 100 Years
• 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini-MAP (MLP 2x3), 8-lead
TSSOP and 8-ball dBGA2 Packages
• Die Sales: Wafer Form, Tape and Reel, and Bumped Wafers

Description

The AT93C46D provides 1024 bits of serial electrically erasable programmable read­only memory (EEPROM), organized as 64 words of 16 bits each (when the ORG pin is connected to VCC), and 128 words of 8 bits each (when the ORG pin is tied to ground). The device is optimized for use in many industrial and commercial applica­tions where low-power and low-voltage operations are essential. The AT93C46D is available in space-saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Thin mini­MAP (MLP 2x3), 8-lead TSSOP, and 8-lead dBGA2 packages.
The AT93C46D is enabled through the Chip Select pin (CS) and accessed via a three-wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock (SK). Upon receiving a Read instruction at DI, the address is decoded and the data is clocked out serially on the DO pin. The Write cycle is completely self-timed, and no separate Erase cycle is required before Write. The Write cycle is only enabled when the part is in the Erase/Write Enable state. When CS is brought high following the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part.
Three-wire Serial EEPROM
1K (128 x 8 or 64 x 16)
AT93C46D
Preliminary
The AT93C46D is available in 1.8 (1.8V to 5.5V) version.
Table 0-1. Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
ORG Internal Organization
NC No Connect
CS SK
DI
DO
CS SK
DI
DO
8-lead SOIC
1 2 3 4
8-lead PDIP
1 2 3 4
CS SK
DI
DO
8 7 6 5
8 7 6 5
8-lead dBGA2
8
VCC NC ORG GND
VCC NC ORG GND
8-lead TSSOP
1 2 3 4
VCC
7
NC
6
ORG
5
GND
Bottom View
8-lead Ultra Thin mini-MAP (MLP 2x3)
8
VCC
7
NC
6
ORG
5
GND
Bottom View
VCC
8
NC
7
ORG
6
GND
5
1
CS
2
SK
3
D1
4
D0
1
CS
2
SK
3
DI
4
DO
5193E–SEEPR–11/07

1. Absolute Maximum Ratings*

Operating Temperature......................................−55°C to +125°C
Storage Temperature .........................................−65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................................ −1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1-1. Block Diagram
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability
Notes: 1. When the ORG pin is connected to VCC, the “x 16” organization is selected. When it is con-
nected to ground, the “x 8” organization is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1 Meg ohm pullup, then the “x 16” organization is selected.
2. For the AT93C46D, if the “x 16” organization is the mode of choice and pin 6 (ORG) is left unconnected, Atmel AT93C46E datasheet.
2
AT93C46D [Preliminary]
®
recommends using AT93C46E device. For more details, see the
5193E–SEEPR–11/07
AT93C46D [Preliminary]
Table 1-1. Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V (unless otherwise noted)
Symbol Test Conditions Max Units Conditions
C
OUT
C
IN
Output Capacitance (DO) 5 pF V
OUT
= 0V
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
Note: 1. This parameter is characterized and is not 100% tested.
Table 1-2. DC Characteristics Applicable over recommended operating range from: T
Symbol Parameter Test Condition Min Typ Max Unit
V
CC1
V
CC2
V
CC3
I
CC
I
SB1
I
SB2
I
SB3
I
IL
I
OL
(1)
V
IL1
(1)
V
IH1
(1)
V
IL2
(1)
V
IH2
V
OL1
V
OH1
V
OL2
V
OH2
Note: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 1.8 5.5 V
Supply Voltage 2.7 5.5 V
Supply Voltage 4.5 5.5 V
Supply Current VCC = 5.0V
Standby Current VCC = 1.8V CS = 0V 0.4 1.0 µA
Standby Current VCC = 2.7V CS = 0V 6.0 10.0 µA
Standby Current VCC = 5.0V CS = 0V 10.0 15.0 µA
Input Leakage VIN = 0V to VCC 0.1 1.0 µA
Output Leakage VIN = 0V to VCC 0.1 1.0 µA
Input Low Voltage
2.7V ≤ V
Input High Voltage 2.0 VCC + 1
Input Low Voltage
1.8V ≤ V
Input High Voltage VCC x 0.7 VCC + 1
Output Low Voltage
2.7V ≤ VCC ≤ 5.5V
Output High Voltage IOH = −0.4 mA 2.4 V
Output Low Voltage
Output High Voltage IOH = −100 µAV
1.8V ≤ V
≤ 2.7V
CC
= −40°C to +85°C, VCC = +1.8V to +5.5V (unless otherwise noted)
AI
READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
−0.6 0.8
≤ 5.5V
CC
≤ 2.7V
−0.6 V
CC
IOL = 2.1 mA 0.4 V
I
= 0.15 mA 0.2 V
OL
– 0.2 V
CC
CC
x 0.3
V
V
5193E–SEEPR–11/07
3
Table 1-3. AC Characteristics
Applicable over recommended operating range from T
= −40°C to + 85°C, VCC = +2.7V to +5.5V,
AI
CL = 1 TTL Gate and 100 pF (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
f
SK
t
SKH
t
SKL
t
CS
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
WP
Endurance
(1)
SK Clock Frequency
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
SK High Time
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
SK Low Time
2.7V ≤ V
1.8V ≤ V
Minimum CS Low Time
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
CS Setup Time Relative to SK
DI Setup Time Relative to SK
CS Hold Time Relative to SK 0 ns
DI Hold Time Relative to SK
Output Delay to “1” AC Test
Output Delay to “0” AC Test
CS to Status Valid AC Test
CS to DO in High Impedance
AC Test CS = V
Write Cycle Time
5.0V, 25°C 1M Write Cycles
CC
CC CC
CC
CC CC
CC
CC CC
CC
CC CC
IL
≤ 5.5V ≤ 5.5V ≤ 5.5V
≤ 5.5V ≤ 5.5V ≤ 5.5V
≤ 5.5V ≤ 5.5V ≤ 5.5V
≤ 5.5V ≤ 5.5V ≤ 5.5V
Note: 1. This parameter is ensured by characterization.
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
4.5V ≤ V
2.7V ≤ V
1.8V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
1.8V ≤ V
1.8V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V 0.1 3 ms
CC
0 0 0
250 250
1000
250 250
1000
250 250
1000
50 50
200
100 100 400
100 100 400
2 1
0.25
250 250
1000
250 250
1000
250 250
1000
100 150 400
5ms
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
AT93C46D [Preliminary]
5193E–SEEPR–11/07
Table 1-4. Instruction Set for the AT93C46D
AT93C46D [Preliminary]
Op
Instruction SB
Code
READ 1 10 A6 – A
EWEN 1 00 11XXXXX 11XXXX
ERASE 1 11 A6 – A
WRITE 1 01 A6 – A
ERAL 1 00 10XXXXX 10XXXX
WRAL 1 00 01XXXXX 01XXXX D7 – D
Address Data
0
0
0
A5 – A
A5 – A
A5 – A
0
0
0
D7 – D
0
0
Commentsx 8 x 16 x 8 x 16
Reads data stored in memory, at specified address
Write enable must precede all programming modes
Erases memory location An – A
D
15
– D
Writes memory location An – A
0
0
0
Erases all memory locations. Valid only at V
D
– D
15
Writes all memory locations. Valid
0
only at VCC = 4.5V to 5.5V
= 4.5V to 5.5V
CC
EWDS 1 00 00XXXXX 00XXXX Disables all programming instructions
Note: The Xs in the address field represent DON’T CARE values and must be clocked.

2. Functional Description

The AT93C46D is accessed via a simple and versatile three-wire serial communication inter­face. Device operation is controlled by seven instructions issued by the host processor. A valid instruction starts with a rising edge of CS and consists of a start bit (logic “1”) followed by the appropriate op code and the desired memory address location.
READ (READ): The Read (READ) instruction contains the address code for the memory loca­tion to be read. After the instruction and address are decoded, data from the selected memory location is available at the serial output pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a dummy bit (logic “0”) precedes the 8- or 16-bit data output string.
ERASE/WRITE ENABLE (EWEN): To assure data integrity, the part automatically goes into the Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable (EWEN) instruction must be executed first before any programming instructions can be carried out. Please note that once in the EWEN state, programming remains enabled until an EWDS instruc­tion is executed or V
power is removed from the part.
CC
ERASE (ERASE): The Erase (ERASE) instruction programs all bits in the specified memory location to the logical “1” state. The self-timed erase cycle starts once the Erase instruction and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
). A logic “1” at pin DO indicates that the
CS
selected memory location has been erased and the part is ready for another instruction.
WRITE (WRITE): The Write (WRITE) instruction contains the 8 or 16 bits of data to be written into the specified memory location. The self-timed programming cycle t
starts after the last bit
WP
of data is received at serial data input pin DI. The DO pin outputs the Read/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
). A logic “0” at DO
CS
indicates that programming is still in progress. A logic “1” indicates that the memory location at the specified address has been written with the data pattern contained in the instruction and the
5193E–SEEPR–11/07
5
part is ready for further instructions. A Ready/Busy status cannot be obtained if the CS is brought high after the end of the self-timed programming cycle tWP.
ERASE ALL (ERAL): The Erase All (ERAL) instruction programs every bit in the memory array to the logic “1” state and is primarily used for testing purposes. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t
). The ERAL instruction is valid only at VCC = 5.0V ± 10%.
CS
WRITE ALL (WRAL): The Write All (WRAL) instruction programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the Ready/Busy status of the part if CS is brought high after being kept low for a minimum of 250 ns (t valid only at V
= 5.0V ± 10%.
CC
). The WRAL instruction is
CS
ERASE/WRITE DISABLE (EWDS): To protect against accidental data disturb, the Erase/Write Disable (EWDS) instruction disables all programming modes and should be executed after all programming operations. The operation of the Read instruction is independent of both the EWEN and EWDS instructions and can be executed at any time.
6
AT93C46D [Preliminary]
5193E–SEEPR–11/07

3. Timing Diagrams

Figure 3-1. Synchronous Data Timing
AT93C46D [Preliminary]
µs
Note: 1. This is the minimum SK period.
Table 3-1. Organization Key for Timing Diagrams
I/O
A
D
Figure 3-2. READ Timing
High Impedance
AT93C46D (1K)
x 8 x 16
N
N
A
6
D
7
A
5
D
15
t
CS
5193E–SEEPR–11/07
7
Figure 3-3. EWEN Timing
C
S
C
S
C
D
S
K
t
CS
DI
Figure 3-4. EWDS Timing
S
K
DI 1 0
Figure 3-5. WRITE Timing
S
001
000
11
...
t
CS
...
t
CS
SK
DI
HIGH IMPEDANCE
O
11
0A0D0
... ...
A
N
D
N
BUSY
t
WP
READY
8
AT93C46D [Preliminary]
5193E–SEEPR–11/07
AT93C46D [Preliminary]
C
S
D
C
D
E
Figure 3-6. WRAL Timing
(1)
S
K
DI
HIGH IMPEDANCE
O
1 0 0 1 ... D
Note: 1. Valid only at VCC = 4.5V to 5.5V.
Figure 3-7. ERASE Timing
S
t
CS
... D00
N
BUSY
READY
t
WP
t
CS
CHECK
STATUS
STANDBY
SK
DI A
HIGH IMPEDANCE
O
1 1 ...1
N
A
N-1AN-2
A0
t
SV
BUSY
READY
t
WP
t
DF
HIGH IMPEDANC
9
5193E–SEEPR–11/07
Figure 3-8. ERAL Timing
C
D
E
(1)
t
CS
S
SK
DI 1 1000
HIGH IMPEDANCE
O
Note: 1. Valid only at VCC = 4.5V to 5.5V.
READY
STANDBY
t
DF
HIGH IMPEDANC
CHECK STATUS
t
SV
BUSY
t
WP
10
AT93C46D [Preliminary]
5193E–SEEPR–11/07
AT93C46D [Preliminary]

4. AT93C46D Ordering Information

Ordering Code Voltage Package Operation Range
AT93C46D-PU (Bulk form only) 1.8 8P3
(1)
AT93C46DN-SH-B AT93C46DN-SH-T AT93C46D-TH-B AT93C46D-TH-T AT93C46DY6-YH-T AT93C46DU3-UU-T
AT93C46D-W-11
Notes: 1. “-B” denotes bulk
2. “-T” denotes tape and reel. SOIC = 4K per reel. TSSOP, Ultra Thin Mini MAP, and dBGA2 = 5K per reel.
3. Available in tape and reel, and wafer form; order as SL788 for inkless wafer form. Bumped die available upon request. Please contact Serial Interface Marketing.
(NiPdAu Lead finish) 1.8 8S1
(2)
(NiPdAu Lead finish) 1.8 8S1
(1)
(NiPdAu Lead finish) 1.8 8A2
(2)
(NiPdAu Lead finish) 1.8 8A2
(2)
(NiPdAu Lead finish) 1.8 8Y6
(2)
(3)
1.8 8U3-1
1.8 Die Sale
Lead-free/Halogen-free/
Industrial Temperature
(−40°C to 85°C)
Industrial
(−40°C to 85°C)
Package Type
8P3 8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP)
8U3-1 8-ball, Die Ball Grid Array Package (dBGA2)
8-lead, 2.00 mm x 3.00 mm Body, 0.50mm Pitch, Ultra-Thin Mini-MAO, Dual No Lead Package. (DFN), (MLP
8Y6
−1.8 Low Voltage (1.8V to 5.5V)
5193E–SEEPR–11/07
2x3mm)
Options
11

5. Part Marking Scheme

5.1 AT93C46D 8-PDIP

TOP MARK Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4 |---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L U Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
4 6 D 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---| | BOTTOM MARK
Pin 1 Indicator (Dot) No Bottom Mark

5.2 AT93C46D 8-SOIC

TOP MARK
|---|---|---|---|---|---|---|---| 8: 2008 2: 2012 :: : :::: :
A T M L H Y W W 9: 2009 3: 2013 :: : :::: ::
|---|---|---|---|---|---|---|---| 50 = Week 50
4 6 D 1 52 = Week 52
|---|---|---|---|---|---|---|---|
* Lot Number Lot Number to Use ALL Characters in Marking
|---|---|---|---|---|---|---|---| | Pin 1 Indicator (Dot) No Bottom Mark
Seal Year Y = SEAL YEAR WW = SEAL WEEK
| Seal Week 6: 2006 0: 2010 02 = Week 2
| | | 7: 2007 1: 2011 04 = Week 4
BOTTOM MARK
12
AT93C46D [Preliminary]
5193E–SEEPR–11/07
AT93C46D [Preliminary]

5.3 AT93C46D 8-TSSOP

TOP MARK
Pin 1 Indicator (Dot) Y = SEAL YEAR WW = SEAL WEEK
| 6: 2006 0: 2010 02 = Week 2 |---|---|---|---| 7: 2007 1: 2011 04 = Week 4
* H Y W W 8: 2008 2: 2012 :: : :::: :
|---|---|---|---|---| 9: 2009 3: 2013 :: : :::: ::
4 6 D 1 * 50 = Week 50
|---|---|---|---|---| 52 = Week 52
BOTTOM MARK
|---|---|---|---|---|---|---|
C 0 0 |---|---|---|---|---|---|---| A A A A A A A |---|---|---|---|---|---|---| <- Pin 1 Indicator

5.4 AT93C46D 8-Ultra Thin Mini MAP

TOP MARK
Y = YEAR OF ASSEMBLY
|---|---|---|
4 6 D XX = ATMEL LOT NUMBER TO COORESPOND WITH
|---|---|---| NSEB TRACE CODE LOG BOOK.
H 1 (e.g. XX = AA, AB, AC,...AX, AY, AZ)
|---|---|---|
Y X X
|---|---|---| Y = SEAL YEAR
* 6: 2006 0: 2010
| 7: 2007 1: 2011 Pin 1 Indicator (Dot) 8: 2008 2: 2012
9: 2009 3: 2013
5193E–SEEPR–11/07
13

5.5 AT93C46D dBGA2

TOP MARK
LINE 1-------> 46DU LINE 2-------> YMTC |<-- Pin 1 This Corner
Y = ONE DIGIT YEAR CODE 4: 2004 7: 2007 5: 2005 8: 2008 6: 2006 9: 2009
M = SEAL MONTH (USE ALPHA DESIGNATOR A-L)
A = JANUARY
B = FEBRUARY
" " """"""" J = OCTOBER
K = NOVEMBER L = DECEMBER
TC = TRACE CODE (ATMEL LOT NUMBERS TO CORRESPOND WITH ATK TRACE CODE LOG BOOK)
14
AT93C46D [Preliminary]
5193E–SEEPR–11/07

6. Package Information

8P3 - PDIP

AT93C46D [Preliminary]
D1
b3
4 PLCS
Top View
D
e
Side View
1
E
E1
N
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
b
b2
A2 A
SYMBOL
A 0.210 2 A2 0.115 0.130 0.195 b 0.014 0.018 0.022 5 b2 0.045 0.060 0.070 6 b3 0.030 0.039 0.045 6 c 0.008 0.010 0.014 D 0.355 0.365 0.400 3
L
D1 0.005 3 E 0.300 0.310 0.325 4 E1 0.240 0.250 0.280 3 e 0.100 BSC eA 0.300 BSC 4 L 0.115 0.130 0.150 2
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
5193E–SEEPR–11/07
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual In-line Package (PDIP)
DRAWING NO.
8P3
01/09/02
REV.
B
15

8S1 - JEDEC SOIC

Ø
E
1
N
TOP VIEW
C
E1
A
b
L
A1
e
D
SIDE VIEW
C
1
TOP VIEW
E
N
Ø
E1
L
END VIEW
e
D
SIDE VIEW
b
A
A1
SYMBOL
A 1.35 – 1.75 A1 0.10 – 0.25
b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.05 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27
θ 0˚ – 8˚
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
MAX
NOTE
16
Note:
These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc.
TITLE
1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906
R
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC)
AT93C46D [Preliminary]
DRAWING NO.
8S1 C
5193E–SEEPR–11/07
3/17/05
REV.

8A2 - TSSOP

Pin 1 indicator
this corner
AT93C46D [Preliminary]
123
N
Top View
b
e
D
Side View
A2
E1
E
L1
L
End View
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A
D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5
A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.304 e 0.65 BSC
L 0.45 0.60 0.75
L1 1.00 REF
MIN
NOM
MAX
NOTE
Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances,
5193E–SEEPR–11/07
datums, etc.
2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006 in) per side.
3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side.
4. Dimension b does b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm.
5. Dimension D and E1 to be determined at Datum Plane H.
2325 Orchard Parkway
R
San Jose, CA 95131
not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the
TITLE 8A2, 8-lead, 4.4 mm Body, Plastic
Thin Shrink Small Outline Package (TSSOP)
DRAWING NO.
8A2
5/30/02
REV.
B
17
8U3-1 – dBGA2
E
PIN 1 BALL PAD CORNER
Top View
PIN 1 BALL PAD CORNER
2
31
4
(d1)
d
8
67
5
e
(e1)
Bottem View
8 SOLDER BALLS
This drawing is for general information only.
1. Dimension 'b' is measured at maximum solder ball diameter.
2.
D
A
2
1.
b
A
1
A
Side View
COMMON DIMENSIONS
(Unit of Measure - mm)
SYMBOL
A 0.73 0.79 0.85 A1 0.09 0.14 0.19 A2 0.40 0.45 0.50 b 0.20 0.25 0.30 2 D 1.50 BSC E 2.0 BSC e 0.50 BSC e1 0.25 REF d 1.00 BSC d1 0.25 REF
MIN
NOM
MAX NOTE
18
1150 E. Cheyenne Mtn. Blvd.
R
Colorado Springs, CO 80906
TITLE
8U3-1, 8-ball, 1.50 x 2.00 mm Body, 0.50 mm pitch,
Small Die Ball Grid Array Package (dBGA2)
AT93C46D [Preliminary]
5/3/05
DRAWING NO.
PO8U3-1 B
5193E–SEEPR–11/07
REV.
8Y1 – MAP
AT93C46D [Preliminary]
PIN 1 INDEX AREA
A
D
2325 Orchard Parkway
R
San Jose, CA 95131
E
Top View
Side View
1
2
PIN 1 INDEX AREA
E1
8
7
A1
End View
A
SYMBOL
A – – 0.90
A1 0.00 – 0.05
D 4.70 4.90 5.10
E 2.80 3.00 3.20
D1 0.85 1.00 1.15
E1 0.85 1.00 1.15
b 0.25 0.30 0.35
e 0.65 TYP
L 0.50 0.60 0.70
b
Bottom View
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
NOM
TITLE
8Y1, 8-lead (4.90 x 3.00 mm Body) MSOP Array Package (MAP) Y1
3 4
D1
6 e 5
MAX
NOTE
DRAWING NO.
8Y1
L
2/28/03
REV.
C
5193E–SEEPR–11/07
19

7. Revision History

Doc. Rev. Date Comments
5193E 11/2007 Modified ‘max’ value in AC Characteristics table
5193D 8/2007
5193C 6/2007
5193C 3/2007 Corrected Figures 4 and 5.
5193B 2/2007 Added ‘Ultra Thin’ description to 8-lead Mini-MAP package.
5193A 1/2007 Initial document release.
Moved Pinout figure Added new feature for Die Sales Modified Ordering Information table layout Modified Park Marking Schemes
Updated to new template Added Product Markup Scheme Added Technical email contact
20
AT93C46D [Preliminary]
5193E–SEEPR–11/07
Headquarters International
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Sales Contact
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5193E–SEEPR–11/07
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