• x16 Organization Utilizing “No Connects” for Pins 6 and 7
• Low Voltage and Standard Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
• 3-Wire Serial Interface
• 2 MHz Clock Rate (5V) Compatibility
• Self-Timed Write Cycle (10 ms max)
• High Reliability
– Endurance: 1 Million Cycles
– Data Retention: 100 Years
• Automotive Grade and Extended Temperature Devices Available
• 8-Pin PDIP and JEDEC SOIC Packages
Description
The AT93C46B provides 1024 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The device is optimized for use in many industrial and commercial applications where low power and
low voltage operatio n ar e essential. The AT93C46B is avai la ble in sp ac e sa vi ng 8- pi n
PDIP and 8-pin JEDEC packages.
The AT93C46B is enabled through the Chip S elect pin (CS) , and accessed vi a a 3wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycle is compl etely selftimed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” fol lowing the in itiation of a WRITE cycle, the DO pin o utputs the
READY/BUSY status of the part.
The AT93C46B is available in 4.5V to 5.5V, 2.7V to 5.5V, and 2.5V to 5.5V versions.
AT93C46B
3-Wire
Serial
2
E
PROMs
1K (64 x 16)
AT93C46B
Pin Configuration
Pin NameFunction
CSChip Select
SKSerial Data Clock
DISerial Data Input
DOSerial Data Output
GNDGround
V
CC
NCNo Connect
Power Supply
CS
SK
DI
DO
CS
SK
DI
SO
8-Pin PDIP
1
2
3
4
8-Pin SOIC
1
2
3
4
8
VCC
7
NC
6
NC
5
GND
8
VCC
7
NC
6
NC
5
GND
0917A-A–11/97
1
Absolute Maximum Ratings*
Operating Temperature.........................-55°C to +125°C
Storage Temperature............................-65°C to +150°C
Voltage on Any Pin
with Respect to Ground........................... -1.0V to +7.0V
Maximum Operating Voltage.................................6.25V
DC Output Current ..............................................5.0 mA
Block Diagram
*NOTICE:Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the dev ice . This is a s tress rating only an d
functional oper ation of the de vice at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions f or e xtended periods ma y af fect de vice
reliability .
2
AT93C46B
AT93C46B
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test ConditionsMaxUnitsConditions
C
C
Output Capacitance (DO )5pFV
OUT
Input Capacitance (CS, SK, DI)5pFVIN = 0V
IN
OUT
= 0V
Note:1. This parameter is characterized and is not 100% tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,
= 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).
Note:1. VIL and VIH max are reference only and are not tested.
-0.1
2.0
0.0
x 0.7
V
CC
I
= 2.1 mA0.4V
OL
I
= -0.4 mA2.4V
OH
I
= 0.15 mA0.2V
OL
I
= -100 µAV
OH
- 0.2V
CC
0.8
+ 1
V
CC
V
x 0.3
CC
+ 1
V
CC
µ
A
µ
A
µ
A
µ
A
µ
A
V
V
3
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
= 1 TTL Gate and 100 pF (unless otherwise noted).
C
L
SymbolParameterTest ConditionMinTypMaxUnits
IL
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
2.7V ≤ V
2.5V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
≤ 5.5V
CC
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
2.5V ≤ V
≤ 5.5V
CC
≤ 5.5V
CC
0
0
0
250
250
500
250
250
500
250
250
500
50
50
100
100
100
200
100
100
200
2
1
0.5
250
250
500
250
250
500
250
250
500
100
100
200
0.110ms
4.5V ≤ V
= 5.0V, Page Mode1MCycles
CC
≤ 5.5V1ms
CC
MHz
4.5V ≤ V
f
SK
SK Clock Frequency
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
t
SKH
SK High Time
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
t
SKL
SK Low Time
2.7V ≤ V
2.5V ≤ V
4.5V ≤ V
t
CS
Minimum CS Low Time
2.7V ≤ V
2.5V ≤ V
t
CSS
t
DIS
t
CSH
t
DIH
t
PD1
t
PD0
t
SV
t
DF
t
WP
CS Setup TimeRelative to SK
DI Setup TimeRelative to SK
CS Hold TimeRelative to SK0ns
DI Hold TimeRelative to SK
Output Delay to ‘1’AC Test
Output Delay to ‘0’AC Test
CS to Status ValidAC Test
CS to DO in High Impedance
AC Test
CS = V
Write Cycle Time
Endurance25°C, V
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4
AT93C46B
Instruction Set for the AT93C46B
InstructionSBOp Code
AT93C46B
Address
(x16)Comments
READ110A
EWEN10011XXXXWrite enable must precede all programming modes.
ERASE111A
WRITE101A
ERAL10010XXXXErases all memory locations. Valid only at VCC = 4.5V to 5.5V.
WRAL10001XXXXWrites all memory locations. Valid only at V
EWDS10000XXXXDisables all programming instructions.
5
5
5
- A
- A
- A
0
0
0
Reads data stored in memory, at specified address.
Erase memory location An - A0.
Writes memory location An - A0.
= 4.5V to 5.5V.
CC
5
Functional Description
The AT93C46B is accessed via a simple and versatile
three-wire serial communication interface. Device operation is controll ed by s even in structions issu ed by the host
processor. A valid instruction starts with a rising edge of CS
and consists of a Sta rt Bit (logi c ‘1’) foll owed by the appropriate Op Code and the desired memory Address location.
READ (READ):
the Address code fo r th e m emo ry loc at ion to b e r ea d. Aft er
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 16 bit data output string.
ERASE/WRITE (EWEN):
part automatically goes into the Erase/Write Disable
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, programming remains enabled un til an Erase/Write Disable
(EWDS) instruc tion is executed o r V
from the part.
ERASE (ERASE):
grams all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY / BUSY status of t he part if CS is brough t high
after being kept low for a minimum of 250 ns (t
‘1’ at pin DO indicates that the selected memory location
has been erased, and the part is ready for another instruction.
Synchronous Data Timing
The Read (READ) instruction contains
To assure data integrity, the
power is removed
CC
The Erase (ERASE) instruction pro-
). A logic
CS
WRITE (WRITE):
The Write (WRITE) instruc tio n con tai ns
the 16 bits of data to be written into the specified memory
location. The self-timed programming cycle starts after the
last bit of data is received at serial data input pin DI. The
DO pin outputs the READY/BUSY status of the part if CS is
brought high after being kept low for a minimum of 250 ns
). A logic ‘0’ at DO in dicate s that prog ramm ing is still in
(t
CS
progress. A logic ‘1’ indicates that the memory l ocation at
the specified address has been written with the data pattern contained in the instruction and the part is ready for
further instructions.
ERASE ALL (ERAL):
The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is primarily u sed for test ing pur pose s. The DO pin ou tputs the READ Y/BUSY statu s of t he part i f CS i s brou ght
high after being kept low for a minimum of 250 ns (t
ERAL instruction is valid only at V
WRITE ALL (WRAL):
The Write All (WRAL) instruction
= 5.0V ± 10%.
CC
CS
). The
programs all memory locations with the data patterns specified in the instruction. The DO pin outputs the
READY/BUSY stat us of th e p art if C S is br ough t hi gh a fter
being kept low for a minimum of 25 0 ns (t
instruction is valid only at V
= 5.0V ± 10%.
CC
ERASE/WRITE DI SABLE (EWDS) :
). The WRAL
CS
To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.