ATMEL AT93C46A-10TI-2.5, AT93C46A-10TI, AT93C46A-10TC-2.7, AT93C46A-10TC-2.5, AT93C46A-10TC Datasheet
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1
Features
•
Low-Voltage and Standard-Voltage Operation
– 5.0 (VCC = 4.5V to 5.5V)
– 2.7 (VCC = 2.7V to 5.5V)
– 2.5 (VCC = 2.5V to 5.5V)
•
3-Wire Serial Interface
•
2 MHz Clock Rate (5V) Compatibility
•
Self-Timed Write Cycle (10 ms max)
•
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
– ESD Protection: > 4,000V
•
Automotive Grade and Extended Temperature Devices Available
•
8-Pin PDIP, 8-Pin JEDEC SOIC, and 8-Pin TSSOP Packages
Description
The AT93C46A provides 1024 bits of serial electrically erasable programmable read
only memory (EEPROM) organized as 64 words of 16 bits each. The devi ce is optimized for use in many ind ustrial and com mercial appli cations where lo w power and
low voltage operation are essential. The AT93C46A is available in space saving 8-pin
PDIP, 8-pin JEDEC, and 8-Pin TSSOP packages.
The AT93C46A is enabled through the Chip Selec t pin (CS), and ac cessed via a 3wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a READ instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The WRITE cycl e is completely selftimed and no separate ERASE cycle is required before WRITE. The WRITE cycle is
only enabled when the part is in the ERASE/WRITE ENABLE state. When CS is
brought “high” followin g the initiation of a WRITE cy cle, the DO pin outputs the
READY/BUSY status of the part.
3-Wire
Serial EEPROM
1K (64 x 16)
AT93C46A
Rev. 0539C–07/98
3-Wire, 1K
Serial E
2
PROM
Pin Configurations
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
NC No Connect
DC Don’t Connect
8-Pin PDIP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
8-Pin SOIC
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
8-Pin TSSOP
1
2
3
4
8
7
6
5
CS
SK
DI
DO
VCC
DC
NC
GND
AT93C46A
2
The AT93C46A is available in 4.5V to 5.5V, 2.7V to 5.5V,
and 2.5V to 5.5V versions.
Block Diagram
Note: 1. This parameter is characterized and is not 100% tested.
Absolute Maximum Ratings*
Operating Temperature.................................. -55°C to +125°C
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the de vic e. T his is a stress r ating o nly an d
functional opera tion of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reli abi li ty.
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage........................................... 6.25V
DC Output Current........................................................5.0 mA
Pin Capacitance
(1)
Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +5.0V (unless otherwise noted).
Test Conditions Max Units Conditions
C
OUT
Output Capacitance (DO) 5 pF V
OUT
= 0V
C
IN
Input Capacitance (CS, SK, DI) 5 pF VIN = 0V
AT93C46A
3
Note: 1. VIL min and VIH max are reference only and are not tested.
DC Characteristics
Applicable over recommended operating range from: TAI = -40°C to +85°C, VCC = +2.5V to +5.5V,
T
AC
= 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
V
CC1
Supply Voltage 1.8 5.5 V
V
CC2
Supply Voltage 2.5 5.5 V
V
CC3
Supply Voltage 2.7 5.5 V
V
CC4
Supply Voltage 4.5 5.5 V
I
CC
Supply Current VCC = 5.0V READ at 1.0 MHz 0.5 2.0 mA
WRITE at 1.0 MHz 0.5 2.0 mA
I
SB1
Standby Current VCC = 2.5V CS = 0V 14.0 20.0
µ
A
I
SB2
Standby Current VCC = 2.7V CS = 0V 14.0 20.0
µ
A
I
SB3
Standby Current VCC = 5.0V CS = 0V 35.0 50.0
µ
A
I
IL
Input Leakage VIN = 0V to VCC 0.1 1.0
µ
A
I
OL
Output Leakage VIN = 0V to VCC 0.1 1.0
µ
A
V
IL1
(1)
V
IH1
(1)
Input Low Voltage
Input High Voltage
4.5V ≤ VCC ≤ 5.5V -0.6
2.0
0.8
VCC + 1
V
V
IL2
(1)
V
IH2
(1)
Input Low Voltage
Input High Voltage
1.8V ≤ VCC ≤ 2.7V -0.6
V
CC
x 0.7
V
CC
x 0.3
VCC + 1
V
V
OL1
V
OH1
Output Low Voltage
Output High Voltage
4.5V ≤ VCC ≤ 5.5V IOL = 2.1 mA 0.4 V
I
OH
= -0.4 mA 2.4 V
V
OL2
V
OH2
Output Low Voltage
Output High Voltage
1.8V ≤ VCC ≤ 2.7V IOL = 0.15 mA 0.2 V
I
OH
= -100 µAV
CC
- 0.2 V
AC Characteristics
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
f
SK
SK Clock Frequency
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
0
0
0
0
2
1
0.5
0.25
MHz
t
SKH
SK High Time
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
t
SKL
SK Low Time
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
t
CS
Minimum CS Low Time
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
AT93C46A
4
Note: 1. This parameter is characterized and is not 100% tested.
t
CSS
CS Setup Time Relative to SK
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
50
50
100
200
ns
t
DIS
DI Setup Time Relative to SK
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
100
100
200
400
ns
t
CSH
CS Hold Time Relative to SK 0 ns
t
DIH
DI Hold Time Relative to SK
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
100
100
200
400
ns
t
PD1
Output Delay to ‘1’ AC Test
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
t
PD0
Output Delay to ‘0’ AC Test
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
t
SV
CS to Status Valid AC Test
4.5V ≤ V
CC
≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
250
250
500
1000
ns
t
DF
CS to DO in High Impedance
AC Test
CS = V
IL
4.5V ≤ VCC ≤ 5.5V
2.7V ≤ V
CC
≤ 5.5V
2.5V ≤ V
CC
≤ 5.5V
1.8V ≤ V
CC
≤ 5.5V
100
100
200
400
ns
t
WP
Write Cycle Time
0.1 10 ms
4.5V ≤ VCC ≤ 5.5V 1 ms
Endurance
(1)
5.0V, 25°C, Page Mode 1M
Write
Cycle
Instruction Set for the AT93C46A
Instruction SB Op Code
Address
Commentsx 16
READ 1 10 A
5
- A
0
Reads data stored in memory, at specified addre ss.
EWEN 1 00 11XXXX Write enable must precede all programming modes.
ERASE 1 11 A
5
- A
0
Erase memory location An - A0.
WRITE 1 01 A
5
- A
0
Writes memory location An - A0.
ERAL 1 00 10XXXX Erases all memory locations. Valid only at VCC = 4.5V to 5.5V.
WRAL 1 00 01XXXX Writes all memory locations. Valid only at V
CC
= 4.5V to 5.5V.
EWDS 1 00 00XXXX Disables all programming instructions.
AC Characteristics (Continued)
Applicable over recommended operating range from TA = -40°C to + 85°C, VCC = +2.5V to + 5.5V,
CL = 1 TTL Gate and 100 pF (unless otherwise noted).
Symbol Parameter Test Condition Min Typ Max Units
AT93C46A
5
Functional Description
The AT93C46A is accessed via a simple and versatile
three-wire serial communication interface. Device operation is controlle d by se ven ins tructio ns issued by the host
processor.
A valid instruction starts with a rising edge
of CS
and consists of a Start Bit (logic ‘1’) followed by the
appropriate Op Code and the desired memory Address
location.
READ (READ):
The Read (READ) instructio n contains
the Address code fo r the me mory l oc ati on to be read. After
the instruction and address are decoded, data from the
selected memory location is available at the serial output
pin DO. Output data changes are synchronized with the rising edges of serial clock SK. It should be noted that a
dummy bit (logic ‘0’) precedes the 16-bit data output string.
ERASE/WRITE (EWEN):
To assure data integrity, the
part automatically go es into the Erase/Write Dis able
(EWDS) state when power is first applied. An Erase/Write
Enable (EWEN) instruction must be executed first before
any programming instructions can be carried out. Please
note that once in the Erase/Write Enable state, programming remains e nabled until an Er ase/Write Disable
(EWDS) instruction is executed or V
CC
power is removed
from the part.
ERASE (ERASE):
The Erase (ERASE) instruction pr ograms all bits in the specified memory location to the logical
‘1’ state. The self-timed erase cycle starts once the ERASE
instruction and address are decoded. The DO pin outputs
the READY/BUSY status of the part if CS is brought high
after being kept low for a minimum of 250 ns (t
CS
). A logic
‘1’ at pin DO indicates that the selected memory location
has been erase d, and the part is r eady for an other instr uction.
WRITE (WRITE):
The Write (WRITE) instruction contains
the 16 bits of data to be written into the specified memory
location. T he se lf-t ime d pr ogra mming cycl e, t
WP
, starts after
the last bit of data is received at serial data input pin DI.
The DO pin outputs the READY/BUSY status of the part if
CS is brought high after being kept low for a minimum of
250 ns (t
CS
). A logic ‘0’ at DO indicates that programming is
still in progress. A logic ‘1’ indicates that the memory location at the specified ad dres s h as been wr itte n with the data
pattern contained in the instruction and the part is ready for
further instructions.
A READY/BUSY status ca nnot be
obtained if the CS is brought high after the end of the
self-timed programming cycle, t
WP
.
ERASE ALL (ERA L):
The Erase All (ERAL) instruction
programs every bit in the memory array to the logic ‘1’ state
and is primarily u sed for te sting p urpos es. The DO pin outputs the READY/BU SY status of the pa rt if CS is brough t
high after being kept low for a minimum of 250 ns (t
CS
). The
ERAL instruction is vali d only at V
CC
= 5.0V ± 10%.
WRITE ALL (WRAL):
The Write All (WRAL) instruction
programs all memory locations with the data patterns specified in the instruction . The DO pin outputs the
READY/BUSY sta tus of the pa rt if CS i s brought h igh after
being kept low for a minimum of 250 ns (t
CS
). The WRAL
instruction is valid only at V
CC
= 5.0V ± 10%.
ERASE/WRITE DISAB LE (EWDS):
To protect against
accidental data disturb, the Erase/Write Disable (EWDS)
instruction disables all programming modes and should be
executed after all programming operations. The operation
of the READ instruction is independent of both the EWEN
and EWDS instructions and can be executed at any time.
AT93C46A
6
Timing Diagrams
Synchronous Data Timing
Note: 1. This is the minimum SK period.
AT93C46A
7
READ Timing
EWEN Timing
(1)
Note: 1. Requires a minimum of nine clock cycles.
EWDS Timing
(1)
Note: 1. Requires a minimum of nine clock cycles.
Organization Key for Timing Diagrams
I/O
AT93C46A
x 16
A
N
A
5
D
N
D
15
CS
SK
DI
101
t
CS
A
N
A
0
0
D
N
D0
DO
CS
SK
DI
100
11
t
CS
CS
SK
DI
1
00 00
t
CS
AT93C46A
8
WRITE Timing
WRAL Timing
(1)(2)
Notes: 1. Valid only at VCC = 4.5V to 5.5V.
2. Requires a minimum of nine clock cycles.
CS
SK
DI
DO HIGH IMPEDANCE
t
CS
BUSY
READY
t
WP
1
0
A
N
A0
D
N
D0
1
HIGH IMPEDANCE
BUSY
READY
t
CS
t
WP
1
0001
D
N
D
0
CS
SK
DI
DO
AT93C46A
9
ERASE Timing
TERAL Timing
(1)
Note: 1. Valid only at VCC = 4.5V to 5.5V.
SK
CS
DI
DO
t
WP
AT93C46A
10
Ordering Information
tWP (max)
(ms)
ICC (max)
(µµµµA)
ISB (max)
(µµµµA)
f
MAX
(kHz) Ordering Code Package Operation Range
10 2000 50.0 2000 AT93C46A-10PC
AT93C46A-10SC
AT93C46A-10TC
8P3
8S1
8T
Commercial
(0°C to 70°C)
10 2000 50.0 2000 AT93C46A-10PI
AT93C46A-10SI
AT93C46A-10TI
8P3
8S1
8T
Industrial
(-40°C to 85°C)
10 800 20.0 1000 AT93C46A-10PC-2.7
AT93C46A-10SC-2.7
AT93C46A-10TC-2.7
8P3
8S1
8T
Commercial
(0°C to 70°C)
10 800 20.0 1000 AT93C46A-10PI-2.7
AT93C46A-10SI-2.7
AT93C46A-10TI-2.7
8P3
8S1
8T
Industrial
(-40°C to 85°C)
10 600 20.0 500 AT93C46A-10PC-2.5
AT93C46A-10SC-2.5
AT93C46A-10TC-2.5
8P3
8S1
8T
Commercial
(0°C to 70°C)
10 600 20.0 500 AT93C46A-10PI-2.5
AT93C46A-10SI-2.5
AT93C46A-10TI-2.5
8P3
8S1
8T
Industrial
(-40°C to 85°C)
Package Type
8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
8T 8-Lead, 0.170" Wide, Thin Small Outline Package (TSSOP)
Options
Blank Standard Device (4.5V to 5.5V)
-2.7 Low Voltage (2.7V to 5.5V)
-2.5 Low Voltage (2.5V to 5.5V)
-1.8 Low Voltage (1.8V to 5.5V)
AT93C46A
11
Packaging Information
.400 (10.16)
.355 (9.02)
PIN
1
.280 (7.11)
.240 (6.10)
.037 (.940)
.027 (.690)
.300 (7.62) REF
.210 (5.33) MAX
SEATING
PLANE
.100 (2.54) BSC
.015 (.380) MIN
.022 (.559)
.014 (.356)
.150 (3.81)
.115 (2.92)
.070 (1.78)
.045 (1.14)
.325 (8.26)
.300 (7.62)
0
15
REF
.430 (10.9) MAX
.012 (.305)
.008 (.203)
.020 (.508)
.013 (.330)
PIN 1
.157 (3.99)
.150 (3.81)
.244 (6.20)
.228 (5.79)
.050 (1.27) BSC
.196 (4.98)
.189 (4.80)
.068 (1.73)
.053 (1.35)
.010 (.254)
.004 (.102)
0
8
REF
.010 (.254)
.007 (.203)
.050 (1.27)
.016 (.406)
6.50 (.256)
6.25 (.246)
0.30 (.012)
0.19 (.008)
.65 (.026) BSC
1.05 (.041)
0.80 (.033)
3.10 (.122)
4.5 (.177)
2.90 (.114)
4.3 (.169)
0.15 (.006)
0.05 (.002)
1.20 (.047) MAX
0.20 (.008)
0.75 (.030)
0.09 (.004)
0.45 (.018)
0
8
REF
PIN 1
8P3
, 8-Lead, 0.300" Wide, Plastic Dual Inline
Package (PDIP)Dimensions in Inches and
(Millimeters)
JEDEC STANDARD MS-001 BA
8S1
, 8-Lead, 0.150" Wide, Plastic Gull Wing Small
Outline (JEDEC SOIC)
Dimensions in Inches and (Millimeters)
8T,
8-Lead, 0.170" Wide, Thin Small Outline Package
(TSSOP)
Dimensions in Millimeters and (Inches)*
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