ATMEL AT91SAM9XE128 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• Incorporates the ARM926EJ-S

– DSP instruction Extensions, ARM Jazelle – 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer – 200 MIPS at 180 MHz – Memory Management Unit – EmbeddedICE

• Additional Embedded Memories

– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed – One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for

AT91SAM9XE128) Internal SRAM, Single-cycle Access at Maximum Matrix Speed

– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128,

AT91SAM9XE256 or AT91SAM9XE512 Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively.

• 128-bit Wide Access

• Fast Read Time: 60 ns

• Page Programming Time: 4 ms, Including Page Auto-erase, Full Erase Time: 10 ms

• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit

• Enhanced Embedded Flash Controller (EEFC)

– Interface of the Flash Block with the 32-bit Internal Bus – Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory

Interface

• External Bus Interface (EBI)

– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash

• USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM

• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device

and Double Port in 217-ball LFBGA Device

– Single or Dual On-chip Transceivers – Integrated FIFOs and Dedicated DMA Channels

• Ethernet MAC 10/100 Base-T

– Media Independent Interface or Reduced Media Independent Interface – 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit

• Image Sensor Interface

– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate – 12-bit Data Interface for Support of High Sensibility Sensors – SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format

• Bus Matrix

– Six 32-bit-layer Matrix – Remap Command

• Fully-featured System Controller, including

– Reset Controller, Shutdown Controller – Four 32-bit Battery Backup Registers for a Total of 16 Bytes – Clock Generator and Power Management Controller – Advanced Interrupt Controller and Debug Unit – Periodic Interval Timer, Watchdog Timer and Real-time Timer

™

, Debug Communication Channel Support

™

ARM® Thumb® Processor

Technology for Java® Acceleration

™

AT91 ARM Thumb Microcontrollers

AT91SAM9XE128 AT91SAM9XE256 AT91SAM9XE512

Preliminary

6254A–ATARM–01-Feb-08

• Reset Controller (RSTC)

– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control

• Clock Generator (CKGR)

– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply,

Providing a Permanent Slow Clock

– 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL

• Power Management Controller (PMC)

– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities – Two Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected

• Debug Unit (DBGU)

– 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention

• Periodic Interval Timer (PIT)

– 20-bit Interval Timer Plus 12-bit Interval Counter

• Watchdog Timer (WDT)

– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock

• Real-Time Timer (RTT)

– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler

• One 4-channel 10-bit Analog to Digital Converter

• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,)

– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

• Peripheral DMA Controller Channels (PDC)

• Two-slot Multimedia Card Interface (MCI)

™

– SDCard/SDIO and MultiMediaCard – Automatic Protocol Control and Fast Automatic Data Transfers with PDC

Compliant

• One Synchronous Serial Controllers (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Signal Control on USART0

Infrared Modulation/Demodulation

• One 2-wire UART

• Two Master/Slave Serial Peripheral Interface (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects – Synchronous Communications

• Two Three-channel 16-bit Timer/Counters (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability – High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2

• Two Two-wire Interfaces (TWI)

– Master, Multi-master and Slave Mode Operation – General Call Supported in Slave Mode – Connection to PDC Channel to Optimize Data Transfers in Master Mode Only

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

• IEEE

• Required Power Supplies:

• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package

1. AT91SAM9XE128/256/512 Description

The AT91SAM9XE128/256/512 is based on the integration of an ARM926EJ-S processor with fast ROM and RAM, 128, 256 or 512 Kbytes of Flash and a wide range of peripherals.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserves its confidentiality.

The AT91SAM9XE128/256/512 embeds an Ethernet MAC, one USB Device Port, and a USB Host Controller. It also integrates several standard peripherals, like USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and a MultiMedia Card Interface.

The AT91SAM9XE128/256/512 system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

1149.1 JTAG Boundary Scan on All Digital Pins

– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL – 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os) – 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter) – Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)

The AT91SAM9XE128/256/512 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices.

The pinout and ball-out are fully compatible with the AT91SAM9260 with the exception that the pin BMS is replaced by the pin ERASE.

6254A–ATARM–01-Feb-08

2. AT91SAM9XE128/256/512 Block Diagram

The block diagram shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-PQFP package and the unavailable pins are highlighted in “Multiplexing

on PIO Controller A” on page 39, “Multiplexing on PIO Controller B” on page 40, “Multiplexing on PIO Controller C” on page 41. The USB Host Port B is also not available. Table 2-1 on page 4

defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package.

Table 2-1. Unavailable Signals in 208-pin PQFP Device

PIO Peripheral A Peripheral B

- HDPB -

- HDMB -

PA30 SCK2 RXD4

PA 31 S C K 0 T X D4

PB12 TWD1 ISI_D10

PB13 TWCK1 ISI_D11

PC2 AD2 PCK1

PC3 AD3 SPI1_NPCS3

PC12 IRQ0 NCS7

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

Figure 2-1. AT91SAM9XE128/256/512 Block Diagram

HDMB

HDPB

HDMA

HDPA

ISI_HSYNC

ISI_DO-ISI_D7 ISI_PCK

ISI_MCK

ISI_VSYNC

Transc.

USB

OHCI

Image

Sensor

Interface

DMA

D0-D15

A0/NBS0

A2-A15, A18-A20

A1/NBS2/NWR2

EBI

A16/BA0

A17/BA1

NCS0

NCS1/SDCS

NAND Flash

CompactFlash

NRD

NWR0/NWE

NWR1/NBS1

NWR3/NBS3

SDCK, SDCKE

RAS, CAS

SDWE, SDA10

NANDOE, NANDWE

A21/NANDALE

A22/NANDCLE

Static

SDRAM

Controller

DPRAM

D16-D31

NWAIT

Memory

Controller

USB

Device

A23-A24

NCS5/CFCS1

A25/CFRNW

NCS4/CFCS0

ECC

Controller

NCS2, NCS6, NCS7

NCS3/NANDCS

CFCE1-CFCE2

Transceiver

DDP

DDM

F100 MDIO MDC ETX0-ETX3 ERX0-ERX3 ERXER-ERXDV ECRS-ECOL ETXEN-ETXER ETXCK-ERXCK

JTAGSEL

RTCK TCK

TMS TDO

TDI NTRST

ERASE

SLAVEMASTER

JTAG Selection and Boundary Scan

System

Controller

10/100 Ethernet

In-Circuit Emulator

AIC

FIFO

MAC

FIFO

DCache

8 Kbytes

MMU

ARM926EJ-S Processor

ICache

16 Kbytes

PDC

DBGU

Peripheral

24-channel

DMA

Bridge

Peripheral

6-layer Matrix

Kbytes

16 or 32

Fast SRAM

ROM

RTT

OSC

Flash

PIOA

SHDC

32 Kbytes

or 512

128, 256

PIOB

Bus Interface

PLLB

Filter

OSC

PITWDT

4GPREG

PMC

PLLA

DMA

Kbytes

PIOC

POR

RSTC

POR

BOD

APB

PDC

4-channel

10-bit ADC

SSC

TC3

TC4

TC0

TC1

SPI0

SPI1

USART0

USART1

USART2

TWI0

TWI1

MCI

TC5

TC2

USART3

GNDANA

VDDANA

ADVREF

ADTRIG

AD0-AD3

RK RF

RD TD TF

TIOB3-TIOB5 TIOA3-TIOA5

TCLK3-TCLK5 TIOB0-TIOB2 TIOA0-TIOA2

MISO

TCLK0-TCLK2

MOSI

SPCK

NPCS0 NPCS1 NPCS2 NPCS3

SPI0_, SPI1_

DTR0

RI0

DCD0

DSR0

USART4

TWCK

TWD

MCCK

MCCDA

MCCDB

TXD0-TXD5

RXD0-RXD5

SCK0-SCK3 RTS0-RTS3 CTS0-CTS3

MCDA0-MCDA3

6254A–ATARM–01-Feb-08

TST

FIQ

IRQ0-IRQ2

DTXD

DRXD

PLLRCA

PCK0-PCK1

XIN

XOUT

XIN32

XOUT32

OSCSEL

SHDN

WKUP

VDDBU

NRST

MCDB0-MCDB3

VDDCORE

3. Signals Description

Table 3-1 gives details on the signal name classified by peripheral.

Table 3-1. Signal Description List

Active

Signal Name Function Type

Power Supplies

VDDIOM EBI I/O Lines Power Supply Power 1.65V to 1.95V or 3.0V to 3.6V VDDIOP0 Peripherals I/O Lines Power Supply Power 3.0V to 3.6V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65V to 3.6V VDDBU Backup I/O Lines Power Supply Power 1.65V to 1.95V VDDANA Analog Power Supply Power 3.0V to 3.6V VDDPLL PLL Power Supply Power 1.65V to 1.95V

VDDCORE

GND Ground Ground GNDPLL PLL Ground Ground GNDANA Analog Ground Ground GNDBU Backup Ground Ground

XIN Main Oscillator Input Input XOUT Main Oscillator Output Output XIN32 Slow Clock Oscillator Input Input XOUT32 Slow Clock Oscillator Output Output

OSCSEL Slow Clock Oscillator Selection Input

PLLRCA PLL A Filter Input PCK0 - PCK1 Programmable Clock Output Output

SHDN Shutdown Control Output

WKUP Wake-Up Input Input

NTRST Test Reset Signal Input Low Pull-up resistor TCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor

JTAGSEL JTAG Selection Input

RTCK Return Test Clock Output

Core Chip and Embedded Memories Power Supply

Clocks, Oscillators and PLLs

Shutdown, Wakeup Logic

ICE and JTAG

Power 1.65V to 1.95V

Level Comments

Accepts between 0V and VDDBU.

Driven at 0V only. Do not tie over VDDBU.

Accepts between 0V and VDDBU.

Pull-down resistor. Accepts between 0V and VDDBU.

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Flash Memory

ERASE

NRST Microcontroller Reset I/O Low Pull-up resistor

TST Test Mode Select Input

DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

IRQ0 - IRQ2 External Interrupt Inputs Input FIQ Fast Interrupt Input Input

PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset PB0 - PB30 Parallel IO Controller B I/O Pulled-up input at reset PC0 - PC31 Parallel IO Controller C I/O Pulled-up input at reset

D0 - D31 Data Bus I/O Pulled-up input at reset A0 - A25 Address Bus Output 0 at reset NWAIT External Wait Signal Input Low

NCS0 - NCS7 Chip Select Lines Output Low NWR0 - NWR3 Write Signal Output Low NRD Read Signal Output Low NUB Upper Byte Select Output Low NLB Lower Byte Select Output Low NWE Write Enable Output Low NBS0 - NBS3 Byte Mask Signal Output Low

CFCE1 - CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output CFCS0 - CFCS1 CompactFlash Chip Select Lines Output Low

Flash and NVM Configuration Bits Erase Command

Reset/Test

Debug Unit - DBGU

Advanced Interrupt Controller - AIC

PIO Controller - PIOA - PIOB - PIOC

External Bus Interface - EBI

Static Memory Controller - SMC

CompactFlash Support

Input High Pull-down resistor

Level Comments

Pull-down resistor. Accepts between 0V and VDDBU.

6254A–ATARM–01-Feb-08

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

NAND Flash Support

NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low

SDRAM Controller

SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA0 - BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output

Multimedia Card Interface MCI

MCCK Multimedia Card Clock Output MCCDA Multimedia Card Slot A Command I/O MCDA0 - MCDA3 Multimedia Card Slot A Data I/O MCCDB Multimedia Card Slot B Command I/O MCDB0 - MCDB3 Multimedia Card Slot B Data I/O

Universal Synchronous Asynchronous Receiver Transmitter USARTx

SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data I/O RXDx USARTx Receive Data Input RTSx USARTx Request To Send Output CTSx USARTx Clear To Send Input DTR0 USART0 Data Terminal Ready Output DSR0 USART0 Data Set Ready Input DCD0 USART0 Data Carrier Detect Input RI0 USART0 Ring Indicator Input

Synchronous Serial Controller - SSC

TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O

Level Comments

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Timer/Counter - TCx

TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O

Serial Peripheral Interface - SPIx_

SPIx_MISO Master In Slave Out I/O SPIx_MOSI Master Out Slave In I/O SPIx_SPCK SPI Serial Clock I/O SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1-SPIx_NPCS3 SPI Peripheral Chip Select Output Low

Two-Wire Interface

TWDx Two-wire Serial Data I/O TWCKx Two-wire Serial Clock I/O

USB Host Port

HDPA USB Host Port A Data + Analog HDMA USB Host Port A Data - Analog HDPB USB Host Port B Data + Analog HDMB USB Host Port B Data + Analog

USB Device Port

DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog

Ethernet 10/100

ETXCK Transmit Clock or Reference Clock Input MII only, REFCK in RMII ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0-ETX3 Transmit Data Output ETX0-ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input RXDV in MII, CRSDV in RMII ERX0-ERX3 Receive Data Input ERX0-ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense and Data Valid Input MII only ECOL Collision Detect Input MII only EMDC Management Data Clock Output EMDIO Management Data Input/Output I/O EF100 Force 100Mbit/sec. Output High

Level Comments

6254A–ATARM–01-Feb-08

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Image Sensor Interface

ISI_D0-ISI_D11 Image Sensor Data Input ISI_MCK Image sensor Reference clock output ISI_HSYNC Image Sensor Horizontal Synchro input ISI_VSYNC Image Sensor Vertical Synchro input ISI_PCK Image Sensor Data clock input

Analog to Digital Converter

AD0-AD3 Analog Inputs Analog

ADVREF Analog Positive Reference Analog ADTRG ADC Trigger Input

Fast Flash Programming Interface

PGMEN[2:0] Programming Enabling Input PGMNCMD Programming Command Input Low PGMRDY Programming Ready Output High PGMNOE Programming Read Input Low PGMNVALID Data Direction Output Low PGMM[3:0] Programming Mode Input PGMD[15:0] Programming Data I/O

Level Comments

Digital pulled-up inputs at reset

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

4. Package and Pinout

The AT91SAM9XE128/256/512 is available in a 208-pin PQFP Green package (0.5mm pitch) or in a 217-ball LFBGA Green package (0.8 mm ball pitch).

4.1 208-pin PQFP Package Outline

Figure 4-1 shows the orientation of the 208-pin PQFP package.

A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet.

Figure 4-1. 208-pin PQFP Package Outline (Top View)

AT91SAM9XE128/256/512 Preliminary

105156

157

208

104

152

6254A–ATARM–01-Feb-08

4.2 208-pin PQFP Package Pinout

Table 4-1. Pinout for 208-pin PQFP Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

1 PA24 53 GND 105 RAS 157 ADVREF 2 PA25 54 DDM 106 D0 158 PC0 3 PA26 55 DDP 107 D1 159 PC1 4 PA27 56 PC13 108 D2 160 VDDANA 5 VDDIOP0 57 PC11 109 D3 161 PB10 6 GND 58 PC10 110 D4 162 PB11 7 PA28 59 PC14 111 D5 163 PB20 8 PA29 60 PC9 112 D6 164 PB21 9 PB0 61 PC8 113 GND 165 PB22 10 PB1 62 PC4 114 VDDIOM 166 PB23 11 PB2 63 PC6 115 SDCK 167 PB24 12 PB3 64 PC7 116 SDWE 168 PB25 13 VDDIOP0 65 VDDIOM 117 SDCKE 169 VDDIOP1 14 GND 66 GND 118 D7 170 GND 15 PB4 67 PC5 119 D8 171 PB26 16 PB5 68 NCS0 120 D9 172 PB27 17 PB6 69 CFOE/NRD 121 D10 173 GND 18 PB7 70 CFWE/NWE/NWR0 122 D11 174 VDDCORE 19 PB8 71 NANDOE 123 D12 175 PB28 20 PB9 72 NANDWE 124 D13 176 PB29 21 PB14 73 A22 125 D14 177 PB30 22 PB15 74 A21 126 D15 178 PB31 23 PB16 75 A20 127 PC15 179 PA0 24 VDDIOP0 76 A19 128 PC16 180 PA1 25 GND 77 VDDCORE 129 PC17 181 PA2 26 PB17 78 GND 130 PC18 182 PA3 27 PB18 79 A18 131 PC19 183 PA4 28 PB19 80 BA1/A17 132 VDDIOM 184 PA5 29 TDO 81 BA0/A16 133 GND 185 PA6 30 TDI 82 A15 134 PC20 186 PA7 31 TMS 83 A14 135 PC21 187 VDDIOP0 32 VDDIOP0 84 A13 136 PC22 188 GND 33 GND 85 A12 137 PC23 189 PA8 34 TCK 86 A11 138 PC24 190 PA9 35 NTRST 87 A10 139 PC25 191 PA10 36 NRST 88 A9 140 PC26 192 PA11 37 RTCK 89 A8 141 PC27 193 PA12 38 VDDCORE 90 VDDIOM 142 PC28 194 PA13 39 GND 91 GND 143 PC29 195 PA14 40 ERASE 92 A7 144 PC30 196 PA15 41 OSCSEL 93 A6 145 PC31 197 PA16 42 TST 94 A5 146 GND 198 PA17 43 JTAGSEL 95 A4 147 VDDCORE 199 VDDIOP0 44 GNDBU 96 A3 148 VDDPLL 200 GND 45 XOUT32 97 A2 149 XIN 201 PA18 46 XIN32 98 NWR2/NBS2/A1 150 XOUT 202 PA19 47 VDDBU 99 NBS0/A0 151 GNDPLL 203 VDDCORE 48 WKUP 100 SDA10 152 NC 204 GND 49 SHDN 101 CFIOW/NBS3/NWR3 153 GNDPLL 205 PA20 50 HDMA 102 CFIOR/NBS1/NWR1 154 PLLRCA 206 PA21 51 HDPA 103 SDCS/NCS1 155 VDDPLL 207 PA22 52 VDDIOP0 104 CAS 156 GNDANA 208 PA23

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

4.3 217-ball LFBGA Package Outline

Figure 4-2 shows the orientation of the 217-ball LFBGA package.

A detailed mechanical description is given in the section “AT91SAM9XE Mechanical Characteristics” of the product datasheet.

Figure 4-2. 217-ball LFBGA Package Outline (Top View)

AT91SAM9XE128/256/512 Preliminary

17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

Ball A1

ABCDEFGHJ K LMNPRTU

6254A–ATARM–01-Feb-08

4.4 217-ball LFBGA Package Pinout

Table 4-2. Pinout for 217-ball LFBGA Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 CFIOW/NBS3/NWR3 D5 A5 J14 TDO P17 PB5 A2 NBS0/A0 D6 GND J15 PB19 R1 NC A3 NWR2/NBS2/A1 D7 A10 J16 TDI R2 GNDANA A4 A6 D8 GND J17 PB16 R3 PC29 A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA A6 A11 D10 GND K2 PC20 R5 PB12 A7 A13 D11 VDDIOM K3 D15 R6 PB23 A8 BA0/A16 D12 GND K4 PC21 R7 GND A9 A18 D13 DDM K8 GND R8 PB26 A10 A21 D14 HDPB K9 GND R9 PB28 A11 A22 D15 NC K10 GND R10 PA0 A12 CFWE/NWE/NWR0 D16 VDDBU K14 PB4 R11 PA4 A13 CFOE/NRD D17 XIN32 K15 PB17 R12 PA5 A14 NCS0 E1 D10 K16 GND R13 PA10 A15 PC5 E2 D5 K17 PB15 R14 PA21 A16 PC6 E3 D3 L1 GND R15 PA23 A17 PC4 E4 D4 L2 PC26 R16 PA24 B1 SDCK E14 HDPA L3 PC25 R17 PA29 B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDIOP0 T1 PLLRCA B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0 B5 A3 F1 D13 L16 PB8 T4 PC1 B6 A7 F2 SDWE L17 PB14 T5 PB10 B7 A12 F3 D6 M1 VDDCORE T6 PB22 B8 A15 F4 GND M2 PC31 T7 GND B9 A20 F14 OSCSEL M3 GND T8 PB29 B10 NANDWE F15 ERASE M4 PC22 T9 PA2 B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6 B12 PC10 F17 TST M15 PB2 T11 PA8 B13 PC13 G1 PC15 M16 PB3 T12 PA11 B14 PC11 G2 D7 M17 PB7 T13 VDDCORE B15 PC14 G3 SDCKE N1 XIN T14 PA20 B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND B17 WKUP G14 GND N3 PC23 T16 PA22 C1 D8 G15 NRST N4 PC27 T17 PA27 C2 D1 G16 RTCK N14 PA31 U1 GNDPLL C3 CAS G17 TMS N15 PA30 U2 ADVREF C4 A2 H1 PC18 N16 PB0 U3 PC2 C5 A4 H2 D14 N17 PB6 U4 PC3 C6 A9 H3 D12 P1 XOUT U5 PB20 C7 A14 H4 D11 P2 VDDPLL U6 PB21 C8 BA1/A17 H8 GND P3 PC30 U7 PB25 C9 A19 H9 GND P4 PC28 U8 PB27 C10 NANDOE H10 GND P5 PB11 U9 PA12 C11 PC9 H14 VDDCORE P6 PB13 U10 PA13 C12 PC12 H15 TCK P7 PB24 U11 PA14 C13 DDP H16 NTRST P8 VDDIOP1 U12 PA15 C14 HDMB H17 PB18 P9 PB30 U13 PA19 C15 NC J1 PC19 P10 PB31 U14 PA17 C16 VDDIOP0 J2 PC17 P11 PA1 U15 PA16 C17 SHDN J3 VDDIOM P12 PA3 U16 PA18 D1 D9 J4 PC16 P13 PA7 U17 VDDIOP0

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

Table 4-2. Pinout for 217-ball LFBGA Package (Continued)

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

D2 D2 J8 GND P14 PA9 D3 RAS J9 GND P15 PA26 D4 D0 J10 GND P16 PA25

5. Power Considerations

5.1 Power Supplies

The AT91SAM9XE128/256/512 has several types of power supply pins:

• VDDCORE pins: Power the core, including the processor, the embedded memories and the peripherals; voltage ranges from 1.65V and 1.95V, 1.8V nominal.

• VDDIOM pins: Power the External Bus Interface I/O lines; voltage ranges between 1.65V and

1.95V (1.8V typical) or between 3.0V and 3.6V (3.3V nominal). The expected voltage range is selectable by software.

• VDDIOP0 pins: Power the Peripheral I/O lines and the USB transceivers; voltage ranges from

3.0V and 3.6V, 3V or 3.3V nominal.

• VDDIOP1 pin: Powers the Peripherals I/O lines involving the Image Sensor Interface; voltage ranges from 1.65V and 3.6V, 1.8V, 2.5V, 3V or 3.3V nominal.

• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage ranges from 1.65V to 1.95V, 1.8V nominal.

• VDDPLL pins: Power the PLL cells and the main oscillator; voltage ranges from 1.65V and

1.95V, 1.8V nominal.

• VDDANA pin: Powers the Analog to Digital Converter; voltage ranges from 3.0V and 3.6V,

3.3V nominal.

The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and their associated I/O lines in the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals.

Ground pins GND are common to VDDCORE, VDDIOM, VDDIOP0 and VDDIOP1 pins power supplies. Separated ground pins are provided for VDDBU, VDDPLL and VDDANA. These ground pins are respectively GNDBU, GNDPLL and GNDANA.

5.2 Power Consumption

The AT91SAM9XE128/256/512 consumes about 500 µA of static current on VDDCORE at 25°C. This static current rises up to 5 mA if the temperature increases to 85°C.

On VDDBU, the current does not exceed 20 µA in worst case conditions.

For dynamic power consumption, the AT91SAM9XE128/256/512 consumes a maximum of 130 mA on VDDCORE at maximum conditions (1.8V, 25°C, processor running full-performance algorithm out of high speed memories).

5.3 Programmable I/O Lines Power Supplies

The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories.

6254A–ATARM–01-Feb-08

The maximum speed is 100 MHz on the pin SDCK (SDRAM Clock) loaded with 30 pF for power supply at 1.8V and 50 pF for power supply at 3.3V. The other signals (control, address and data signals) do not exceed 50 MHz.

The voltage ranges are determined by programming registers in the Chip Configuration registers located in the Matrix User Interface.

At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either

1.8V or 3.3V. The user must program the EBI voltage range before getting the device out of its Slow Clock Mode.

6. I/O Line Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors.

TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors.

The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.

The NTRST signal is described in Section 6.3.

All the JTAG signals are supplied with VDDIOP0.

6.2 Test Pin

6.3 Reset Pins

6.4 ERASE Pin

The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results.

This pin is supplied with VDDBU.

NRST is a bi-directional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0.

NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor.

As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected.

The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in the table “DC Characteristics” in the section “AT91SAM9XE Electrical Characteristics” in the product datasheet.

The NRST signal is inserted in the Boundary Scan.

The pin ERASE is used to re-initialize the Flash content and the NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ, so that it can be left unconnected for normal operations.

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

This pin is debounced on the RC oscillator or 32,768 Hz to improve the glitch tolerance. Minimum debouncing time is 200 ms.

6.5 PIO Controllers

All the I/O lines are Schmitt trigger inputs and all the lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to “DC Characteristics” in the section “AT91SAM9XE128/256/512 Electrical Characteristics”. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers.

After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables.

6.6 I/O Line Drive Levels

The PIO lines PA0 to PA31 and PB0 to PB31 and PC0 to PC3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently with a total of 350 mA on all I/O lines.

Refer to the “DC Characteristics” section of the product datasheet.

AT91SAM9XE128/256/512 Preliminary

6.7 Shutdown Logic Pins

The SHDN pin is an output only, which is driven by the Shutdown Controller.

The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.

6.8 Slow Clock Selection

The AT91SAM9XE128/256/512 slow clock can be generated either by an external 32,768 Hz crystal or the on-chip RC oscillator.

The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32,768 Hz startup delay is 1200 ms whereas it is 200 µs for the internal RC oscillator. The pin OSCSEL must be tied either to GNDBU or VDDBU for correct operation of the device.

Refer to the Slow Clock Selection table in the Electrical Characteristics section of the product datasheet for the states of the OSCSEL signal.

6254A–ATARM–01-Feb-08

7. Processor and Architecture

7.1 ARM926EJ-S Processor

• RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set

• DSP Instruction Extensions

• 5-Stage Pipeline Architecture:

– Instruction Fetch (F) – Instruction – Execute (E) – Data Memory (M) – Register Write (W)

• 8 KB Data Cache, 16 KB Instruction Cache

– Virtually-addressed 4-way Associative Cache – Eight words per line – Write-through and Write-back Operation – Pseudo-random or Round-robin Replacement

• Write Buffer

– Main Write Buffer with 16-word Data Buffer and 4-address Buffer – DCache Write-back Buffer with 8-word Entries and a Single Address Entry – Software Control Drain

• Standard ARM v4 and v5 Memory Management Unit (MMU)

– Access Permission for Sections – Access Permission for large pages and small pages can be specified separately for

each quarter of the page

– 16 embedded domains

• Bus Interface Unit (BIU)

– Arbitrates and Schedules AHB Requests – Separate Masters for both instruction and data access providing complete Matrix

system flexibility

– Separate Address and Data Buses for both the 32-bit instruction interface and the

32-bit data interface

– On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit

(Words)

Decode (D)

7.2 Bus Matrix

AT91SAM9XE128/256/512 Preliminary

• 6-layer Matrix, handling requests from 6 masters

• Programmable Arbitration strategy

– Fixed-priority Arbitration

6254A–ATARM–01-Feb-08

7.2.1 Matrix Masters

AT91SAM9XE128/256/512 Preliminary

– Round-Robin Arbitration, either with no default master, last accessed default master

or fixed default master

• Burst Management

– Breaking with Slot Cycle Limit Support – Undefined Burst Length Support

• One Address Decoder provided per Master

– Three different slaves may be assigned to each decoded memory area: one for

internal ROM boot, one for internal flash boot, one after remap

• Boot Mode Select

– Non-volatile Boot Memory can be internal ROM or internal Flash – Selection is made by General purpose NVM bit sampled at reset

• Remap Command

– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory

(ROM or Flash)

– Allows Handling of Dynamic Exception Vectors

The Bus Matrix of the AT91SAM9XE128/256/512 manages six Masters, thus each master can perform an access concurrently with others, depending on whether the slave it accesses is available.

7.2.2 Matrix Slaves

Each Master has its own decoder, which can be defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.

Table 7-1. List of Bus Matrix Masters

Master 0 ARM926™ Instruction

Master 1 ARM926 Data

Master 2 Peripheral DMA Controller

Master 3 USB Host Controller

Master 4 Image Sensor Controller

Master 5 Ethernet MAC

Each Slave has its own arbiter, thus allowing a different arbitration per Slave to be programmed.

Table 7-2. List of Bus Matrix Slaves

Slave 0 Internal Flash

Slave 1 Internal SRAM

Internal ROM

Slave 2

USB Host User Interface

Slave 3 External Bus Interface

Slave 4 Reserved

Slave 5 Internal Peripherals

6254A–ATARM–01-Feb-08

7.2.3 Masters to Slaves Access

All the Masters can normally access all the Slaves. However, some paths do not make sense, such as allowing access from the Ethernet MAC to the internal peripherals.

Thus, these paths are forbidden or simply not wired, and shown as “–” in the following table.

Table 7-3. AT91SAM9XE128/256/512 Masters to Slaves Access

Master 0 and 1 2 3 4 5

ARM926 Instruction

Slave 0 Internal Flash X – – X 1 Internal SRAM X X X X X

Internal ROM X X – – –

UHP User Interface X – – – –

3 External Bus Interface X X X X X 4 Reserved – ––––

Internal Peripherals X X – – –

and Data

Periphera DMA

Controller

ISI Controller Ethernet MAC USB Host

Controller

7.3 Peripheral DMA Controller

• Acting as one Matrix Master

• Allows data transfers from/to peripheral to/from any memory space without any intervention of the processor.

• Next Pointer Support, forbids strong real-time constraints on buffer management.

• Twenty-four channels

– Two for each USART – Two for the Debug Unit – Two for each Serial Synchronous Controller – Two for each Serial Peripheral Interface – Two for the Two Wire Interface – One for Multimedia Card Interface – One for Analog To Digital Converter

The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):

– TWI0 Transmit Channel – TWI1 Transmit Channel – DBGU Transmit Channel – USART4 Transmit Channel – USART3 Transmit Channel – USART2 Transmit Channel – USART1 Transmit Channel – USART0 Transmit Channel

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AT91SAM9XE128/256/512 Preliminary

– SPI1 Transmit Channel – SPI0 Transmit Channel – SSC Transmit Channel – TWI0 Receive Channel – TWI1 Receive Channel – DBGU Receive Channel – USART4 Receive Channel – USART3 Receive Channel – USART2 Receive Channel – USART1 Receive Channel – USART0 Receive Channel – ADC Receive Channel – SPI1 Receive Channel – SPI0 Receive Channel – SSC Receive Channel – MCI Transmit/Receive Channel

7.4 Debug and Test Features

• ARM926 Real-time In-circuit Emulator

– Two real-time Watchpoint Units – Two Independent Registers: Debug Control Register and Debug Status Register – Test Access Port Accessible through JTAG Protocol – Debug Communications Channel

• Debug Unit

–Two-pin UART – Debug Communication Channel Interrupt Handling – Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on All Digital Pins

6254A–ATARM–01-Feb-08

8. Memories

Figure 8-1. AT91SAM9XE128/256/512 Memory Mapping

0x0000 0000

0x0FFF FFFF

0x1000 0000

0x1FFF FFFF

0x2000 0000

0x2FFF FFFF

0x3000 0000

0x3FFF FFFF

0x4000 0000

0x4FFF FFFF

0x5000 0000

0x5FFF FFFF

0x6000 0000

0x6FFF FFFF

0x7000 0000

0x7FFF FFFF

0x8000 0000

0x8FFF FFFF

0x9000 0000

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

Address Memory Space

Internal Memories

EBI

Chip Select 0

EBI

Chip Select 1/

SDRAMC

EBI

Chip Select 2

EBI

Chip Select 3/

NANDFlash

EBI

Chip Select 4/

Compact Flash

Slot 0

EBI

Chip Select 5/

Compact Flash

Slot 1

EBI

Chip Select 6

EBI

Chip Select 7

Undefined

(Abort)

Internal Peripherals

256M Bytes

1,518M Bytes

256M Bytes

0x0000 0000

0x0FFF FFFF

0xF000 0000

0xFFFA 0000

0xFFFA 4000

0xFFFA 8000

0xFFFA C000

0xFFFB 0000

0xFFFB 4000

0xFFFB 8000

0xFFFB C000

0xFFFC 0000

0xFFFC 4000

0xFFFC 8000

0xFFFC C000

0xFFFD 0000

0xFFFD 4000

0xFFFD 8000

0xFFFD C000

0xFFFE 0000

0xFFFE 4000

0xFFFF C000

0xFFFF FFFF

Internal Memory Mapping

0x10 0000

0x10 8000

0x20 0000

0x28 0000

0x30 0000

0x30 8000

0x50 0000

0x50 4000

Peripheral Mapping

Reserved

TCO, TC1, TC2

TC3, TC4, TC5

Reserved

Boot Memory (1)

ROM

Reserved

Flash

Reserved

SRAM

Reserved

UHP

Reserved

UDP

MCI

TWI0

USART0

USART1

USART2

SSC

ISI

EMAC

SPI0

SPI1

USART3

USART4

TWI1

ADC

SYSC

32K Bytes

128, 256 or 512K Bytes

32K Bytes

16K Bytes

(1) Can be ROM or Flash

Notes :

depending on GPNVM[3]

System Controller Mapping

0xFFFF C000

0xFFFF E800

0xFFFF EA00

0xFFFF EC00

0xFFFF EE00

0xFFFF EF10 0xFFFF F000

0xFFFF F200

0xFFFF F400

0xFFFF F600

0xFFFF F800

0xFFFF FA00

0xFFFF FC00

0xFFFF FD00

0xFFFF FD10 0xFFFF FD20

0xFFFF FD30

0xFFFF FD40

0xFFFF FD50 0xFFFF FD60

0xFFFF FFFF

Reserved

ECC 512 Bytes

512 BytesSDRAMC

512 BytesSMC

MATRIX

CCFG

AIC

DBGU

PIOA

PIOB

PIOC

EEFC

PMC

RSTC

SHDC

RTTC

PITC

WDTC GPBR

Reserved

512 Bytes

512 bytes

256 Bytes

16 Bytes 16 Bytes

16 Bytes

16 Bytes 16 Bytes

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional features.

Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. The bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master requesting such an access.

Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding.

Regarding Master 0 and Master 1 (ARM926 Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap, refer to Table 8-3, “Internal Memory Mapping,” on page 27 for details.

A complete memory map is presented in Figure 8-1 on page 22.

8.1 Embedded Memories

8.1.1 AT91SAM9XE128

• 32 KB ROM

– Single Cycle Access at full matrix speed

• 16 KB Fast SRAM

– Single Cycle Access at full matrix speed

• 128 KB Embedded Flash

8.1.2 AT91SAM9XE256

• 32 KB ROM

– Single Cycle Access at full matrix speed

• 32 KB Fast SRAM

– Single Cycle Access at full matrix speed

• 256 KB Embedded Flash

8.1.3 AT91SAM9XE512

• 32 KB ROM

– Single Cycle Access at full matrix speed

• 32 KB Fast SRAM

– Single Cycle Access at full matrix speed

• 512 KB Embedded Flash

8.1.4 ROM Topology

6254A–ATARM–01-Feb-08

The embedded ROM contains the Fast Flash Programming and the SAM-BA boot programs. Each of these two programs is stored at 16 KB Boundary and the program executed at address

zero depends on the combination of the TST pin and PA0 to PA2 pins. Figure 8-2 shows the contents of the ROM and the program available at address zero.

Figure 8-2. ROM Boot Memory Map

0x0000 0000

SAM-BA Program

FFPI

Program

0x0000 7FFF

ROM

8.1.4.1 Fast Flash Programming Interface

The Fast Flash Programming Interface programs the device through a serial JTAG interface or a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 is tied low.

0x0000 0000

0x0000 3FFF

SAM-BA Program

TST=0

0x0000 0000

FFPI

Program

0x0000 3FFF

TST=1

PA0=1 PA1=1 PA2=0

8.1.4.2 SAM-BA

Table 8-1. Signal Description

Signal Name PIO Type Active Level Comments

PGMEN0 PA0 Input High Must be connected to VDDIO

PGMEN1 PA1 Input High Must be connected to VDDIO

PGMEN2 PA2 Input Low Must be connected to GND

PGMNCMD PA4 Input Low Pulled-up input at reset

PGMRDY PA5 Output High Pulled-up input at reset

PGMNOE PA6 Input Low Pulled-up input at reset

PGMNVALID PA7 Output Low Pulled-up input at reset

PGMM[3:0] PA8..PA10 Input Pulled-up input at reset

PGMD[15:0] PA12..PA27 Input/Output Pulled-up input at reset

Boot Assistant

The SAM-BA Boot Assistant is a default Boot Program that provides an easy way to program in situ the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication through the DBGU or through the USB Device Port.

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

• Communication through the DBGU supports a wide range of crystals from 3 to 20 MHz via software auto-detection.

• Communication through the USB Device Port is depends on crystal selected:

– limited to an 18,432 Hz crystal if the internal RC oscillator is selected – supports a wide range of crystals from 3 to 20 MHz if the 32,768 Hz crystal is

selected

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

8.1.5 Embedded Flash

The Flash of the AT91SAM9XE128/256/512 is organized in 256/512/1024 pages of 512 bytes directly connected to the 32-bit internal bus. Each page contains 128 words.

The Flash contains a 512-byte write buffer allowing the programming of a page. This buffer is write-only as 128 32-bit words, and accessible all along the 1 MB address space, so that each word can be written at its final address.

The Flash benefits from the integration of a power reset cell and from a brownout detector to prevent code corruption during power supply changes, even in the worst conditions.

8.1.5.1 Enhanced Embedded Flash Controller

The Enhanced Embedded Flash Controller (EEFC) is continuously clocked.

8.1.5.2 Lock Regions

The Enhanced Embedded Flash Controller (EEFC) is a slave for the bus matrix and is configurable through its User Interface on the APB bus. It ensures the interface of the Flash block with the 32-bit internal bus. Its 128-bit wide memory interface increases performance, four 32-bit data are read during each access, this multiply the throughput by 4 in case of consecutive data.

It also manages the programming, erasing, locking and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash descriptor definition that informs the system about the Flash organization, thus making the software generic programming of the access parameters of the Flash (number of wait states, timings, etc.)

The memory plane of 128, 256 or 512 Kbytes is organized in 8, 16 or 32 locked regions of 32 pages each. Each lock region can be locked independently, so that the software protects the first memory plane against erroneous programming:

If a locked-regions erase or program command occurs, the command is aborted and the EEFC could trigger an interrupt.

The Lock bits are software programmable through the EEFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

6254A–ATARM–01-Feb-08

Figure 8-3. Flash First Memory Plane Mapping

0x0020 0000

Locked Regions Area

128, 256 or 512 Kbytes

256, 512 or 1024 Pages

Page 0Locked Region 0

Page 31

512 bytes

0x0021 FFFF or 0x0023 FFFF or 0x0027 FFFF

8.1.5.3 GPNVM Bits

8.1.5.4 Security Bit

Locked Region 7, 15 or 31

32 bits wide

16 KBytes

The AT91SAM9XE128/256/512 features four GPNVM bits that can be cleared or set respectively through the commands “Clear GPNVM Bit” and “Set GPNVM Bit” of the EEFC User Interface.

Table 8-2. General-purpose Non volatile Memory Bits

GPNVMBit[#] Function

0 Security Bit

1 Brownout Detector Enable

2 Brownout Detector Reset Enable

3 Boot Mode Select (BMS)

The AT91SAM9XE128/256/512 features a security bit, based on a specific GPNVM bit, GPNVMBit[0]. When the security is enabled, access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden. This ensures the confidentiality of the code programmed in the Flash.

Disabling the security bit can only be achieved by asserting the ERASE pin at 1, and after a full Flash erase is performed. When the security bit is deactivated, all accesses to the Flash are permitted.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation.

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

AT91SAM9XE128/256/512 Preliminary

8.1.5.5 Non-volatile Brownout Detector Control

Two GPNVM bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

• GPNVMBit[1] is used as a brownout detector enable bit. Setting GPNVMBit[1] enables the BOD, clearing it disables the BOD. Asserting ERASE clears GPNVMBit[1] and thus disables the brownout detector by default.

• GPNVMBit[2] is used as a brownout reset enable signal for the reset controller. Setting GPNVMBit[2] enables the brownout reset when a brownout is detected, clearing GPNVMBit[2] disables the brownout reset. Asserting ERASE disables the brownout reset by default.

8.1.6 Boot Strategies

Table 8-3 summarizes the Internal Memory Mapping for each Master, depending on the Remap

status and the GPNVMBit[3] state at reset.

Table 8-3. Internal Memory Mapping

Address

0x0000 0000 ROM Flash SRAM

REMAP = 0 REMAP = 1

GPNVMBit[3] clear GPNVMBit[3] set

The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters.

REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. Refer to the section “AT91SAM9XE Bus Matrix” in the product datasheet for more details.

When REMAP = 0, a non volatile bit stored in Flash memory (GPNVMBit[3]) allows the user to lay out to 0x0, at his convenience, the ROM or the Flash. Refer to the section “Enhanced Embedded Flash Controller (EEFC)” in the product datasheet for more details.

Note: Memory blocks not affected by these parameters can always be seen at their specified base

addresses. See the complete memory map presented in Figure 8-1 on page 22.

The AT91SAM9XE Matrix manages a boot memory that depends on the value of GPNVMBit[3] at reset. The internal memory area mapped between address 0x0 and 0x0FFF FFFF is reserved for this purpose.

If GPNVMBit[3] is set, the boot memory is the internal Flash memory

If GPNVMBit[3] is clear (Flash reset State), the boot memory is the embedded ROM. After a Flash erase, the boot memory is the internal ROM.

8.1.6.1 GPNVMBit[3] = 0, Boot on Embedded ROM

The system boots using the Boot Program.

• Boot on slow clock (On-chip RC or 32,768 Hz)

• Auto baudrate detection

• SAM-BA Boot in case no valid program is detected in external NVM, supporting

– Serial communication on a DBGU – USB Device Port

6254A–ATARM–01-Feb-08

8.1.6.2 GPNVMBit[3] = 1, Boot on Internal Flash

• Boot on slow clock (On-chip RC or 32,768 Hz)

The customer-programmed software must perform a complete configuration.

To speed up the boot sequence when booting at 32 kHz, the user must take the following steps:

1. Program the PMC (main oscillator enable or bypass mode)

2. Program and start the PLL

3. Switch the main clock to the new value.

8.2 External Memories

The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256 MB memory area assigned.

Refer to the memory map in Figure 8-1 on page 22.

8.2.1 External Bus Interface

• Integrates three External Memory Controllers:

– Static Memory Controller – SDRAM Controller – ECC Controller

• Additional logic for NANDFlash

• Full 32-bit External Data Bus

• Up to 26-bit Address Bus (up to 64 MB linear)

• Up to 8 chip selects, Configurable Assignment:

– Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2 – Static Memory Controller on NCS3, Optional NAND Flash support – Static Memory Controller on NCS4 - NCS5, Optional CompactFlash support – Static Memory Controller on NCS6-NCS7

8.2.2 Static Memory Controller

• 8-, 16- or 32-bit Data Bus

• Multiple Access Modes supported

– Byte Write or Byte Select Lines – Asynchronous read in Page Mode supported (4- up to 32-byte page size)

• Multiple device adaptability

– Compliant with LCD Module – Control signals programmable setup, pulse and hold time for each Memory Bank

• Multiple Wait State Management

– Programmable Wait State Generation – External Wait Request – Programmable Data Float Time

• Slow Clock mode supported

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

8.2.3 SDRAM Controller

• Supported devices:

• Numerous configurations supported

• Programming facilities

• Energy-saving capabilities

• Error detection

• SDRAM Power-up Initialization by software

• CAS Latency of 1, 2 and 3 supported

• Auto Precharge Command not used

AT91SAM9XE128/256/512 Preliminary

– Standard and Low Power SDRAM (Mobile SDRAM)

– 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path

– Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable

– Self-refresh, power down and deep power down modes supported

– Refresh Error Interrupt

8.2.4 Error Corrected Code Controller

• Hardware error corrected code generation

– Detection and correction by software

• Supports NAND Flash and SmartMedia devices with 8- or 16-bit data path

• Supports NAND Flash and SmartMedia with page sizes of 528,1056, 2112 and 4224 bytes specified by software

• Supports 1 bit correction for a page of 512, 1024, 2112 and 4096 bytes with 8- or 16-bit data path

• Supports 1 bit correction per 512 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path

• Supports 1 bit correction per 256 bytes of data for a page size of 512, 2048 and 4096 bytes with 8-bit data path

6254A–ATARM–01-Feb-08

9. System Controller

The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.

The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure the EBI chip select assignment and voltage range for external memories.

The System Controller’s peripherals are all mapped within the highest 16 KB of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF.

However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction have an indexing mode of ±4 KB.

Figure 9-1 on page 31 shows the System Controller block diagram.

Figure 8-1 on page 22 shows the mapping of the User Interfaces of the System Controller

peripherals.

AT91SAM9XE128/256/512 Preliminary

6254A–ATARM–01-Feb-08

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