ATMEL AT91SAM9RL64 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Incorporates the ARM926EJ-S
– DSP Instruction Extensions
– ARM Jazelle
– 4 Kbyte Data Cache, 4 Kbyte Instruction Cache, Write Buffer
– 210 MIPS at 190 MHz
– Memory Management Unit
– EmbeddedICE
– Mid-level implementation Embedded Trace Macrocell™
• Multi-layer AHB Bus Matrix for Large Bandwidth Transfers
– Six 32-bit-layer Matrix
– Boot Mode Select Option, Remap Command
• One 32-KByte internal ROM, Single-cycle Access at Maximum Speed
• One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed
– 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB
Bus Matrix
– Single-cycle Accessible on AHB Bus at Bus Speed
– Single-cycle Accessible on TCM Interface at Processor Speed
• 2-channel DMA
– Memory to Memory Transfer
– 16 Bytes FIFO
– LInked List
• External Bus Interface (EBI)
– EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
CompactFlash
• LCD Controller (for AT91SAM9RL64 only)
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen
Support
• High Speed (480 Mbit/s) USB 2.0 Device Controller
– On-Chip High Speed Transceiver, UTMI+ Physical Interface
– Integrated FIFOs and Dedicated DMA
– 4 Kbyte Configurable Integrated DPRAM
• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock
• Reset Controller (RSTC)
– Based on Two Power-on Reset Cells
– Reset Source Identification and Reset Output Control
• Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 12 MHz On-chip Oscillator for Main System Clock and USB Clock
®
Technology for Java® Acceleration
™
In-circuit Emulation, Debug Communication Channel Support
®
™
ARM® Thumb® Processor
AT91 ARM
Thumb
Microcontrollers
AT91SAM9R64
AT91SAM9RL64
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6289BS–ATARM–07-Oct-08
– One PLL up to 240 MHz
– One PLL 480 MHz Optimized for USB HS
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• Real-time Clock (RTC)
– Time, Date and Alarm 32-bit Parallel Load
– Low Power Consumption
– Programmable Periodic Interrupt
• One 6-channel 10-Bit Analog-to-Digital Converter
– Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels
• Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• 22-channel Peripheral DMA Controller (PDC)
• One MultiMedia Card Interface (MCI)
™
– SDCard/SDIO 1.0 and MultiMediaCard
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
3.1 Compliant
• Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
®
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– High-speed Synchronous Communications
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• Two Two-wire Interfaces (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
2
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
(TWI0 only)
• SAM-BA
• IEEE
• Required Power Supplies:
• Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
1. Description
®
Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
®
1149.1 JTAG Boundary Scan on All Digital Pins
– 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with
a large fast SRAM and a wide range of peripherals.
The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller
(for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two
SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides touch
screen management.
The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External
Bus Interface capable of interfacing with a wide range of memory and peripheral devices.
Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the
features and signals of AT91SAM9RL64 that are not available or partially available for
AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified.
Table 1-1. Unavailable or Partially Available Features and Signals in AT91SAM9R64
Feature Full/Partial Signal Peripheral A Peripheral B
AC97 Full
EBI Partial
AC97FS
AC97CK
AC97TX
AC97RX
D16-D31
NCS2
NCS5/CFCS1
PD1
PD2
PD3
PD4
PB16-PB31
PD0
PD13
-
-
6289BS–ATARM–07-Oct-08
3
Table 1-1. Unavailable or Partially Available Features and Signals in AT91SAM9R64
Feature Full/Partial Signal Peripheral A Peripheral B
LCDMOD
LCDCC
LCDVSYNC
LCDC Full
PWM Partial PWM2 PD5 and PD12 -
SPI Partial
SSC1 Full
LCDHSYNC
LCDDOTCK
LCDDEN
LCDD0-LCDD23
NPCS2
NPCS3
RF1
RK1
TD1
RD1
TK1
TF1
PC2
PC3
PC4
PC5
PC6
PC7
PC8-PC31
PD8
-
-
PD9 and PD13
PA 8
PA 9
PA 1 3
PA 1 4
PA 2 9
PA 3 0
Touchscreen
ADC
TC Partial
TWI Full
USART0 Partial
USART1 Partial SCK1 - PD2
USART2 Partial
Partial
AD3YM
GPAD4
GPAD5
TIOA1
TIOB1
TCLK1
TIOA2
TIOB2
TWD1
TWCK1
SCK0
RTS0
CTS0
DSR0
DTR0
DCD0
RI0
SCK2
RTS2
CTS2
PA 20
PD6
PD7
-
PD10
PD11
PA 8
PA 9
PA 10
PD14
PD15
PD16
PD17
PD9
PA 29
PA 30
-
PC29
PC30
PC31
PD10
PD11
-
-
-
SCK3
USART3 Partial
4
AT91SAM9R64/RL64 Preliminary
RTS3
CTS3
-
PA 2 0
PD3
PD4
6289BS–ATARM–07-Oct-08
6289BS–ATARM–07-Oct-08
AIC
D0-D15
A0/NBS0
A2-A15
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
FIQ
IRQ
PLLRCA
DRXD
DTXD
APB
PLLA
A1/NBS2/NWR2
TST
PCK0-PCK1
System Controller
VDDBU
SHDN
WKUP
XIN
NRST
NANDOE, NANDWE
PMC
UPLL
XOUT
WDT
RTT
32 kHz
OSC
XIN32
XOUT32
SHDC
RSTC
DBGU
SLAVEMASTER
PDC
4
GPBREG
A23-A24, A18-A20
A25/CFRNW
NCS4/CFCS0
NWAIT
CFCE1-CFCE2
EBI
Static
Memory
Controller
CompactFlash
NAND Flash
& ECC
NCS3/NANDCS
TWI0
USART0
USART1
USART2
USART3
PWM
TC0
TC1
TC2
SSC0
PDC
Peripheral
DMA
Controller
Peripheral
Bridge
ROM
32K Bytes
2-channel
DMA
12 MHz
OSC
USB
Device
HS
3-channel 10-bit ADC
PDC
SDRAM
Controller
DA0-DA3
CDA
CK
TWD0
TWCK0
CTS1
RTS1
RXD0-RXD3
TXD0-TXD3
NPCS0-NPCS1
SPCK
MOSI
MISO
TIOA0
TIOB0
TK0
TF0
TD0
RD0
RF0
RK0
TSADTRG
AD0
TSADVREF
VDDANA
GNDAN
SRAM
64K Bytes
HS UTMI
Transceiver
POR
ARM926EJ-S Processor
JTAG Selection and Boundary Scan
In-Circuit Emulator
TDI
TDO
TMS
TCK
JTAGSEL
I
RTCK
ICache
4 Kbytes
DCache
4 Kbytes
BMS
RTC
RC
TCM
Interface
ITCM DTCM
A21/NANDALE
A22/NANDCLE
POR
VDDCORE
AD1
PDC
AD2
5-layer AHB Bus Matrix
D
PIT
PIOA
PIOC
PIOD
PIOB
PDC
PDC
PDC
DMA
VBG
DFSDP
DFSDM
DHSDP
DHSDM
GNDUTMI
VDDUTMII
VDDUTMIC
PWM1
TCLK0
TCLK2
PWM3
PWM0
SPI
MCI
NTRST
Figure 2-1. AT91SAM9R64 Block Diagram
2. Block Diagrams
AT91SAM9R64/RL64 Preliminary
5
6
AIC
D0-D15
A0/NBS0
A2-A15
A16/BA0
A17/BA1
NCS0
NCS1/SDCS
NRD/CFOE
NWR0/NWE/CFWE
NWR1/NBS1/CFIOR
NWR3/NBS3/CFIOW
SDCK, SDCKE
RAS, CAS
SDWE, SDA10
FIQ
IRQ
PLLRCA
DRXD
DTXD
APB
PLLA
A1/NBS2/NWR2
TST
PCK0-PCK1
System Controller
VDDBU
SHDN
WKUP
XIN
NRST
NANDOE, NANDWE
PMC
UPLL
XOUT
WDT
RTT
OSC
32K
XIN32
XOUT32
SHDC
RSTC
DBGU
SLAVEMASTER
PDC
4
GPBREG
A23-A24 A18-A20
NCS5/CFCS1
A25/CFRNW
NCS4/CFCS0
D16-D31
NWAIT
CFCE1-CFCE2
EBI
Static
Memory
Controller
CompactFlash
NAND Flash
& ECC
NCS2
NCS3/NANDCS
MCI
TWI0
USART0
USART1
USART2
USART3
SPI
PWM
TC0
TC1
TC2
AC97
PDC
SSC0
SSC1
PDC
Peripheral
DMA
Controller
Peripheral
Bridge
ROM
32K Bytes
2-channel
DMA
OSC
12M
USB
Device
HS
6-channel 10-bit ADC
PDC
SDRAM
Controller
DA0-DA3
CDA
CK
TWD0
TWCK0
CTS0-CTS3
RTS0-RTS3
SCK0-SCK3
RXD0-RXD3
TXD0-TXD3
NPCS0-NPCS3
SPCK
MOSI
MISO
PWM0-PWM3
TCLK0-TCLK2
TIOA0-TIOA2
TIOB0-TIOB2
AC97CK
AC97FS
AC97RX
AC97TX
TK0-TK1
TF0-TF1
TD0-TD1
RD0-RD1
RF0-RF1
RK0-RK1
TSADTRG
AD0X
P
TSADVREF
VDDANA
GNDAN
VBG
DFSDP
DFSDM
LCDC
SRAM
64K Bytes
HS UTMI
Transceiver
POR
DHSDP
DHSDM
GNDUTMI
VDDUTMII
ARM926EJ-S Processor
JTAG Selection and Boundary Scan
In-Circuit Emulator
TDI
TDO
TMS
TCK
JTAGSEL
I
RTCK
ICache
4 Kbytes
DCache
4 Kbytes
BMS
NTRST
RTC
RC
TCM
Interface
ITCM DTCM
A21/NANDALE
A22/NANDCLE
POR
VDDCORE
AD1X
M
Touch
Screen
Controller
GPAD4
GPAD5
DCD0
DSR0
DTR0
RI0
PDC
AD2Y
P
AD3Y
M
TWI1
TWD1
TWCK1
6-layer AHB Bus Matrix
D
DMA
PIT
PIOA
PIOC
PIOD
PIOB
PDC
PDC
PDC
DMA
VDDUTMIC
LCDD0-LCDD23
LCDVSYNC
LCDHSYNC
LCDDOTCK
LDDEN
LCDCC
LCDPWR
LCDMOD
AT91SAM9R64/RL64 Preliminary
Figure 2-2. AT91SAM9RL64 Block Diagram
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
3. Signal Description
Table 3-1 gives details on the signal name classified by peripheral.
Table 3-1. Signal Description List
Active
Signal Name Function Type
Power Supplies
VDDIOM EBI I/O Lines Power Supply Power 1.65V to 3.6V
VDDIOP Peripherals I/O Lines Power Supply Power 3.0V to 3.6V
VDDUTMII USB UTMI+ Interface Power Supply Power 3.0V to 3.6V
VDDUTMIC USB UTMI+ Core Power Supply Power 1.08V to 1.32V
GNDUTMI USB UTMI Ground Ground
VDDBU Backup I/O Lines Power Supply Power 1.08V to 1.32V
GNDBU Backup Ground Ground
VDDPLLA PLL Power Supply Power 3.0V to 3.6V
GNDPLLA PLL Ground Ground
VDDPLLB UTMI PLL and OSC 12M Power Supply Power 1.08 V to 1.32V
GNDPLLB UTMI PLL and OSC 12M Ground Ground
VDDANA ADC Analog Power Supply Power 3.0V to 3.6V
GNDANA ADC Analog Ground Ground
VDDCORE Core Chip Power Supply Power 1.08V to 1.32V
GNDCORE Ground Ground
GND Ground Ground
Clocks, Oscillators and PLLs
XIN Main Oscillator Input Input
XOUT Main Oscillator Output Output
XIN32 Slow Clock Oscillator Input Input
XOUT32 Slow Clock Oscillator Output Output
VBG Bias Voltage Reference Analog
PLLRCA PLL A Filter Input
PCK0 - PCK1 Programmable Clock Output Output
Shutdown, Wakeup Logic
SHDN Shutdown Control Output
WKUP Wake-Up Input Input Accept between 0V and VDDBU
ICE and JTAG
TCK Test Clock Input No pull-up resistor
TDI Test Data In Input No pull-up resistor
TDO Test Data Out Output
TMS Test Mode Select Input No pull-up resistor
JTAGSEL JTAG Selection Input Pull-down resistor
Level Comments
Driven at 0V only.
0: The device is in backup mode.
1: The device is running (not in backup mode.)
6289BS–ATARM–07-Oct-08
7
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
NTRST Test Reset Signal Input Low Pull-up resistor.
Reset/Test
NRST Microcontroller Reset I/O Low Pull-up resistor
TST Test Mode Select Input Pull-down resistor
BMS Boot Mode Select Input
Debug Unit - DBGU
DRXD Debug Receive Data Input
DTXD Debug Transmit Data Output
Advanced Interrupt Controller - AIC
IRQ External Interrupt Input Input
FIQ Fast Interrupt Input Input
PIO Controller - PIOA - PIOB - PIOC-PIOD
PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset
PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset
PC0 - PC31 Parallel IO Controller C I/O Pulled-up input at reset
PD0 - PD21 Parallel IO Controller D I/O Pulled-up input at reset
External Bus Interface - EBI
D0 - D31 Data Bus I/O
A0 - A25 Address Bus Output 0 at reset
NWAIT External Wait Signal Input Low
Static Memory Controller - SMC
NCS0 - NCS5 Chip Select Lines Output Low NCS2, NCS5 not present on AT91SAM9R64.
NWR0 - NWR3 Write Signal Output Low
NRD Read Signal Output Low
NWE Write Enable Output Low
NBS0 - NBS3 Byte Mask Signal Output Low
CompactFlash Support
CFCE1 - CFCE2 CompactFlash Chip Enable Output Low
CFOE CompactFlash Output Enable Output Low
CFWE CompactFlash Write Enable Output Low
CFIOR CompactFlash IO Read Output Low
CFIOW CompactFlash IO Write Output Low
CFRNW CompactFlash Read Not Write Output
CFCS0 - CFCS1 CompactFlash Chip Select Lines Output Low CFCS1 not present on AT91SAM9R64.
Level Comments
Must be connected to GND or VDDIOP.
No pullup resistor
BMS = 0 when tied to GND
BMS = 1 when tied to VDDIOP
Pulled-up input at reset. D16-D31 not present
on AT91SAM9R64.
8
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
NAND Flash Support
NANDCS NAND Flash Chip Select Output Low
NANDOE NAND Flash Output Enable Output Low
NANDWE NAND Flash Write Enable Output Low
SDRAM Controller
SDCK SDRAM Clock Output
SDCKE SDRAM Clock Enable Output High
SDCS SDRAM Controller Chip Select Output Low
BA0 - BA1 Bank Select Output
SDWE SDRAM Write Enable Output Low
RAS - CAS Row and Column Signal Output Low
SDA10 SDRAM Address 10 Line Output
Multimedia Card Interface MCI
CK Multimedia Card Clock I/O
CDA Multimedia Card Slot A Command I/O
DA0 - DA3 Multimedia Card Slot A Data I/O
Universal Synchronous Asynchronous Receiver Transmitter USARTx
SCKx USARTx Serial Clock I/O SCKx not present on AT91SAM9R64.
TXDx USARTx Transmit Data I/O
RXDx USARTx Receive Data Input
RTSx USARTx Request To Send Output
CTSx USARTx Clear To Send Input
DTR0 USART0 Data Terminal Ready I/O Not present on AT91SAM9R64.
DSR0 USART0 Data Set Ready Input Not present on AT91SAM9R64.
DCD0 USART0 Data Carrier Detect Output Not present on AT91SAM9R64.
RI0 USART0 Ring Indicator Input Not present on AT91SAM9R64.
Synchronous Serial Controller - SSCx
TD0 - TD1 SSC Transmit Data Output TD1 not present on AT91SAM9R64.
RD0 - RD1 SSC Receive Data Input RD1 not present on AT91SAM9R64.
TK0 - TK1 SSC Transmit Clock I/O TK1 not present on AT91SAM9R64.
RK0 - RK1 SSC Receive Clock I/O RK1 not present on AT91SAM9R64.
TF0 - TF1 SSC Transmit Frame Sync I/O TF1 not present on AT91SAM9R64.
RF0 - RF1 SSC Receive Frame Sync I/O RF1 not present on AT91SAM9R64.
Level Comments
RTS0, RTS2, RTS3 not present on
AT91SAM9R64.
CTS0, CTS2, CTS3 not present on
AT91SAM9R64.
6289BS–ATARM–07-Oct-08
9
Table 3-1. Signal Description List (Continued)
Active
Signal Name Function Type
AC97 Controller - AC97C
AC97RX AC97 Receive Signal Input Not present on AT91SAM9R64.
AC97TX AC97 Transmit Signal Output Not present on AT91SAM9R64.
AC97FS AC97 Frame Synchronization Signal Output Not present on AT91SAM9R64.
AC97CK AC97 Clock signal Input Not present on AT91SAM9R64.
Timer/Counter - TC
TCLKx TC Channel x External Clock Input Input TCLK1 not present on AT91SAM9R64.
TIOAx TC Channel x I/O Line A I/O TIOA1, TIOA2 not present on AT91SAM9R64.
TIOBx TC Channel x I/O Line B I/O TIOB1, TIOB2 not present on AT91SAM9R64.
Pulse Width Modulation Controller- PWMC
PMWx Pulse Width Modulation Output Output PWM2 not present on AT91SAM9R64.
Serial Peripheral Interface - SPI
MISO Master In Slave Out I/O
MOSI Master Out Slave In I/O
SPCK SPI Serial Clock I/O
NPCS0 SPI Peripheral Chip Select 0 I/O Low
NPCS1 - NPCS3 SPI Peripheral Chip Select Output Low NPCS2, NPCS3 not present on AT91SAM9R64.
Two-Wire Interface - TWIx
TWDx TWIx Two-wire Serial Data I/O TWD1 not present on AT91SAM9R64.
TWCKx TWIx Two-wire Serial Clock I/O TWCK1 not present on AT91SAM9R64.
Touch Screen Analog-to-Digital Converter
GPAD0-GPAD5 Analog Inputs Analog GPAD4, GPAD5 not present on AT91SAM9R64.
AD0X
AD1X
AD2Y
AD3Y
P
M
P
M
Touch Panel Right side Analog Multiplexed with AD0
Touch Panel Left side Analog Multiplexed with AD1
Touch Panel Top side Analog Multiplexed with AD2
Touch Panel Bottom side Analog
TSADTRG ADC Trigger Input
TSADVREF ADC Reference Analog
LCD Controller - LCDC
LCDD0 - LCDD23 LCD Data Bus Output Not present on AT91SAM9R64.
LCDVSYNC LCD Vertical Synchronization Output Not present on AT91SAM9R64.
LCDHSYNC LCD Horizontal Synchronization Output Not present on AT91SAM9R64.
LCDDOTCK LCD Dot Clock Output Not present on AT91SAM9R64.
LCDDEN LCD Data Enable Output Not present on AT91SAM9R64.
LCDCC LCD Contrast Control Output Not present on AT91SAM9R64.
LCDPWR LCD panel Power enable control Output Not present on AT91SAM9R64.
LCDMOD LCD Modulation signal Output Not present on AT91SAM9R64.
Level Comments
Multiplexed with AD3. Not present on
AT91SAM9R64.
10
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
Table 3-1. Signal Description List (Continued)
Signal Name Function Type
USB High Speed Device
DFSDM USB Device Full Speed Data - Analog
DFSDP USB Device Full Speed Data + Analog
DHSDM USB Device High Speed Data - Analog
DHSDP USB Device High Speed Data + Analog
Active
Level Comments
6289BS–ATARM–07-Oct-08
11
4. Package and Pinout
BALL A1
12
1
2
3
4
5
6
7
8
9
10
11
ABCDE F GHJ KL M
The AT91SAM9R64 is available in a 144-ball BGA package. The AT91SAM9RL64 is available
in a 217-ball LFBGA package.
4.1 144-ball BGA Package Outline
Figure 4-1 shows the orientation of the 144-ball BGA package.
Figure 4-1. 144-ball BGA Pinout (Top View)
12
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
4.2 Pinout
AT91SAM9R64 Pinout for 144-ball BGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 DFSDM D1 PLLRCA G1 PB[10] K1 A[5]
A2 DHSDM D2 VDDUTMII
A3 XIN
A4 XOUT
A5 XIN32 D5 JTAGSEL
A6 XOUT32 D6 GNDBU G6 GND
A7 TDO D7 TCK G7 GND
A8 PA[31] D8 PA[26] G8 GND
A9 PA[22] D9 PA[24] G9 GNDUTMI
A10 PA[16] D10 PA[13] G10 VDDCORE
A11 PA[14] D11 PA[6] G11 VDDIOP
A12 PA[11] D12 PD[20] G12 VDDIOP K12 PB[1]
B1 DFSDP E1 GNDPLLA
B2 DHSDP
B3 NC
B4 VDDPLLB
B5 GNDPLLB
B6 TMS
B7 RTCK E7 NRST H7 GND
B8 PA[27] E8 BMS H8 GND
B9 PA[21] E9 PA[25]
B10 PA[12] E10 PA[15]
B11 PD[21] E11 PA[5] H11 VDDCORE L11 PB[0]
B12 PA[10] E12 PA[4] H12 VDDIOP L12 GNDANA
C1 VDDPLLA
C2 VBG
C3 VDDBU
C4 SHDN
C5 WKUP
C6 NTRST
C7 TDI F7 TST
C8 PA[28] F8 VDDUTMIC
C 9 PA [ 2 3] F9 PA [ 3]
C10 PA[7] F10 PA[2]
C11 PD[19] F11 PA[0]
C12 PD[18] F12 PA[1]
D3 NWR3/NBS3/CFIOW G3 PB[12] K3 A[13]
D4 NWR1/NBS1/CFIOR G4 PB[9] K4 A[15]
E2 NWR0/NWE/CFWE H2 PB[15] L2 A[8]
E3 NRD/CFOE H3 A[0] L3 A[11]
E4 NCS0 H4 A[2] L4 A[16]
E5 NCS1/SDCS H5 SDA10 L5 SDWE
E6 PB[2] H6 D[1] L6 D[4]
F1 PB[5] J1 A[4] M1 A[9]
F2 PB[6] J2 A[1] M2 A[10]
F3 PB[7] J3 A[3] M3 A[12]
F4 PB[8] J4 A[14] M4 A[17]
F5 PB[3] J5 CAS M5 D[0]
F6 PB[4] J6 D[2] M6 SDCK
G2 PB[11] K2 A[6]
G5 PB[13] K5 RAS
K6 D[3]
K7 D[6]
K8 D[13]
K9 VDDIOM
K10 VDDIOM
K11 D[11]
H1 PB[14] L1 A[7]
L7 D[7]
L8 D[15]
H9 VDDIOM L9 PC[1]
H10 SDCKE L10 PC[0]
J7 D[5] M7 D[8]
J8 D[12] M8 ADVREF
J9 D[14] M9 VDDANA
J10 VDDIOM M10 PA[17]
J11 D[10] M11 PA[18]
J12 D[9] M12 PA[19]
4.3 217-ball LFBGA Package Outline
Figure 4-2 shows the orientation of the 217-ball LFBGA package.
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13
Figure 4-2. 217-ball LFBGA Pinout (Top View)
BALL A1
12
1
2
3
4
5
6
7
8
9
10
11
13
14
15
16
17
ABCDEFGHJ KLM NPRTU
14
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
4.4 Pinout
Table 4-1. AT91SAM9RL64 Pinout for 217-ball LFBGA Package
Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name
A1 DFSDM D5 SHDN J14 PD[1] P17 PC[11]
A2 DHSDP D6 JTAGSEL J15 PD[0] R1 A[0]
A3 VDDPLLB D7 NTRST J16 PC[30] R2 A[2]
A4 XIN D8 BMS J17 PC[31] R3 A[7]
A5 XOUT D9 TDO K1 PB[14] R4 A[10]
A6 GNDPLLB D10 PA [ 3 0] K2 PB[15] R5 A[14]
A7 XOUT32 D11 GND K3 PB[17] R6 SDA10
A8 GND D12 PA [ 2 3 ] K4 PB[16] R7 D[0]
A9 NRST D13 PA [ 15 ] K8 VDDUTMIC R8 VDDIOM
A10 RTCK D14 PA[ 1 2 ] K9 VDDIOP R9 D[6]
A11 PA[29] D15 PA [ 8 ] K10 PC[28] R10 D[9]
A12 PA[26] D16 PD[13] K14 PC[25] R11 NC
A13 PA[22] D17 PD[16] K15 PC[24] R12 VDDIOM
A14 PA[14] E1 GNDPLLA K16 PC[26] R13 PC[1]
A15 PA[10] E2 NCS1/SDCS K17 PC[27] R14 PB[1]
A16 PD[20] E3 NCS0 L1 PB[18] R15 PC[5]
A17 PD[17] E4 NWR3/NBS3/CFIOW L2 PB[19] R16 PC[6]
B1 DFSDP E14 PD[15] L3 PB[21] R17 PC[7]
B2 DHSDM E15 PD[14] L4 PB[20] T1 A[3]
B3 VBG E16 PA[ 5 ] L14 PC[21] T2 A[5]
B4 NC E17 PA [4 ] L15 PC[20] T3 A[8]
B5 NC F1 NRD/CFOE L16 PC[22] T4 A[12]
B6 XIN32 F2 PB[2] L17 PC[23] T5 A[16]
B7 TST F3 NWR0/NWE/CFWE M1 PB[22] T6 RAS
B8 GND F4 PB[3] M2 PB[23] T7 D[2]
B9 TMS F14 PA [ 1] M3 PB[25] T8 D[4]
B10 VDDCORE F15 PA [0 ] M4 PB[24] T9 D[7]
B11 PA[28] F16 PA [ 2 ] M14 PC[17] T10 D[10]
B12 PA[25] F17 PA [ 3 ] M15 PC[16] T11 D[14]
B13 PA[21] G1 GND M16 PC[18] T12 VDDANA
B14 PA[13] G2 VDDIOM M17 PC[19] T13 PA [1 7 ]
B15 PD[21] G3 PB[5] N1 PB[26] T14 PA [ 19 ]
B16 PD[19] G4 PB[4] N2 PB[27] T15 PC[2]
B17 PA [ 9] G14 PD[12] N3 PB[29] T16 PC[3]
C1 VDDPLLA G15 PD[11] N4 PB[28] T17 PC[4]
C2 VDDUTMII G16 PD[10] N14 PC[13] U1 A[4]
C3 GND G17 PD[9] N15 PC[12] U2 A[6]
C4 GNDUTMI H1 PB[8] N16 PC[14] U3 A[9]
C5 VDDBU H2 PB[9] N17 PC[15] U4 A[13]
C6 WKUP H3 PB[7] P1 PB[30] U5 A[17]
C7 GNDBU H4 PB[6] P2 PB[31] U6 SDWE
C8 TCK H8 VDDCORE P3 A[1] U7 D[3]
C9 TDI H9 VDDIOP P4 A[11] U8 SDCK
C10 PA[31] H10 PD[4] P5 A[15] U9 D[11]
C11 PA[27] H14 PD[8] P6 CAS U10 D[12]
C12 PA[24] H15 PD[5] P7 D[1] U11 D[13]
C13 PA[16] H16 PD[2] P8 SDCKE U12 TSADVREF
C14 PA[11] H17 PD[3] P9 D[5] U13 PA [ 1 8]
C15 PD[18] J1 PB[12] P10 D[8] U14 PA [ 2 0 ]
C16 PA[ 7 ] J2 PB[13] P11 D[15] U15 PD[6]
C17 PA[ 6 ] J3 PB[11] P12 PC[0] U16 PD[7]
D1 PLLRCA J4 PB[10] P13 PB[0] U17 GNDANA
D2 NWR1/NBS1/CFIOR J8 VDDCORE P14 PC[8]
D3 GND J9 VDDIOP P15 PC[9]
D4 GND J10 PC[29] P16 PC[10]
(1)
Note: 1. Shaded cells define the pins powered by VDDIOM.
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5. Power Considerations
5.1 Power Supplies
The AT91SAM9R64/RL64 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V
(1.8V nominal) or between 3.0V and 3.6V (3.3V nominal).
• VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDPLLA pin: Powers the PLL cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
• VDDPLLB pin: Powers the UTMI PLL (480MHz) and OSC 12M cells; voltage ranges from
1.08V and 1.32V, 1.2V nominal.
• VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDUTMIC pin: Powers the UTMI+ core; voltage ranges from 1.08V and 1.32V, 1.2V
nominal.
• VDDANA pin: Powers the ADC cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM and VDDIOP are identified in the pinout table and the PIO multiplexing tables. These supplies enable the user to power the device differently for interfacing with
memories and for interfacing with peripherals.
5.1.1 USB
Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies.
Separated ground pins are provided for VDDBU, VDDPLLA, VDDPLLB and VDDANA. These
ground pins are respectively GNDBU, GNDPLLA, GNDPLLB and GNDANA. A common ground
pin is provided for VDDUTMII and VDDUTMIC. This ground pin is GNDUTMI.
Caution: VDDCORE and VDDIO constraints at startup to be checked in the Core Power Supply
POR Characteristics in the Electical Characteristics section of the datasheet.
Power Supply Considerations
To achieve the best performances on the UDPHS, care must be taken in the power supplies
choice and especially on VDDPLLB,VDDUTMIC and VDDUTMII.
The USB High speed requires power supplies with a ripple voltage < 20 mV on VDDPLLB and
VDDUTMIC. The VDDUTMII powering the UTMI transceiver must also be filtered.
It is highly recommended to use an LDO linear regulator to generate the 1.2 volts for both
VDDPLLB and VDDUTMIC. VDDUTMII can be connected on the 3.3 volts of the system via an
LC filter.
The figure below gives an example of VDDPLLB, VDDUTMIC and VDDUTMII.
16
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
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