• One 32-KByte internal ROM, Single-cycle Access at Maximum Speed
• One 64-KByte internal SRAM, Single-cycle Access at Maximum Speed
– 4 Blocks of 16 Kbytes Configurable in TCM or General-purpose SRAM on the AHB
Bus Matrix
– Single-cycle Accessible on AHB Bus at Bus Speed
– Single-cycle Accessible on TCM Interface at Processor Speed
• 2-channel DMA
– Memory to Memory Transfer
– 16 Bytes FIFO
– LInked List
• External Bus Interface (EBI)
– EBI Supports SDRAM, Static Memory, ECC-enabled NAND Flash and
CompactFlash
• LCD Controller (for AT91SAM9RL64 only)
– Supports Passive or Active Displays
– Up to 24 Bits per Pixel in TFT Mode, Up to 16 bits per Pixel in STN Color Mode
– Up to 16M Colors in TFT Mode, Resolution Up to 2048x2048, Virtual Screen
Support
• High Speed (480 Mbit/s) USB 2.0 Device Controller
– On-Chip High Speed Transceiver, UTMI+ Physical Interface
– Integrated FIFOs and Dedicated DMA
– 4 Kbyte Configurable Integrated DPRAM
• Fully-featured System Controller, including
– Reset Controller, Shutdown Controller
– Four 32-bit Battery Backup Registers for a Total of 16 Bytes
– Clock Generator and Power Management Controller
– Advanced Interrupt Controller and Debug Unit
– Periodic Interval Timer, Watchdog Timer and Real-time Timer and Real-time Clock
• Reset Controller (RSTC)
– Based on Two Power-on Reset Cells
– Reset Source Identification and Reset Output Control
• Shutdown Controller (SHDC)
– Programmable Shutdown Pin Control and Wake-up Circuitry
• Clock Generator (CKGR)
– Selectable 32768 Hz Low-power Oscillator or Internal Low-power RC Oscillator on
Battery Backup Power Supply, Providing a Permanent Slow Clock
– 12 MHz On-chip Oscillator for Main System Clock and USB Clock
®
Technology for Java® Acceleration
™
In-circuit Emulation, Debug Communication Channel Support
®
™
ARM® Thumb® Processor
AT91 ARM
Thumb
Microcontrollers
AT91SAM9R64
AT91SAM9RL64
Preliminary
Summary
NOTE: This is a summary document.
The complete document is available on
the Atmel website at www.atmel.com.
6289BS–ATARM–07-Oct-08
– One PLL up to 240 MHz
– One PLL 480 MHz Optimized for USB HS
• Power Management Controller (PMC)
– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities
– Two Programmable External Clock Signals
• Advanced Interrupt Controller (AIC)
– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources
– One External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected
• Debug Unit (DBGU)
– 2-wire UART and Support for Debug Communication Channel, Programmable ICE Access Prevention
– Mode for General Purpose 2-wire UART Serial Communication
• Periodic Interval Timer (PIT)
– 20-bit Interval Timer plus 12-bit Interval Counter
• Watchdog Timer (WDT)
– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock
• Real-time Timer (RTT)
– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler
• Real-time Clock (RTC)
– Time, Date and Alarm 32-bit Parallel Load
– Low Power Consumption
– Programmable Periodic Interrupt
• One 6-channel 10-Bit Analog-to-Digital Converter
– Touch Screen Interface Compatible with Industry Standard 4-wire Sensitive Touch Panels
• Four 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC and PIOD)
– 118 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os for 217-ball BGA Package
– Input Change Interrupt Capability on Each I/O Line
– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output
• 22-channel Peripheral DMA Controller (PDC)
• One MultiMedia Card Interface (MCI)
™
– SDCard/SDIO 1.0 and MultiMediaCard
– Automatic Protocol Control and Fast Automatic Data Transfers with PDC
3.1 Compliant
• Two Synchronous Serial Controllers (SSC)
– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter
– I²S Analog Interface Support, Time Division Multiplex Support
– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer
• One AC97 Controller (AC97C)
– 6-channel Single AC97 Analog Front End Interface, Slot Assigner
• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)
®
– Individual Baud Rate Generator, IrDA
– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support
Infrared Modulation/Demodulation, Manchester Encoding/Decoding
• One Master/Slave Serial Peripheral Interface (SPI)
– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects
– High-speed Synchronous Communications
• One Three-channel 16-bit Timer/Counter (TC)
– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel
– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability
• One Four-channel 16-bit PWM Controller (PWMC)
• Two Two-wire Interfaces (TWI)
– Compatible with Standard Two-wire Serial Memories
– One, Two or Three Bytes for Slave Address
2
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
– Sequential Read/Write Operations
– Master, Multi-master and Slave Mode Operation
– Bit Rate: Up to 400 Kbits
– General Call Supported in Slave Mode
– Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data Transfers in Master Mode Only
(TWI0 only)
• SAM-BA
• IEEE
• Required Power Supplies:
• Available in a 144-ball BGA (AT91SAM9R64) and a 217-ball LFBGA (AT91SAM9RL64) Package
1.Description
®
Boot Assistant
– Default Boot Program
– Interface with SAM-BA Graphic User Interface
®
1149.1 JTAG Boundary Scan on All Digital Pins
– 1.08 to 1.32V for VDDCORE, VDDUTMIC, VDDPLLB and VDDBU
– 3.0V to 3.6V for VDDPLLA, VDDANA, VDDUTMII and VDDIOP
– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM
The AT91SAM9R64/RL64 device is based on the integration of an ARM926EJ-S processor with
a large fast SRAM and a wide range of peripherals.
The AT91SAM9R64/RL64 embeds one USB Device High Speed Controller, one LCD Controller
(for AT91SAM9RL64 only), one AC97 controller, a 2-channel DMA Controller, four USARTs, two
SSCs, one SPI, two TWIs, three Timer Counter channels, a 4-channel PWM generator, one Multimedia Card interface and a 6-channel Analog-to-digital converter that also provides touch
screen management.
The AT91SAM9R64/RL64 is architectured on a 6-layer bus matrix. It also features an External
Bus Interface capable of interfacing with a wide range of memory and peripheral devices.
Some features are not available for AT91SAM9R64 in the 144-ball BGA package.
Separate block diagrams and PIO multiplexing are provided in this document. Table 1-1 lists the
features and signals of AT91SAM9RL64 that are not available or partially available for
AT91SAM9R64. When the signal is multiplexed on a PIO, the PIO line is specified.
Table 1-1.Unavailable or Partially Available Features and Signals in AT91SAM9R64
FeatureFull/PartialSignalPeripheral APeripheral B
AC97Full
EBIPartial
AC97FS
AC97CK
AC97TX
AC97RX
D16-D31
NCS2
NCS5/CFCS1
PD1
PD2
PD3
PD4
PB16-PB31
PD0
PD13
-
-
6289BS–ATARM–07-Oct-08
3
Table 1-1.Unavailable or Partially Available Features and Signals in AT91SAM9R64
Note:1. Shaded cells define the pins powered by VDDIOM.
6289BS–ATARM–07-Oct-08
15
5.Power Considerations
5.1Power Supplies
The AT91SAM9R64/RL64 has several types of power supply pins:
• VDDCORE pins: Power the core, including the processor, the embedded memories and the
peripherals; voltage ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDIOM pins: Power the External Bus Interface; voltage ranges between 1.65V and 1.95V
(1.8V nominal) or between 3.0V and 3.6V (3.3V nominal).
• VDDIOP pins: Power the Peripherals I/O lines; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDBU pin: Powers the Slow Clock oscillator and a part of the System Controller; voltage
ranges from 1.08V and 1.32V, 1.2V nominal.
• VDDPLLA pin: Powers the PLL cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
• VDDPLLB pin: Powers the UTMI PLL (480MHz) and OSC 12M cells; voltage ranges from
1.08V and 1.32V, 1.2V nominal.
• VDDUTMII pin: Powers the UTMI+ interface; voltage ranges from 3.0V and 3.6V, 3.3V
nominal.
• VDDUTMIC pin: Powers the UTMI+ core; voltage ranges from 1.08V and 1.32V, 1.2V
nominal.
• VDDANA pin: Powers the ADC cell; voltage ranges from 3.0V and 3.6V, 3.3V nominal.
The power supplies VDDIOM and VDDIOP are identified in the pinout table and the PIO multiplexing tables. These supplies enable the user to power the device differently for interfacing with
memories and for interfacing with peripherals.
5.1.1USB
Ground pins GND are common to VDDCORE, VDDIOM and VDDIOP pins power supplies.
Separated ground pins are provided for VDDBU, VDDPLLA, VDDPLLB and VDDANA. These
ground pins are respectively GNDBU, GNDPLLA, GNDPLLB and GNDANA. A common ground
pin is provided for VDDUTMII and VDDUTMIC. This ground pin is GNDUTMI.
Caution: VDDCORE and VDDIO constraints at startup to be checked in the Core Power Supply
POR Characteristics in the Electical Characteristics section of the datasheet.
Power Supply Considerations
To achieve the best performances on the UDPHS, care must be taken in the power supplies
choice and especially on VDDPLLB,VDDUTMIC and VDDUTMII.
The USB High speed requires power supplies with a ripple voltage < 20 mV on VDDPLLB and
VDDUTMIC. The VDDUTMII powering the UTMI transceiver must also be filtered.
It is highly recommended to use an LDO linear regulator to generate the 1.2 volts for both
VDDPLLB and VDDUTMIC. VDDUTMII can be connected on the 3.3 volts of the system via an
LC filter.
The figure below gives an example of VDDPLLB, VDDUTMIC and VDDUTMII.
16
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
VIN
CE
VSS
VOUT
ADJ
10µF0.1µF
10µF
MIC5235YM5
1K
100K
VIN
1V2_USB
0.1µF
1V2_USB
2.2µH
VDDPLLB
0.1µF
1V2_USB
2.2µH
VDDUTMIC
0.1µF
3V3
2.2µH
VDDUTMII
Figure 5-1.Example of PLL and USB Power Supplies
5.2Power Consumption
The AT91SAM9R64/RL64 consumes about 450 µA of static current on VDDCORE at 25°C and
up to 4 mA at 85°C.
On VDDBU, the current does not exceed 5 µA @25°C and 30 µA @85°C.
For dynamic power consumption, the AT91SAM9R64/RL64 consumes a maximum of 70 mA on
VDDCORE in worst case conditions (1.2V, 85°C, processor running full-performance algorithm).
5.3Programmable I/O Lines Power Supplies
The power supplies pins VDDIOM support two voltage ranges. This allows the device to reach
its maximum speed either out of 1.8V or 3.3V external memories.
The maximum speed is MCK on the pin SDCK (SDRAM Clock) loaded with 30pF for power supply at 1.8V and 50 pF for power supply at 3.3V.
The maximum speed on the other signals of the External Bus Interface (control, address and
data signals) is 50 MHz.
6289BS–ATARM–07-Oct-08
17
The voltage ranges are determined by programming registers in the Chip Configuration registers
located in the Matrix User Interface.
At reset, the selected voltage defaults to 3.3V nominal and power supply pins can accept either
1.8V or 3.3V. The user must make sure to program the EBI voltage range before getting the
device out of its Slow Clock Mode.
The PIO lines are supplied through VDDIOP and the speed of the signal that can be driven on
them can reach 50 MHz with 50 pF load.
6.I/O Line Considerations
6.1JTAG Port Pins
TMS, TDI and TCK are schmitt trigger inputs and have no pull-up resistors.
TDO is an output, driven at up to VDDIOP, and have no pull-up resistor.
The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level. It
integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations.
All the JTAG signals are supplied with VDDIOP except JTAGSEL supplied by VDDBU.
6.2Test Pin
The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal
operations. Driving this line at a high level leads to unpredictable results.
6.3Reset Pins
6.4PIO Controllers
This pin is supplied with VDDBU.
NRST is an open-drain output integrating a non-programmable pull-up resistor. It can be driven
with voltage at up to VDDIOP.
As the product integrates power-on reset cells, which manages the processor and the JTAG
reset, the NRST and NTRST pin can be left unconnected.
The NRST and NTRST pins integrates a permanent pull-up resistor of 100 kΩ typical to
VDDIOP.
The NRST signal is inserted in the Boundary Scan.
All the I/O lines which are managed by the PIO Controllers integrate a programmable pull-up
resistor. Refer to the section “AT91SAM9R64/RL64 Electrical Characteristics” in the product
datasheet for more details.
After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which
are multiplexed with the External Bus Interface signals that require to be enabled as Peripheral
at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing
tables.
18
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
6.5Shutdown Logic Pins
The SHDN pin is an output only, which is driven by the Shutdown Controller only at low level. It
can be tied high with an external pull-up resistor at VDDBU only.
The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU.
7.Processor and Architecture
7.1ARM926EJ-S Processor
•RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java
acceleration
•Two Instruction Sets
–ARM High-performance 32-bit Instruction Set
–Thumb High Code Density 16-bit Instruction Set
•DSP Instruction Extensions
•5-Stage Pipeline Architecture:
–Instruction Fetch (F)
–Instruction
–Execute (E)
–Data Memory (M)
–Register Write (W)
•4-Kbyte Data Cache, 4-Kbyte Instruction Cache
–Virtually-addressed 4-way Associative Cache
–Eight words per line
–Write-through and Write-back Operation
–Pseudo-random or Round-robin Replacement
•Write Buffer
–Main Write Buffer with 16-word Data Buffer and 4-address Buffer
–DCache Write-back Buffer with 8-word Entries and a Single Address Entry
–Software Control Drain
•Standard ARM v4 and v5 Memory Management Unit (MMU)
–Access Permission for Sections
–Access Permission for large pages and small pages can be specified separately for
each quarter of the page
–16 embedded domains
•Bus Interface Unit (BIU)
–Arbitrates and Schedules AHB Requests
–Separate Masters for both instruction and data access providing complete Matrix
system flexibility
–Separate Address and Data Buses for both the 32-bit instruction interface and the
32-bit data interface
–On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit
(Words)
Decode (D)
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
19
7.2Matrix Masters
7.3Matrix Slaves
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 masters, which means that
each master can perform an access concurrently with others, to an available slave.
Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the masters have the same decodings.
Table 7-1.List of Bus Matrix Masters
Master 0DMA Controller
Master 1USB Device High Speed DMA
Master 2LCD Controller DMA
Master 3Peripheral DMA Controller
Master 4ARM926™ Instruction
Master 5ARM926 Data
The Bus Matrix of the AT91SAM9R64/RL64 product manages 6 slaves. Each slave has its own
arbiter, allowing a different arbitration per slave.
Table 7-2.List of Bus Matrix Slaves
Slave 0Internal ROM
Slave 1Internal SRAM
Slave 2LCD Controller User Interface
Slave 3UDP High Speed RAM
Slave 4External Bus Interface (EBI)
Slave 5Peripheral Bridge
7.4Master to Slave Access
All the Masters can normally access all the Slaves. However, some paths do not make sense,
for example allowing access from the USB Device High speed DMA to the Internal Peripherals.
Thus, these paths are forbidden or simply not wired, and shown as “-” in the following table.
Table 7-3.AT91SAM9R64/RL64 Master to Slave Access
Masters0 1 2345
Slaves
0Internal ROMXXXXX
1Internal SRAMXXXXXX
2LCD Controller User Interface----XX
3UDP High Speed RAM----XX
4External Bus InterfaceXXXXXX
DMA
Controller
USB HS
Device DMA
LCD
Controller
DMA
Peripheral
DMA
ARM926
Instruction
ARM926
Data
5Peripheral BridgeXXX---
20
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
7.5Peripheral DMA Controller (PDC)
• Acting as one AHB Bus Matrix Master
• Allows data transfers from/to peripheral to/from any memory space without any intervention
of the processor.
• Next Pointer support, prevents strong real-time constraints on buffer management.
The Peripheral DMA Controller handles transfer requests from the channel according to the following priorities (Low to High priorities):
a. TWI0 Transmit Channel
b. DBGU Transmit Channel
c. USART3 Transmit Channel
d. USART2 Transmit Channel
e. USART1 Transmit Channel
f.USART0 Transmit Channel
g. AC97 Transmit Channel
h. SPI Transmit Channel
i.SSC1 Transmit Channel
j.SSC0 Transmit Channel
k. TWI0 Receive Channel
l.DBGU Receive Channel
m. ADC Receive Channel
n. USART3 Receive Channel
o. USART2 Receive Channel
p. USART1 Receive Channel
q. USART0 Receive Channel
r.AC97 Receive Channel
s. SPI Receive Channel
t.SSC1 Receive Channel
u. SSC0 Transmit Channel
v. MCI Receive/Transmit Channel
AT91SAM9R64/RL64 Preliminary
7.6DMA Controller
• Acting as one Matrix Master
• Embeds 2 channels
• 16 bytes/FIFO for Channel Buffering
• Linked List support with Status Write Back operation at End of Transfer
• Word, Half-word, Byte transfer support
7.7Debug and Test Features
• ARM926 Real-time In-circuit Emulator
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
6289BS–ATARM–07-Oct-08
21
– Debug Communications Channel
• Debug Unit
–Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
22
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
8.Memories
16K Bytes
0xFFFC 0000
16K Bytes
0xFFFC 4000
0xFFFC C000
SPI
16K Bytes
0xFFFC 8000
16K Bytes
16K Bytes
16K Bytes
0xFFFA 4000
TCO, TC1, TC2
0xFFFA 8000
MCI
0xFFFB 0000
0xFFFB 4000
USART0
0xFFFB C000
USART1
0xFFFA 0000
0xFFFA C000
TWI1
16K Bytes
TWI0
16K Bytes
16K Bytes
0xFFFB 8000
16K Bytes
16K Bytes
SSC1
256M Bytes
0x1000 0000
0x0000 0000
0x0FFF FFFF
0xF000 0000
0xEFFF FFFF
Address Memory Space
Internal Peripherals
Internal Memories
EBI
Chip Select 0
EBI
Chip Select 1/
SDRAMC
EBI
Chip Select 2
EBI
Chip Select 3/
NANDFlash
EBI
Chip Select 4/
Compact Flash
Slot 0
EBI
Chip Select 5/
Compact Flash
Slot 1
Undefined
(Abort)
256M Bytes
256M Bytes
256M Bytes
256M Bytes
256M Bytes
2,048M Bytes
0x2000 0000
0x1FFF FFFF
0x3000 0000
0x2FFF FFFF
0x4000 0000
0x3FFF FFFF
0x6FFF FFFF
0x6000 0000
0x5FFF FFFF
0x5000 0000
0x4FFF FFFF
0x7000 0000
256M Bytes
0xFFFF FD00
0xFFFF FC00
0xFFFF FA00
0xFFFF F800
0xFFFF F600
0xFFFF F400
0xFFFF F200
16 Bytes
256 Bytes
512 bytes
512 bytes
512 Bytes
512 Bytes
PMC
PIOC
PIOB
PIOA
DBGU
RSTC
0xFFFF F000
512 Bytes
AIC
0xFFFF EE00
512 Bytes
MATRIX
0xFFFF EC00
512 Bytes
SMC
0xFFFF FD10
16 Bytes
SHDC
0xFFFF EA00
512 Bytes
SDRAMC
0xFFFF FD20
16 Bytes
RTTC
0xFFFF FD30
16 Bytes
PITC
0xFFFF FD40
16 Bytes
WDTC
0xFFFF FD60
16 Bytes
GPBR
0xFFFF FD70
Reserved
256M Bytes
1 MBytes
0x0020 0000
SRAM(2)
0x0030 0000
0x0010 0000
0x0040 0000
UDPHS RAM
0x0050 0000
ROM
0x0FFF FFFF
Peripheral Mapping
Internal Memory Mapping
Boot Memory (1)
0x0000 0000
(1) Can be SRAM, ROM depending
on BMS and the REMAP Command
Notes :
LCD Controller
User Interface
0x0060 0000
0xFFFF C000
16K BytesSYSC
0xFFFF FFFF
0xFFFF FFFF
System Controller Mapping
0x0070 0000
Undefined
(Abort)
PWMC
AC97
ADC
1 MBytes
1 MBytes
1 MBytes
1 MBytes
0xFFFF E800
ECC
512 Bytes
0xFFFF C000
Reserved
0xFFFF FFFF
Reserved
0xF000 0000
16K Bytes
0xFFFD 0000
512 bytes
PIOD
(2) Software programmable
ITCM(2)
DTCM(2)
1 MBytes
1 MBytes
0xFFFF EF10
SSC0
USART2
UART3
0xFFFD 4000
0xFFFD 8000
UDPHS
16K Bytes
16K Bytes
16K Bytes
0xFFFD C000
TouchScreen
RTCC
0xFFFF FE00
0xFFFF E600
DMAC
512 Bytes
Reserved
Reserved
0xFFFF FD50
SCKCR
16 Bytes
128 Bytes
Figure 8-1.AT91SAM9R64/RL64 Memory Mapping
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
23
A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of
the Advanced High performance Bus (AHB) for its Master and Slave interfaces with additional
features.
Decoding breaks up the 4G bytes of address space into 16 banks of 256M bytes. The banks 1 to
8 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to
EBI_NCS5. The bank 0 is reserved for the addressing of the internal memories, and a second
level of decoding provides 1M byte of internal memory area. The bank 15 is reserved for the
peripherals and provides access to the Advanced Peripheral Bus (APB).
Other areas are unused and performing an access within them provides an abort to the master
requesting such an access.
8.1Embedded Memories
• 32 KB ROM
– Single Cycle Access at full bus speed
• 64 KB Fast SRAM
– Single Cycle Access at full bus speed
– Supports ARM926EJ-S TCM interface at full processor speed
8.1.1Internal Memory Mapping
Table 8-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap
status (RCBx bit) and the BMS state at reset.
8.1.1.1Internal SRAM
Table 8-1.Internal Memory Mapping
(1)
Address
RCBx
BMS = 1BMS =0
0x0000 0000ROMEBI_NCS0
Notes: 1. x = 0 to maximum Master number.
2. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is
defined by the reset state of SMC Setup, SMC Pulse, SMC Cycle and SMC Mode CS0
registers.
= 0RCBx
(2)
(1)
SRAM
= 1
The AT91SAM9R64/RL64 product embeds a total of 64Kbyte high-speed SRAM split in 4 blocks
of 16KBytes.
After reset and until the Remap Command is performed, the SRAM is only accessible at address
0x0030 0000.
After Remap, the SRAM also becomes available at address 0x0.
This Internal SRAM can be allocated to threes areas. Its Memory Mapping is detailed in Table 8-
2.
• Internal SRAM A is the ARM926EJ-S Instruction TCM. The user can map this SRAM block
anywhere in the ARM926 instruction memory space using CP15 instructions and the TCR
configuration register located in the Chip Configuration User Interface. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0010 0000.
24
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
• Internal SRAM B is the ARM926EJ-S Data TCM. The user can map this SRAM block
anywhere in the ARM926 data memory space using CP15 instructions. This SRAM block is
also accessible by the ARM926 Data Master and by the AHB Masters through the AHB bus
at address 0x0020 0000.
• Internal SRAM C is only accessible by all the AHB Masters. After reset and until the Remap
Command is performed, this SRAM block is accessible through the AHB bus at address
0x0030 0000 by all the AHB Masters. After Remap, this SRAM block also becomes
accessible through the AHB bus at address 0x0 by the ARM926 Instruction and the ARM926
Data Masters.
Within the 64Kbyte SRAM size available, the amount of memory assigned to each block is software programmable as a multiple of 16K Bytes according to Table 8-2. This Table provides the
size of the Internal SRAM C according to the size of the Internal SRAM A and the Internal SRAM
B.
Table 8-2.Internal SRAM Block Size
AT91SAM9R64/RL64 Preliminary
Remaining Internal SRAM C
Internal SRAM B (DTCM) size
At reset, the whole memory is assigned to Internal SRAM C.
The memory blocks assigned to SRAM A, SRAM B and SRAM C areas are not contiguous and
when the user dynamically changes the Internal SRAM configuration, the new 16-Kbyte block
organization may affect the previous configuration from a software point of view.
Table 8-3 illustrates different configurations and the related 16-Kbyte blocks (RB0 to RB3)
assignments.
Table 8-3. 16-Kbyte Block Allocation example
Configuration examples and related 16-Kbyte block assignments
Decoded
Area
Internal
SRAM A
(ITCM)
Internal
SRAM B
(DTCM)
Internal
SRAM C
(AHB)
Note:1. Configuration after reset.
Address
0x0010 0000RB1RB1RB1RB1RB1RB1
0x0010 4000RB0RB0RB0
0x0020 0000RB3RB3RB3RB3RB3RB3
0x0020 4000RB2RB2RB2
0x0030 0000RB3RB3RB3RB2RB2RB2RB1RB0
0x0030 4000RB2RB2RB2RB1RB0RB0
0x0030 8000RB1RB0RB0
0x0030 C000RB0
I = 0K
D = 0K
A = 64K
(1)
I = 16K
D = 0K
A = 48K
0
16K Bytes
32K Bytes
I =32K
D = 0K
A = 32K
I = 0K
D = 16K
A = 48K
Internal SRAM A (ITCM) Size
016K Bytes32K Bytes
64K Bytes48K Bytes32K Bytes
48K Bytes32K Bytes16K Bytes
32K Bytes16K Bytes0K Bytes
I = 16K
D = 16K
A = 32K
I = 32K
D = 16K
A = 16K
I = 0K
D = 32K
A = 32K
I = 16K
D = 32K
A = 16K
I = 32K
D = 32K
A = 0K
6289BS–ATARM–07-Oct-08
25
8.1.1.2Internal ROM
8.1.2Boot Strategies
When accessed from the AHB, the internal Fast SRAM is single cycle accessible at full matrix
speed (MCK). When accessed from the processor’s TCM Interface, they are also single cycle
accessible at full processor speed.
The AT91SAM9R64/RL64 embeds an Internal ROM, which contains the SAM-BA program.
At any time, the ROM is mapped at address 0x0040 0000. It is also accessible at address 0x0
(BMS =1) after the reset and before the Remap Command.
The system always boots at address 0x0. To ensure maximum boot possibilities, the memory
layout can be changed with two parameters.
REMAP allows the user to layout the internal SRAM bank to 0x0 to ease the development. This
is done by software once the system has boot. Refer to the Bus Matrix Section for more details.
When REMAP = 0 BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done by a hardware way at reset.
Note: All the memory blocks can always be seen at their specified base addresses that are not
concerned by these parameters.
The AT91SAM9R64/RL64 Bus Matrix manages a boot memory that depends on the level on the
pin BMS at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved to this effect.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
8.1.2.1BMS = 1, boot on embedded ROM
The system boots on Boot Program.
• Boot on on-chip RC
• Enable the 32768 Hz oscillator
• Auto baudrate detection
• Downloads and runs an application from external storage media into internal SRAM
• Downloaded code size depends on embedded SRAM size
• Automatic detection of valid application
• Bootloader on a non-volatile memory
–SDCard
–NAND Flash
– SPI DataFlash
• SAM-BA Boot in case no valid program is detected in external NVM, supporting
– Serial communication on a DBGU
– USB Device HS Port
®
connected on NPCS0 of the SPI0
8.1.2.2BMS = 0, boot on external memory
• Boot on on-chip RC
26
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
• Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit
data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory.
For optimization purposes, nothing else is done. To speed up the boot sequence user programmed software should perform a complete configuration:
• Enable the 32768 Hz oscillator if best accuracy needed
• Program the PMC (main oscillator enable or bypass mode)
• Program and Start the PLL
• Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the
new clock
• Switch the main clock to the new value
8.2External Memories
The AT91SAM9R64/RL64 features one External Bus Interface to offer interface to a wide range
of external memories and to any parallel peripheral.
8.2.1External Bus Interface
• Integrates three External Memory Controllers:
– Static Memory Controller
– SDRAM Controller
– SLC Nand Flash ECC Controller
• Additional logic for NAND Flash
• Optional Full 32-bit External Data Bus
• Up to 26-bit Address Bus (up to 64MBytes linear per chip select)
• Up to 6 chips selects, Configurable Assignment:
– Static Memory Controller on NCS0
– SDRAM Controller (SDCS) or Static Memory Controller on NCS1
– Static Memory Controller on NCS2
– Static Memory Controller on NCS3, Optional NAND Flash support
– Static Memory Controller on NCS4 - NCS5, Optional CompactFlash
AT91SAM9R64/RL64 Preliminary
and CompactFlash
TM
M
support
8.2.2Static Memory Controller
• 8-, 16- or 32-bit Data Bus
• Multiple Access Modes supported
– Byte Write or Byte Select Lines
– Asynchronous read in Page Mode supported (4- up to 32-byte page size)
• Multiple device adaptability
– Control signals programmable setup, pulse and hold time for each Memory Bank
• Multiple Wait State Management
– Programmable Wait State Generation
– External Wait Request
– Programmable Data Float Time
• Slow Clock mode supported
6289BS–ATARM–07-Oct-08
27
8.2.3SDRAM Controller
• Supported devices:
• Programming facilities
• Energy-saving capabilities
• Error detection
• SDRAM Power-up Initialization by software
• SDRAM CAS Latency of 1, 2 and 3 supported
• Auto Precharge Command not used
– Standard and Low Power SDRAM (Mobile SDRAM)
– 2K, 4K, 8K Row Address Memory Parts
– SDRAM with two or four Internal Banks
– SDRAM with 16- or 32-bit Data Path
– Word, half-word, byte access
– Automatic page break when Memory Boundary has been reached
– Multibank Ping-pong Access
– Timing parameters specified by software
– Automatic refresh operation, refresh rate is programmable
– Self-refresh, power down and deep power down modes supported
– Refresh Error Interrupt
8.2.4NAND Flash Error Corrected Code Controller
• Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select
• Single bit error correction and 2-bit Random detection.
• Automatic Hamming Code Calculation while writing
– ECC value available in a register
• Automatic Hamming Code Calculation while reading
– Error Report, including error flag, correctable error flag and word address being
detected erroneous
– Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes
pages
28
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
9.System Controller
The System Controller is a set of peripherals, which allow handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc.
The System Controller User Interface embeds also the registers allowing to configure the Matrix
and a set of registers configuring the EBI chip select assignment and the voltage range for external memories.
9.1System Controller Mapping
As shown in Figure 8-1, the System Controller’s peripherals are all mapped within the highest
16K bytes of the 4 Gbyte address space, between addresses 0xFFFF C000 and 0xFFFF FFFF.
However, all the registers of System Controller are mapped on the top of the address space.
This allows addressing all the registers of the System Controller from a single pointer by using
the standard ARM instruction set, as the Load/Store instruction have an indexing mode of +/4kbytes.
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
29
9.2Block Diagram
NRST
SLCK
Advanced
Interrupt
Controller
Real-Time
Timer
Periodic
Interval
Timer
Reset
Controller
PA0-PA31
periph_nreset
System Controller
Watchdog
Timer
wdt_fault
WDRPROC
PIO
Controllers
Power
Management
Controller
XIN
XOUT
PLLRCA
MAINCK
PLLACK
pit_irq
MCK
proc_nreset
wdt_irq
periph_irq[2..4]
periph_nreset
periph_clk[2..24]
PCK
MCK
pmc_irq
nirq
nfiq
rtt_irq
Embedded
Peripherals
periph_clk[2..4]
pck[0-1]
in
out
enable
ARM926EJ-S
SLCK
SLCK
irq
fiq
irq0-irq2
fiq
periph_irq[6..24]
periph_irq[2..24]
int
int
periph_nreset
periph_clk[6..24]
jtag_nreset
por_ntrst
proc_nreset
periph_nreset
dbgu_txd
dbgu_rxd
pit_irq
dbgu_irq
pmc_irq
rstc_irq
wdt_irq
rstc_irq
SLCK
Boundary Scan
TAP Controller
jtag_nreset
debug
PCK
debug
idle
debug
Bus Matrix
MCK
periph_nreset
proc_nreset
backup_nreset
periph_nreset
idle
Debug
Unit
dbgu_irq
MCK
dbgu_rxd
periph_nreset
dbgu_txd
rtt_alarm
Shutdown
Controller
SLCK
rtt_alarm
backup_nreset
SHDN
WKUP
4 General-purpose
Backup Registers
backup_nreset
XIN32
XOUT32
PB0-PB31
PC0-PC31
VDDBU Powered
VDDCORE Powered
ntrst
VDDCORE
POR
12MHz
MAIN OSC
PLLA
VDDBU
POR
SLOW
CLOCK
OSC
UPLL
por_ntrst
VDDBU
rtt_irq
HSCK
USB High Speed
Device
Por t
HSCK
periph_nreset
periph_irq[22]
RC
OSC
PD0-PD21
SCKCR
Real-Time
Clock
rtc_irq
SLCK
backup_nreset
rtc_alarm
rtt_alarm
rtc_alarm
periph_clk[22]
Figure 9-1.System Controller Block Diagram
30
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
9.3Reset Controller
The Reset Controller is based on two Power-on-Reset cells, one on VDDBU and one on
VDDCORE.
The Reset Controller is capable to return to the software the source of the last reset, either a
general reset (VDDBU rising), a wake-up reset (VDDCORE rising), a software reset, a user
reset or a watchdog reset.
The Reset Controller controls the internal resets of the system and the NRST pin output. It is
capable to shape a reset signal for the external devices, simplifying to a minimum connection of
a push-button on the NRST pin to implement a manual reset.
The configuration of the Reset Controller is saved as supplied on VDDBU.
9.4Shutdown Controller
The Shutdown Controller is supplied on VDDBU and allows a software-controllable shut down of
the system through the pin SHDN. An input change of the WKUP pin or an alarm releases the
SHDN pin, and thus wakes up the system power supply.
9.5Clock Generator
The Clock Generator is made up of:
AT91SAM9R64/RL64 Preliminary
• One low-power 32768 Hz Slow Clock Oscillator with bypass mode
• One low-power RC oscillator
• One 12 MHz Main Oscillator, which can be bypassed
• One 480 MHz PLL (UPLL or PLLB) providing a clock for the USB High Speed Device
Controller
• One 80 to 240 MHz programmable PLL, providing the PLL Clock (PLLCK). This PLL has an
input divider to offer a wider range of output frequencies from the 12 MHz input, the only
limitation being the lowest input frequency shall be higher or equal to 1 MHz.
6289BS–ATARM–07-Oct-08
31
Figure 9-2.Clock Generator Block Diagram
Power
Management
Controller
XIN
XOUT
Main Clock
MAINCK
ControlStatus
PLL and
Divider
PLLRCA
PLL Clock
PLLCK
12M Main
Oscillator
UPLL
(PLLB)
On Chip
RC OSC
Slow Clock
SLCK
XIN32
XOUT32
Slow Clock
Oscillator
Clock Generator
RCEN
HSCK
OSCSEL
OSC32EN
OSC32BYP
9.6Slow Clock Selection
9.6.1Description
The AT91SAM9R64/RL64 slow clock can be generated either by an external 32768Hz crystal or
the on-chip RC oscillator. The 32768Hz crystal oscillator can be bypassed to accept an external
slow clock on XIN32.
Configuration is located in the slow clock control register (SCKCR) located at address
0xFFFFFD50 in the backed up part of the system controller and so is preserved while VDDBU is
present.
Refer to the “Clock Generator” section for more details.
9.7Power Management Controller
The Power Management Controller provides all the clock signals to the system. It provides:
• the Processor Clock PCK
• the Master Clock MCK, in particular to the Matrix and the memory interfaces
• the USB Device HS Clock HSCK
• independent peripheral clocks, typically at the frequency of MCK
• two programmable clock outputs: PCK0 and PCK1
This allows the software control of five flexible operating modes:
• Normal Mode, processor and peripherals running at a programmable frequency
• Idle Mode, processor stopped waiting for an interrupt
• Slow Clock Mode, processor and peripherals running at low frequency
32
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
MCK
periph_clk[..]
int
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
PCK
Processor
Clock
Controller
Idle Mode
Master Clock Controller
Peripherals
Clock Controller
ON/OFF
SLCK
MAINCK
PLLCK
Prescaler
/1,/2,/4,...,/64
Programmable Clock Controller
pck[..]
ON/OFF
• Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor
stopped waiting for an interrupt
• Backup Mode, Main Power Supplies off, VDDBU powered by a battery
Figure 9-3.AT91SAM9R64/RL64 Power Management Controller Block Diagram
9.8Periodic Interval Timer
• Includes a 20-bit Periodic Counter, with less than 1 µs accuracy
• Windowed, prevents the processor to be in a dead-lock on the watchdog access
9.10Real-Time Timer
• Real-Time Timer, allowing backup of time with different accuracies
– 32-bit Free-running back-up Counter
– Integrates a 16-bit programmable prescaler running on slow clock
– Alarm Register capable to generate a wake-up of the system through the Shut Down
Controller
9.11Real-Time Clock
• Low power consumption
• Full asynchronous design
®
/WindowsCE® compliant tick generator
6289BS–ATARM–07-Oct-08
33
• Two hundred year calendar
• Programmable Periodic Interrupt
• Alarm and update parallel load
• Control of alarm and update Time/Calendar Data In
9.12General-Purpose Backed-up Registers
• Four 32-bit backup general-purpose registers
9.13Advanced Interrupt Controller
• Controls the interrupt lines (nIRQ and nFIQ) of the ARM Processor
• Thirty-two individually maskable and vectored interrupt sources
– Source 0 is reserved for the Fast Interrupt Input (FIQ)
– Source 1 is reserved for system peripherals (PIT, RTT, PMC, DBGU, etc.)
– Programmable Edge-triggered or Level-sensitive Internal Sources
– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive
• One External Sources plus the Fast Interrupt signal
• 8-level Priority Controller
– Drives the Normal Interrupt of the processor
– Handles priority of the interrupt sources 1 to 31
– Higher priority interrupts can be served during service of lower priority interrupt
• Vectoring
– Optimizes Interrupt Service Routine Branch and Execution
– One 32-bit Vector Register per interrupt source
– Interrupt Vector Register reads the corresponding current Interrupt Vector
•Protect Mode
– Easy debugging by preventing automatic operations when protect modeIs are
enabled
•Fast Forcing
– Permits redirecting any normal interrupt source on the Fast Interrupt of the
processor
9.14Debug Unit
34
AT91SAM9R64/RL64 Preliminary
• Composed of two functions
–Two-pin UART
– Debug Communication Channel (DCC) support
•Two-pin UART
– Implemented features are 100% compatible with the standard Atmel USART
– Independent receiver and transmitter with a common programmable Baud Rate
Generator
– Even, Odd, Mark or Space Parity Generation
– Parity, Framing and Overrun Error Detection
– Automatic Echo, Local Loopback and Remote Loopback Channel Modes
6289BS–ATARM–07-Oct-08
• Debug Communication Channel Support
9.15Chip Identification
• Chip ID: 0x019B03A0
• JTAG ID: 0x05B2003F
• ARM926 TAP ID: 0x0792603F
9.16PIO Controllers
• 4 PIO Controllers, PIOA, PIOB, PIOC and PIOD, controlling a maximum of 118 I/O Lines
• Each PIO Controller controls up to 32 programmable I/O Lines
• Fully programmable through Set/Clear Registers
• Multiplexing of two peripheral functions per I/O Line
• For each I/O Line (whether assigned to a peripheral or used as general purpose I/O)
• Synchronous output, provides Set and Clear of several I/O lines in a single write
AT91SAM9R64/RL64 Preliminary
– Support for two PDC channels with connection to receiver and transmitter
– Offers visibility of and interrupt trigger from COMMRX and COMMTX signals from
the ARM Processor’s ICE Interface
– PIOA has 32 I/O Lines
– PIOB has 32 I/O Lines
– PIOC has 32 I/O Lines
– PIOD has 22 I/O Lines
– Input change interrupt
– Glitch filter
– Multi-drive option enables driving in open drain
– Programmable pull up on each I/O line
– Pin data status register, supplies visibility of the level on the pin at any time
10. Peripherals
10.1Peripheral Mapping
As shown in Figure 8-1, the Peripherals are mapped in the upper 256M bytes of the address
space between the addresses 0xFFFA 0000 and 0xFFFC FFFF.
Each User Peripheral is allocated 16K bytes of address space.
6289BS–ATARM–07-Oct-08
35
10.2Peripheral Identifiers
The Table 10-1 defines the Peripheral Identifiers of the AT91SAM9R64/RL64. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller
and for the control of the peripheral clock with the Power Management Controller.
Note:Setting AIC, SYSIRQ, LCDC and IRQ bits in the clock set/clear registers of the PMC has no effect.
36
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
10.3Peripheral Interrupts and Clock Control
10.3.1System Interrupt
The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:
• the SDRAM Controller
• the Debug Unit
• the Periodic Interval Timer
• the Real-time Timer
• the Real-time Clock
• the Watchdog Timer
• the Reset Controller
• the Power Management Controller
The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used
within the Advanced Interrupt Controller.
10.3.2External Interrupts
All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signal IRQ, use a
dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs.
AT91SAM9R64/RL64 Preliminary
10.4Peripherals Signals Multiplexing on I/O Lines
The AT91SAM9R64/RL64 features 4 PIO controllers, PIOA, PIOB, PIOC and PIOD, which multiplexes the I/O lines of the peripheral set.
Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral
functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of
the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and
“Comments” have been inserted in this table for the user’s own comments; they may be used to
track how pins are defined in an application.
Note that some peripheral functions which are output only, might be duplicated within the both
tables.
The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral
mode. If I/O is mentioned, the PIO Line resets in input with the pull-up enabled, so that the
device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low.
If a signal name is mentioned in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case for pins controlling
memories, in particular the address lines, which require the pin to be driven as soon as the reset
is released. Note that the pull-up resistor is also enabled in this case.
The AT91SAM9RL64 and AT91SAM9R64 do not have the same peripheral signal multiplexing,
each one follows.
6289BS–ATARM–07-Oct-08
37
10.4.1AT91SAM9RL64 PIO Multiplexing
10.4.1.1AT91SAM9RL64 PIO Controller A Multiplexing
Table 10-2.AT91SAM9RL64 Multiplexing on PIO Controller A
PIO Controller AApplication Usage
Reset
I/O LinePeripheral APeripheral B
PA0MC_DA0I/OVDDIOP
PA1MC_CDAI/OVDDIOP
PA2MC_CKI/OVDDIOP
PA3MC_DA1TCLK0I/OVDDIOP
PA4MC_DA2TIOA0I/OVDDIOP
PA5MC_DA3TIOB0I/OVDDIOP
PA6TXD0I/OVDDIOP
PA7RXD0I/OVDDIOP
PA8SCK0RF1I/OVDDIOP
PA9RTS0RK1I/OVDDIOP
PA10CTS0RK0I/OVDDIOP
PA11TXD1I/OVDDIOP
PA12RXD1I/OVDDIOP
PA13TXD2TD1I/OVDDIOP
PA14RXD2RD1I/OVDDIOP
PA15TD0I/OVDDIOP
PA16RD0I/OVDDIOP
PA17AD0I/OVDDANA
State
Power
SupplyFunctionComments
PA18AD1RTS1I/OVDDANA
PA19AD2CTS1I/OVDDANA
PA20AD3SCK3I/OVDDANA
PA21DRXDI/OVDDIOP
PA22DTXDRF0I/OVDDIOP
PA23TWD0I/OVDDIOP
PA24TWCK0I/OVDDIOP
PA25MISOI/OVDDIOP
PA26MOSII/OVDDIOP
PA27SPCKI/OVDDIOP
PA28NPCS0I/OVDDIOP
PA29RTS2TF1I/OVDDIOP
PA30CTS2TK1I/OVDDIOP
PA31NWAITIRQI/OVDDIOP
38
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
10.4.1.2AT91SAM9RL64 PIO Controller B Multiplexing
Table 10-3.AT91SAM9RL64 Multiplexing on PIO Controller B
PIO Controller BApplication Usage
Reset
I/O LinePeripheral APeripheral B
PB0TXD3I/OVDDIOP
PB1RXD3I/OVDDIOP
PB2A21/NANDALEA21VDDIOM
PB3A22/NANDCLEA22VDDIOM
PB4NANDOEI/OVDDIOM
PB5NANDWEI/OVDDIOM
PB6NCS3/NANDCSI/OVDDIOM
PB7NCS4/CFCS0NPCS1I/OVDDIOM
PB8CFCE1PWM0I/OVDDIOM
PB9CFCE2PWM1I/OVDDIOM
PB10A25/CFRNWFIQA25VDDIOM
PB11A18A18VDDIOM
PB12A19A19VDDIOM
PB13A20A20VDDIOM
PB14A23PCK0A23VDDIOM
PB15A24ADTRGA24VDDIOM
PB16D16I/OVDDIOM
PB17D17I/OVDDIOM
State
Power
SupplyFunctionComments
PB18D18I/OVDDIOM
PB19D19I/OVDDIOM
PB20D20I/OVDDIOM
PB21D21I/OVDDIOM
PB22D22I/OVDDIOM
PB23D23I/OVDDIOM
PB24D24I/OVDDIOM
PB25D25I/OVDDIOM
PB26D26I/OVDDIOM
PB27D27I/OVDDIOM
PB28D28I/OVDDIOM
PB29D29I/OVDDIOM
PB30D30I/OVDDIOM
PB31D31I/OVDDIOM
6289BS–ATARM–07-Oct-08
39
10.4.1.3AT91SAM9RL64 PIO Controller C Multiplexing
Table 10-4.AT91SAM9RL64 Multiplexing on PIO Controller C
PIO Controller CApplication Usage
Reset
I/O LinePeripheral APeripheral B
PC0TF0I/OVDDIOP
PC1TK0LCDPWRI/OVDDIOP
PC2LCDMODPWM0I/OVDDIOP
PC3LCDCCPWM1I/OVDDIOP
PC4LCDVSYNCI/OVDDIOP
PC5LCDHSYNCI/OVDDIOP
PC6LCDDOTCKI/OVDDIOP
PC7LCDDENI/OVDDIOP
PC8LCDD0LCDD2I/OVDDIOP
PC9LCDD1LCDD3I/OVDDIOP
PC10LCDD2LCDD4I/OVDDIOP
PC11LCDD3LCDD5I/OVDDIOP
PC12LCDD4LCDD6I/OVDDIOP
PC13LCDD5LCDD7I/OVDDIOP
PC14LCDD6LCDD10I/OVDDIOP
PC15LCDD7LCDD11I/OVDDIOP
PC16LCDD8LCDD12I/OVDDIOP
PC17LCDD9LCDD13I/OVDDIOP
State
Power
SupplyFunctionComments
PC18LCDD10LCDD14I/OVDDIOP
PC19LCDD11LCDD15I/OVDDIOP
PC20LCDD12LCDD18I/OVDDIOP
PC21LCDD13LCDD19I/OVDDIOP
PC22LCDD14LCDD20I/OVDDIOP
PC23LCDD15LCDD21I/OVDDIOP
PC24LCDD16LCDD22I/OVDDIOP
PC25LCDD17LCDD23I/OVDDIOP
PC26LCDD18I/OVDDIOP
PC27LCDD19I/OVDDIOP
PC28LCDD20I/OVDDIOP
PC29LCDD21TIOA1I/OVDDIOP
PC30LCDD22TIOB1I/OVDDIOP
PC31LCDD23TCLK1I/OVDDIOP
40
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
10.4.1.4AT91SAM9RL64 PIO Controller D Multiplexing
Table 10-5.AT91SAM9RL64 Multiplexing on PIO Controller D
PIO Controller DApplication Usage
Reset
I/O LinePeripheral APeripheral BComments
PD0NCS2I/OVDDIOP
PD1AC97_FSI/OVDDIOP
PD2AC97_CKSCK1I/OVDDIOP
PD3AC97_TXCTS3I/OVDDIOP
PD4AC97_RXRTS3I/OVDDIOP
PD5DTXDPWM2I/OVDDIOP
PD6AD4I/OVDDANA
PD7AD5I/OVDDANA
PD8NPCS2PWM3I/OVDDIOP
PD9SCK2NPCS3I/OVDDIOP
PD10TWD1TIOA2I/OVDDIOP
PD11TWCK1TIOB2I/OVDDIOP
PD12PWM2PCK1I/OVDDIOP
PD13NCS5/CFCS1NPCS3I/OVDDIOP
PD14DSR0PWM0I/OVDDIOP
PD15DTR0PWM1I/OVDDIOP
PD16DCD0PWM2I/OVDDIOP
PD17RI0I/OVDDIOP
State
Power
SupplyFunctionComments
PD18PWM3I/OVDDIOP
PD19PCK0I/OVDDIOP
PD20PCK1I/OVDDIOP
PD21TCLK2I/OVDDIOP
6289BS–ATARM–07-Oct-08
41
10.4.2AT91SAM9R64 PIO Multiplexing
Note:In Table 10-6, Table 10-7, Table 10-8 and Table 10-9, shaded cells indicate I/O lines that are NOT available on the
AT91SAM9R64.
10.4.2.1AT91SAM9R64 PIO Controller A Multiplexing
Table 10-6.AT91SAM9R64 Multiplexing on PIO Controller A
PIO Controller AApplication Usage
Reset
I/O LinePeripheral APeripheral B
PA0MC_DA0I/OVDDIOP
PA1MC_CDAI/OVDDIOP
PA2MC_CKI/OVDDIOP
PA3MC_DA1TCLK0I/OVDDIOP
PA4MC_DA2TIOA0I/OVDDIOP
PA5MC_DA3TIOB0I/OVDDIOP
PA6TXD0I/OVDDIOP
PA7RXD0I/OVDDIOP
PA 8NANAReserved
PA 9NANAReserved
PA10CTS0RK0I/OVDDIOP
PA11TXD1I/OVDDIOP
PA12RXD1I/OVDDIOP
PA13TXD2I/OVDDIOP
PA14RXD2I/OVDDIOP
PA15TD0I/OVDDIOP
PA16RD0I/OVDDIOP
PA17AD0I/OVDDIOP
PA18AD1RTS1I/OVDDIOP
PA19AD2CTS1I/OVDDIOP
PA 20NANAReserved
PA21DRXDI/OVDDIOP
PA22DTXDRF0I/OVDDIOP
PA23TWD0I/OVDDIOP
PA24TWCK0I/OVDDIOP
PA25MISOI/OVDDIOP
PA26MOSII/OVDDIOP
PA27SPCKI/OVDDIOP
PA28NPCS0I/OVDDIOP
PA 29NANAReserved
PA 30NANAReserved
PA31NWAITIRQI/OVDDIOP
State
Power
SupplyFunctionComments
42
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
AT91SAM9R64/RL64 Preliminary
10.4.2.2AT91SAM9R64 PIO Controller B Multiplexing
Table 10-7.AT91SAM9R64 Multiplexing on PIO Controller B
PIO Controller BApplication Usage
Reset
I/O LinePeripheral APeripheral B
PB0TXD3I/OVDDIOP
PB1RXD3I/OVDDIOP
PB2A21/NANDALEA21VDDIOM
PB3A22/NANDCLEA22VDDIOM
PB4NANDOEI/OVDDIOM
PB5NANDWEI/OVDDIOM
PB6NCS3/NANDCSI/OVDDIOM
PB7NCS4/CFCS0NPCS1I/OVDDIOM
PB8CFCE1PWM0I/OVDDIOM
PB9CFCE2PWM1I/OVDDIOM
PB10A25/CFRNWFIQA25VDDIOM
PB11A18A18VDDIOM
PB12A19A19VDDIOM
PB13A20A20VDDIOM
PB14A23PCK0A23VDDIOM
PB15A24ADTRGA24VDDIOM
PB16-
PB31
NANAReserved
State
Power
SupplyFunctionComments
6289BS–ATARM–07-Oct-08
43
10.4.2.3AT91SAM9R64 PIO Controller C Multiplexing
Table 10-8.AT91SAM9R64 Multiplexing on PIO Controller C
PIO Controller CApplication Usage
Reset
I/O LinePeripheral APeripheral B
PC0TF0I/OVDDIOP
PC1TK0I/OVDDIOP
PC2-
PC31
NANAReserved
State
Power
SupplyFunctionComments
10.4.2.4AT91SAM9R64 PIO Controller D Multiplexing
Table 10-9.AT91SAM9R64 Multiplexing on PIO Controller D
PIO Controller DApplication Usage
Reset
I/O LinePeripheral APeripheral BComments
PD0-
PD17
PD18PWM3I/OVDDIOP
PD19PCK0I/OVDDIOP
PD20PCK1I/OVDDIOP
PD21TCLK2I/OVDDIOP
NANAReserved
State
Power
SupplyFunctionComments
44
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
11. Embedded Peripherals Overview
11.1Serial Peripheral Interface (SPI)
• Supports communication with serial external devices
– Four chip selects with external decoder support allow communication with up to 15
peripherals
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
Sensors
– External co-processors
• Master or slave serial peripheral bus interface
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
and data per chip select
– Programmable delay between consecutive transfers
– Selectable mode fault detection
• Very fast transfers supported
– Transfers with baud rates up to MCK
– The chip select line may be left active to speed up transfers on the same device
AT91SAM9R64/RL64 Preliminary
11.2Two-wire Interface (TWI)
• Compatibility with standard two-wire serial memory
• One, two or three bytes for slave address
• Sequential read/write operations
• Supports either master or slave modes
• Compatible with Standard Two-wire Serial Memories
• Master, Multi-master and Slave Mode Operation
• Bit Rate: Up to 400 Kbits
• General Call Supported in Slave mode
• Connection to Peripheral DMA Controller (PDC) Channel Capabilities Optimizes Data
Transfers in Master Mode Only
– One Channel for the Receiver, One Channel for the Transmitter
– Next Buffer Support
11.3USART
• Programmable Baud Rate Generator
• 5- to 9-bit full-duplex synchronous or asynchronous serial communications
– 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode
• -3/+3 LSB Integral Non Linearity, -2/+2 LSB Differential Non Linearity
• Integrated 6-to-1 multiplexer, offering eight independent 3.3V analog inputs
• External voltage reference for better accuracy on low voltage inputs
• Individual enable and disable of each channel
• Multiple trigger sources
– Hardware or software trigger
– External trigger pin
– Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger
• Sleep Mode and conversion sequencer
– Automatic wakeup on trigger and back to sleep mode after conversions of all
enabled channels
48
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
12. Package Drawings
Figure 12-1. 144-ball LFBGA Package Drawing
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
49
Figure 12-2. 217-ball LFBGA Package Drawing
50
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
13. Ordering Information
Table 13-1.AT91SAM9R64/RL64 Ordering Information
Ordering CodePackagePackage TypeTemperature Operating Range
AT91SAM9R64-CULFBGA144Green
AT91SAM9RL64-CULFBGA217Green
AT91SAM9R64/RL64 Preliminary
Industrial
-40°C to 85°C
6289BS–ATARM–07-Oct-08
51
Revision History
Doc. RevComments
“Features”“Debug Unit (DBGU)” on page 2, updated
Figure 8-1 “AT91SAM9R64/RL64 Memory Mapping”, Internal Memory Mapping updated.
Table 7-2, “List of Bus Matrix Slaves”, Table 7-3, “AT91SAM9R64/RL64 Master to Slave Access”, Slave
3 updated.
6289BS
6289ASFirst issue
Section 5.1 “Power Supplies”, updated with caution on VDDCORE and VDDIO constraints
Section 5.1.1 “USB Power Supply Considerations” and Figure 5-1 added to datasheet.
Section 5.2 “Power Consumption”, first two sentences updated.
Table 3-1, “Signal Description List”, additional comments on BMS.
SHDN comments updated.
Table 10-3 and Table 10-7 PB8, PB9 Peripheral A column: typos corrected, “CFCE1”, “CFCE2”.
Change
Request
Ref.
5846
5276
5291
5420
5388
5423
rfo
5788
52
AT91SAM9R64/RL64 Preliminary
6289BS–ATARM–07-Oct-08
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