Atmel AT91SAM9M10-G45-EK User guide

AT91SAM9M10-G45-EK

....................................................................................................................

User Guide

6495B–ATARM–21-Apr-10

Section 1

Introduction.................................................................................................................1-1

1.1 Scope ................................................................................................................................. 1-1

1.2 Applicable Documents ....................................................................................................... 1-2

Section 2

Kit Contents ................................................................................................................2-1

2.1 Deliverables ....................................................................................................................... 2-1

2.2 Evaluation Board Specifications......................................................................................... 2-2

2.3 Electrostatic Warning ......................................................................................................... 2-2

Section 3

Power up.....................................................................................................................3-1

3.1 Power Up the Board...........................................................................................................3-1

3.2 Battery................................................................................................................................ 3-1

3.3 DevStart ............................................................................................................................. 3-1

3.4 Recovery Procedure .......................................................................................................... 3-2

3.5 Sample Code and Technical Support ................................................................................ 3-2

Section 4

Board Description .......................................................................................................4-1

4.1 Equipment on the Board .................................................................................................... 4-1

4.1.1 Interfaces ............................................................................................................. 4-1

4.1.2 Board Interface Connection ................................................................................. 4-2

4.1.3 Push Button Switches .......................................................................................... 4-2

4.1.4 Display LCD and LEDs ........................................................................................ 4-3

4.2 Hardware Layout and Configuration .................................................................................. 4-3

4.2.1 Processor............................................................................................................. 4-3

4.2.2 Clock Circuitry...................................................................................................... 4-4

4.2.3 Reset Circuitry ..................................................................................................... 4-4

4.2.4 Memory................................................................................................................ 4-4

4.2.5 Power Supplies .................................................................................................... 4-7

4.2.6 Debug Interface ................................................................................................. 4-10

4.2.7 Audio Stereo Interface ....................................................................................... 4-15

4.2.8 TV-Out Extension .............................................................................................. 4-17

4.2.9 Software Controlled LEDs ................................................................................. 4-18

4.2.10 Serial Peripheral Interface Controller (SPI) ....................................................... 4-19

4.2.11 Two Wire Interface (TWI)................................................................................... 4-19

4.2.12 SD/MMC Interface ............................................................................................. 4-19

4.2.13 TFT LCD with Touch Panel ............................................................................... 4-20

4.2.14 Push Buttons ..................................................................................................... 4-22

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4.2.15 Expansion Slot ................................................................................................... 4-22

Section 5

Configuration ..............................................................................................................5-1

5.1 JTAG/ICE Configuration..................................................................................................... 5-1

5.2 ETHERNET Configuration ................................................................................................. 5-1

5.3 Jumpers Configuration ....................................................................................................... 5-2

5.4 Miscellaneous Configuration Items .................................................................................... 5-3

5.5 PIO Configuration............................................................................................................... 5-3

5.5.1 Peripheral Signals Multiplexing on I/O Lines ....................................................... 5-3

5.5.2 Multiplexing on PIO Controller A (PIOA).............................................................. 5-3

5.5.3 Multiplexing on PIO Controller B (PIOB).............................................................. 5-5

5.5.4 Multiplexing on PIO Controller C (PIOC) ............................................................. 5-6

5.5.5 Multiplexing on PIO Controller D (PIOD) ............................................................. 5-7

5.5.6 Multiplexing on PIO Controller E (PIOE).............................................................. 5-8

Section 6

Connectors .................................................................................................................6-1

6.1 Power Supply ..................................................................................................................... 6-1

6.2 RS232 Connector with RTS/CTS Handshake Support ...................................................... 6-1

6.3 DBGU................................................................................................................................. 6-2

6.4 Ethernet.............................................................................................................................. 6-3

6.5 USB Host ........................................................................................................................... 6-3

6.6 USB Host/Device ............................................................................................................... 6-4

6.7 JTAG Debugging Connector .............................................................................................. 6-4

6.8 SD/MMC- MCI0.................................................................................................................. 6-6

6.9 SD/MMC- MCI1.................................................................................................................. 6-7

6.10 AC97 .................................................................................................................................. 6-8

6.11 Image Sensor - ISI ............................................................................................................. 6-9

6.12 Video ................................................................................................................................ 6-10

6.13 Display Devices................................................................................................................ 6-10

6.13.1 TFT LCD ............................................................................................................ 6-10

6.14 LCD Extension ................................................................................................................. 6-11

Section 7

Schematics .................................................................................................................7-1

7.1 Schematics......................................................................................................................... 7-1

Section 8

Revision History..........................................................................................................8-1

8.1 Revision History ................................................................................................................. 8-1

1-ii AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

1.1 Scope

Section 1

Introduction

This User Guide introduces the AT91SAM9M10(G45) Evaluation Kit and describes its development and debugging capabilities.

Figure 1-1. Board Photo

The Atmel® SAM9M10-G45-EK is a fully-featured evaluation platform for the Atmel AT91SAM9M10 or AT91SAM9G45 microcontroller. The kit is equipped with an AT91SAM9M10 chip, which is a superset of the AT91SAM9G45, and therefore allows evaluating that reference as well. The evaluation kit allows users to extensively evaluate, prototype and create application-specific designs.

The SAM9M10-G45-EK includes many hardware peripherals such as:

 Two high speed USB hosts and one high speed device port

 An Ethernet 10/100 interface

 Two high speed multimedia card interfaces

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6495B–ATARM–21-Apr-10

Introduction

 An LCD TFT display (480*272 RGB) with resistive touch panel

 A composite video output

 A camera interface

 Several communication peripherals such as:

– Universal Synchronous/Asynchronous Receiver Transmitter (USART)

– Two-Wire Interface (TWI)

The external memory block is made of 3 memory types:

 DDR2-SDRAM

 NAND Flash

 NOR Flash (not populated by default)

1.2 Applicable Documents

Table 1-1. Applicable Documents

Reference Title Comments

Atmel Literature n° 6438 SAM9G45 Preliminary

Atmel Literature n° 6355 SAM9M10 Preliminary

This document describes the SAM9G45, which is part of the Atmel's Smart ARM

®

Microcontrollers.

It is available from

http://www.atmel.com/dyn/resources/prod_documents/doc6438.pdf

This document describes the SAM9M10, which is part of the Atmel's Smart ARM® Microcontrollers

http://www.atmel.com/dyn/resources/prod_documents/doc6355.pdf

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2.1 Deliverables

The Atmel SAM9M10-G45-EK toolkit includes:

 Board

– The SAM9M10-G45-EK board

 Power supply

– Universal input AC/DC power supply with US, Europe and UK plug adapters

– One 3V Lithium Battery type CR1225

 Cables

– One micro A/B-type USB cable

– One serial RS232 cable

– One RJ45 crossed cable

 A Welcome Letter

Figure 2-1. Unpacked SAM9M10-G45-EK

Section 2

Kit Contents

Unpack and inspect this kit carefully. Contact your local Atmel distributor, should you have issues concerning the contents of the kit.

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Kit Contents

2.2 Evaluation Board Specifications

Table 2-1. SAM9M10-G45-EK Specifications

Characteristics Specifications

Clock speed 400 MHz PCK, 133 MHz MCK

Ports Ethernet, USB, RS232, DBGU, JTAG

Board supply voltage 5 VDC from connector

Temperature

- operating

- storage

Relative humidity 0 to 90% (non condensing)

Dimensions 180 mm x 140 mm

RoHS status Compliant

-10° to +50° C

-40° to +85° C

2.3 Electrostatic Warning

The SAM9M10-G45-EK evaluation board is shipped in a protective anti-static package. The board must not be subjected to high electrostatic potentials. We strongly recommend using a grounding strap or sim ilar ESD protective device when handling the board in hostile ESD environments (offices with synthetic carpet, for example...). Avoid touching the component pins or any other metallic element on the board.

-

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3.1 Power Up the Board

Unpack the board taking care to avoid electrostatic discharge. Unpack the power supply, select the right power plug adapter corresponding to that of your country, and insert it in the power supply.

Connect the power supply DC connector to the board and plug the power supply to an AC power plug.

The board LCD should light up and display a welcome page. Then, click or touch icons displayed on the screen and enjoy the demo.

3.2 Battery

The SAM9M10-G45-EK ships with a 3V coin battery.

This battery is not required for the board to start up.

The coin battery is provided for user convenience in case the user would like to exercise the date and time backup function of the SAM9M10 series devices when the board is switched off.

Section 3

Power up

3.3 DevStart

The on-board NAND Flash contains a “SAM9M10-G45-EK DevStart”.

It is stored in the “SAM9M10-G45-EK DevStart” folder on the USB Flash disk available when the SAM9M10-G45-EK is connected to a host computer.

Click the file “welcome.html” in this folder to launch SAM9M10-G45-EK DevStart.

SAM9M10-G45-EK DevStart guides you through installation processes of IAR™ EWARM, Keil MDK and GNU toolkits. Then, it gives you step-by-step instructions on how to rebuild a single example project and

how to program it into the SAM9M10-G45-EK. Optionally, if you have a SAM-ICE™, instructions are also given about how to debug the code.

We recommend that you backup the “SAM9M10-G45-EK DevStart” folder on your computer before launching it.

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Power up

3.4 Recovery Procedure

The DevStart ends by giving step-by-step instructions on how to recover the SAM9M10-G45-EK to the state as it was when shipped by Atmel.

Follow the instructions if you deleted the contents of the NAND Flash and want to recover from this situation.

3.5 Sample Code and Technical Support

After boot up, you can run some sample code or your own application on the development kit. You can download sample code and get Technical support from

http://www.atmel.com/dyn/products/tech_support.asp?Faq=y&family_id=689%20.

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4.1 Equipment on the Board

PARALLEL

FLASH

AT91SAM9M10

DEBUG

JTAG/ICEDBGU

System Controller

External Memory

EBI0

EBI1 / 1.8v

DDR2

SDRAM

DDR2

SDRAM

NAND

FLASH

Multimédia Cards Interface

Multimedia Cards Interface

MCI0

SPI0

MCI1

Data

Flash

USART

USB

Host A

Host B

Device

ETHERNET

10/100 MAC

ETHERNET

10/100 MAC

LCD Interface

AC97

PIO

TWI

oooooooo oooooooo

Serial

Eeprom

oooooooo oooooooo

4 bits interface SD/MMC

8 bits interface SD/MMC

Micro

Line In

Line Out

oooooooo oooooooo

LCD TFT 480*272

LCD TFT

480*272

PWM

PHY RMII

RS232

Codec

NPCS0

NCS0

NCS3

NCS1

Led

CD

User I/OAudioVidéoLCD TFTMultimedia cardsMain Memory

Touch

Screen

Touch

Screen

Composite

video

VCC 5V PIOJTAG/ICEDBGUUSB

Hub / Device

USB Hub

High / Full

RS232Ethernet RMII/MIIISI

Image Sensor

Interface

Image Sensor

Interface

Power /

Shdn

Joystick

& P.B

Figure 4-1. Board Architecture

Section 4

Board Description

4.1.1 Interfaces

The board is equipped with an AT91SAM9M10-CU embedded microprocessor (324-ball TFBGA package) together with the following interfaces or peripherals:

 DDR2/LPDDR memory interface is connected to 128 MB DDR2-SDRAM memory

 External Bus Interface (EBI) is connected to three kinds of memory devices (DDR2-SDRAM, NAND

Flash and NOR Flash (not populated))

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Board Description

 One TWI serial memory

 One USB Host/Device multiplexed port interface

 One USB Host port interface

 One RS232 serial communication port

 One DBGU serial communication port

 One JTAG/ICE debug interface

 One Ethernet 100-base TX with three status LEDs

 One AC97 Audio CODEC with headphone line out, line in and mono/stereo microphone inputs

 One TV interface (composite video output)

 One 4.3" TFT LCD Module with touch screen and back light

 One ISI connector (camera interface)

 One power red LED and two general-purpose green LEDs

 Two user input push buttons

 One joystick with 4-direction control and selector

 One wakeup input push button

 One reset input push button

 One SD/SDIO/MMC plus card slot (4/8 bit interface)

 One SD/SDIO/MMC card slot (4-bit interface)

 One Lithium Coin Cell Battery Retainer for 12 mm cell size (memory backup usage)

4.1.2 Board Interface Connection

 Ethernet using RJ45 connector (J15)

 USB Host, support USB host using a type A connector (J12)

 USB Host/Device, support USB host/device using a type micro AB connector (J14)

 UART1 (RX, TX, RTS, CTS) connected to a 9-way male D-type RS232 connector (J11)

 DBGU (RX and TX only) connected to a 9-way male D-type RS232 connector (J10)

 JTAG, 20 pin IDC connector (J13)

 SD/MMCplus connector (J5)

 SD/MMC connector (J6)

 Headphone (J7), line-in (J8) and microphone headset (J9)

 Speaker output (JP15)

 Image sensor connector (J17)

 TFT LCD display, with TouchScreen and backligth (J24)

 Test points; various test points are located throughout the board

 Main power supply (J2)

4.1.3 Push Button Switches

 Reset, board reset (BP1)

 Wake up, push button to bring processor out of low power mode (BP2)

 Right and left click, user push button switches (BP4 and BP5)

 Joystick (BP3)

4-2 AT91SAM9M10-G45-EK User Guide

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4.1.4 Display LCD and LEDs

DBGU RS232 JTAG ETHERNET

WAKE-UP

BUTTON

RESET

BUTTON

BACKUP

BATTERY

«RIGHT»

USER BUTTON

«LEFT»

USER BUTTON

SD/MMC 1

SLOT

SD/MMC 0

SLOT

USER

JOYSTICK

VIDEO

OUTPUT

HEADPHONES

HEADER

MICROPHONE

INPUT

LINE

INPUT

LCD DISPLAY AREA

LCD EXTENSION

CONNECORS

ISI/CAMERA

CONNECTOR

POWER

HOST

USB

HOST

DEVICE

USB

Y6

TP2

J20

J7

R85

L11

JP15

J9

J8

TP4

J6

R185

Y7

BP3

C205

R181

R183

L22

L20

MN20

TP6

C203

C206

MN12

JP13

C201

C141

C143

JP14

JP17

JP18

MN14

C139

C146

C147

J10

L17 C198

C128

R71

R69

C126

C199

C133

C129

MN9

R72

R74

R73

R70

C127

C137

C155

C156

R75

R84 R83

R78

L10

Y3

C148

C149

R79

R80

L12

L9

L8

MN15

JP10

J11

J18

MN8

MN11

MN16

MN10

JP9

RR19

RR17

RR13

RR11

JP6

JP5

C168

J12

R203

R204

C59

RR25

RR23

RR21

TP5

C48

R40

R42

R44

M

N

5

RR9

C170

MN17

J14

Y2

C64

C41

C47

C38

C66

R37

R46

MN6

Q2

D3

J17

R20R5

L4

C186

R99

R106

R39R12

R100

R101

R120

L3

L2

JP8

C177

C179

R117

R116

R48

Y1

J13

J23

RR45

JP11

J1

C183

Y5

Y4

JP3JP2JP1

MN7

J15

R191

R192

R193

R194

R195

R196

RR36

C37 R29

R22

R21

D2D1

JP12

MN13

C185

R114

R109

R104

R115

R105

R112

C178

C176

C182

J5

C31 R27

BP5

L5

JP7

BP2

Q1

JP16

JP4

C23

R110

MN2

C187

C180

C181

C9

RR47

J2

D6

D4

D5

CR1

TP1

R197

R198

TP3

BP4

J3

BP1

C27

C6

MN1

MN4

C12

19

20

1

29

30

39

40

71

82

12

34

1

2

12

34

1

2

1

4

2

1

SD/MMC

VIDEO

HEAD PHONE

MIC IN

LINE IN

DBGU

SELECT

E2PROM

NANDCS NCS0

RS232

VDDIOM1

USB

LCD EXTENSION

VDDIOM0

HOST

USB

HOST /DEV

1

ISI

J1

VDDUTMII

VDDUTMIC

VDDCORE

VDDPLLUTMI

ICE

BMS

JP2/P2/JD3

VDDIOPn

ETHERNET

LEFT

BAT

VDDBU

3V3

NPCS0

SD/MMC+

CR1225

3V

WAKEUP

5VCC POWER

RIGHT

NRST

 Display, 480xRGBx272 pixels LCD module display connected to the PIO port E (LCD1)

 One surface-mounted power red LED, user interface (D3)

 Two surface-mounted green LEDs, user interface (D1 and D2)

 Three surface-mounted LEDs indicate Ethernet status (D4, D5, D6)

Figure 4-2. Board Layout Commented

Board Description

4.2 Hardware Layout and Configuration

4.2.1 Processor

The major components of the SAM9M10-G45-EK board are shown in Figure 4-1.

The board features the Atmel SAM9M10-CU 324-ball TFBGA package. This chip runs at a nominal frequency of 400 MHz for the core and 133 MHz for the system bus.

For more information, refer to the latest SAM9M10 datasheet available from http://www.atmel.com/

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6495B–ATARM–21-Apr-10

Board Description

4.2.2 Clock Circuitry

The SAM9M10-G45-EK includes six clock sources:

 Two are alternatives for the SAM9M10 main clock,

 One crystal and one crystal oscillator are used for the Ethernet MII/RMII chip,

 One crystal is used for the AC97 codec chip,

 One crystal or one crystal oscillator is used for the TV encoder.

Table 4-1. Main Components Associated with the Clock Systems

Quantity Description Component assignment

1 Crystal for Internal Clock, 12 MHz Y1

1 Crystal for RTC Clock, 32.768 kHz Y2

1 Oscillator for Ethernet Clock RMII, 50 MHz Y4

1 Crystal for Ethernet Clock MII, 25 MHz (not populated) Y5

1 Crystal for AC97 Codec Clock, 24.576 MHz Y3

1

4.2.3 Reset Circuitry

The reset sources are:

 Power on reset

 Push button reset

 JTAG reset from an in-circuit emulator interface.

4.2.4 Memory

4.2.4.1 External Memories

The SAM9M10 features a DDR2/LPDDR memory interface and an External Bus Interface (EBI) to permit interfacing to a wide range of external memories and to almost any kind of parallel peripheral.

The SAM9M10-G45-EK board is equipped with DDR2/LPDDR devices featuring 128 MB of DDR2SDRAM memory (16Meg*8*4).

The External Bus Interface (EBI) is connected to three kinds of memory devices:

 One Parallel Flash (not populated by default)

 Two DDR2-SDRAM

 One NAND Flash (2Gb, 8 bit bus)

Crystal for TV Encoder Clock, 13 MHz, or Oscillator for TV Encoder, 13 MHz (not populated)

Y7 Y6

The chip selects NCS0, NCS1 and NCS3 are used for NOR Flash, DDR2-SDRAM and NAND Flash memories, respectively. Furthermore, a dedicated jumper can disconnect each of the two NCS0 and NCS3 signals, making them available for other functions.

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Figure 4-3. EBI0 - DDR2

Board Description

C88

DDR_DQM1

DDR_DQS1

C68 100nC68 100n

C70 100nC70 100n

C74 100nC74 100n

C76 100nC76 100n

1V8

DDR_D12

DDR_D15

DDR_D10

DDR_D14

DDR_D11

DDR_D8

DDR_D9

DDR_D13

C8

C2

D3

D7

DQ1

DQ3

DQ0

DQ2

DDR2 SDRAM

A3

A1H3A2

A0

MN7

J2

H8

H7

DDR_A0

DDR_A2

DDR_A1

DDR_A3

D1

D9

DQ4

A4

J8

DDR_A4

DDR_A5

B1

DQ5

DQ6

A5J3A6J7A7K2A8

DDR_A6

B9

DQ7

K8

DDR_A7

DDR_A8

A8

B7

DQS

A9K3A10

H2

DDR_A9

DDR_A10

B3

DQS

A11

L2

K7

DDR_A11

DDR_A12

E1

E9

A2

L1

A1

H9

VDD

VDDL

RDQS/NU

RDQS/DM

BA0

BA1

A12

ODT

A13

L8

F9

G2

G3

DDR_A13

BA0

BA1

C88

100n

C84100nC84100n

C86100nC86100n

C80100nC80100n

C82100nC82100n

C78 100nC78 100n

DDR_VREF

E3

C3

A9

C1

C9

C7

VDDQ

CKE8CK

CKE

F8

F2

CK

NCK

CKE

A7

K9

A3

E2

J1

VSS

VREF

CS

CASG7RAS

F7

G8

CS

CAS

RAS

E7

B8

D8

B2

D2

VSS

VSSQ

VSSDL

RFU1G1RFU2

WE

RFU3

L3

L7

F3

NWE

DDR_VREF

R51

1.5k

R51

1.5k

R52

1.5k

R52

1.5k

C91

100n

C91

100n

C89

100n

R501RR50

1R

4.7u

C90

L5 10uHL5 10uH

1V8

DDR_DQM0

DDR_DQS0

C71 100nC71 100n C72 100nC72 100n

C69 100nC69 100n

C73 100nC73 100n

C67 100nC67 100n

C75 100nC75 100n

1V8

DDR_D3

DDR_D7

DDR_D2

DDR_D4

DDR_D5

DDR_D6

DDR_D0

DDR_D1

C8

D1

B3

E9

A8

B1

D3

B7

B9

D9

DQ4

DQ1C2DQ2D7DQ3

DQ5

DQ0

DQ7

DQ6

DQS

DDR2 SDRAM

A6

A2

A4J8A5

A7

A9K3A10H2BA0

A1

A3

A8

J3

DDR_A4

DDR_A5

J7

K2

DDR_A6

DDR_A7

K8

DDR_A8

DDR_A9

DDR_A10

A11

K7

DDR_A11

A0

MN6

J2

H8

H7

H3

DDR_A2

DDR_A0

DDR_A1

DDR_A3

A2

RDQS/NU

RDQS/DM

A12L2A13

L8

DDR_A12

DDR_A13

A1

VDD

G2

G3

BA0

BA1

DDR_BA0

DDR_BA1

E1

L1

VDDH9VDD

VDD

VDDL

ODT

BA1

F9

C79 100nC79 100n

C77 100nC77 100n

A9

C1

VDDQ

CKEF2CK

CKE

DDR_CKE

C85100nC85100n

C83 100nC83 100n

C81100nC81100n

C7

C9

C3

VDDQ

CKF8CASG7RAS

E8

CK

NCK

DDR_CLK

DDR_NCLK

VDDQ

C87

DDR_VREF

A3

E2

VREF

CS

G8

CS

CAS

DDR_CS

100n

E3

J1

VSS

F7WEF3

RAS

DDR_CAS

DDR_RAS

E7

B8

A7

K9

B2

D8

D2

VSS

VSSQ

VSSDL

RFU1

RFU2

RFU3

L3

L7

G1

NWE

DDR_WE

DDR_D[0..15]

DDR_A[0..13]

AT91SAM9M10-G45-EK User Guide 4-5

6495B–ATARM–21-Apr-10

Board Description

Figure 4-4. EBI1 - DDR2 + Flash

0 _D

LASH

EBI1_F

E2

10

10 N

N M

M

_A1

LASH

EBI1_F

1_FLASH_D1

EBI

2 H

1

00

O

/

I

A0E1A1D1A2

_A2

EBI1_FLASH

EBI1_FLASH_D2

E3

H

FLAS

1 C

_A3

LASH

EBI1_F

2 O

/

I

EBI1_FLASH_D3

H3

3

O

/

I

A3A1A4B1A5

_A4

LASH

EBI1_F

EBI1_FLASH_D4

EBI1_FLASH_D5

EBI1_FLASH_D6

E4

H4

H5

4 O

/

I

I/O5

DT

DT 2

2

AT49SV32

2 D

_A5

_A6

LASH

EBI1_F

EBI1_FLASH_A7

8

7

_D

LASH

LASH_D9

EBI1_FLASH_D10

EBI1_F

EBI1_FLASH

EBI1_F

2

E5

G

F2

I/O6

I/O8

I/O7

I/O9

A6C2A7A2A8B5A9A5A10C5A11

EBI1_FLASH_A10

EBI1_FLASH_A8

EBI1_FLASH_A9

EBI1_FLASH_A11

EBI1_FLASH_D13

EBI1_FLASH_D12

EBI1_FLASH_D14

EBI1_FLASH_D11

I/O10F3I/O11G3I/O12F4I/O13G5I/O14F5I/O15

A12

A13

B6

A6

C6

D5

EBI1_FLASH_A12

EBI1_FLASH_A14

EBI1_FLASH_A15

EBI1_FLASH_A13

A14

EBI1_FLASH_D15

G6

A15

D6

EBI1_FLASH_A16

A16

E6

EBI1_FLASH_A17

100nF

C100

1V8

G4

A3

RDY/ BUSY

A17B2A18

A19

D4

C3

D3

1_FLASH_A20

1_FLASH_A19

EBI1_FLASH_A21

EBI1_FLASH_A18

EBI

H1

C4

F6

H6

NC

NC1

VCC

GND

CBGA

WE

OE

VPP

A20

RESET

CE

F1

A4

B3

B4

G1

1V8

DNP

R40 470KR40 470K

JP9JP9

VREF1

..15] 0

FLASH_D[ _

EBI1

R39 100KR39 100K

EBI1_NRD/CFOE

1V8

EBI1_NWE/NWR0/CFWE

DQS1_EBI1

DQM1_EBI1

C83 100nFC83 100nF

C81 100nFC81 100nFC

C87 100nFC87 100nF

C95 100nFC95 100nF

C89 100nFC89 100nF

C99 100nFC99 100nF

C91 100nFC91 100nF

C93 100nFC93 100nF

C97 100nFC97 100nF

C102

100nF

VREF1

C1

C7

E3

B8

A7

A3

J1

C9

A9

C3

E1

L1

DT

F9

00nFC

00nF 1

1

6

8

C

E1

L1

D VD

ODT

F9

VDDL

88 100nFC88 100nF

C

VDDL

VDDQ

KE C

F2

EBI1

KE_ C

F

F n

n 0

0

0 10

0 10 9

9 C

C

A9

VDDQ

CKEF2CK

CKE_EBI1

EBI1

KE_ C

VDDQ

F

F n

n 0

0

2 10

2 10 9

9 C

C

C1

VDDQ

CK

F8

E8

EBI1 K_

CLK_EBI1

NCL

F

n

n 0

0

6 10

4 10

9

9 C

C

C7

C3

VDDQ

CKF8C

E8

NCLK_EBI1

CLK_EBI1

EBI1

EBI1 K_

L C

NCLK_

C9

VDDQ

nFC98 100nF 0

C98 10

VDDQ

E2

VREF

CS

G8

CS_EBI1

VREF1

E2

F

VRE

S

C

G8

(NCS1)

CS_EBI1

EBI1

CS_

G7

AS_EBI1 C

C101

A3

G7

CAS_EBI1

VSS

AS C

VSS

AS

1

EBI

CAS_

VSS

AS R

F7WEF3

AS_EBI1 R

100nF

E3

VSS

AS R

F7

RAS_EBI1

K9

B2

VSS

VSSQ

G1

WE_EBI1

B2

B8

K9

A7

J1

VSS

VSSQ

E W

1

F3

G

EBI1 E_ W

A8

H2

SDA10) (

2 A1 R_

D

EBI1_D

A8

H2

(SDA10)

2 A1 R_

D D _

EBI1

DQS

A10

K7

R_A13 D

EBI1_D

S

Q D

A10

K7

3

A1 R_

D D _

EBI1

B3

A2

RDQS/NU

RDQS/DM

A11

A13

A12

L8

L2

EBI1_DDR_A14

EBI1_DDR_A15

EBI1 _ 0 M Q D

1V8 1V8

A2

B3

U

M

S/D Q

RDQS/N

RD

2

1

A1

A13

2

L8

L

4

5 A1

A1 R_

R_ D D _

_DD

EBI1

E9

A1

VDD

BA0G2O

BA1

G3

1

EBI

BA1_EBI1

BA0_

nFC

nF 00

00

0 1

2 100nFC82 100nF

8

C

H9

A1

E9

D

D VD

VD

BA1

BA0

3

2

G

1

EBI

_EBI1

_

BA1

BA0

BA1_EBI1

BA0_EBI1

C85 100nFC85 100nF

VDDH9VDD

00nFC84100nF 1

C84

D VD

10

11

9

D12

_D

_

_D

R

D

1_D

EBI

EBI1_D

EBI1_DDR_D8

EBI1_D

EBI

EBI1_DDR_D14

EBI1_DDR_D15

EBI1_DDR_D13

9

1 D

B1

C8

D7

D

B9

C2

D3

B7

7

Q4

Q6

Q5

Q

DQ0

DQ2

D

DQ1

DQ3

D

DQS

F-3

F-3 C

C

DRAM

M8

M8 4

4

MN9

S

S 2

2 R

R DD

DD

MT47H6

A0

A2

A4

A1

A3

A6

A8

A5

A7

2 J

A5 _

_DDR 1

EBI

1_DDR_D3

EBI

D3

DQ2

3

-

F

F C

C M8

M8 4

4 H6

H6 7

7

MT4

A2

J2

DDR_A5 _

EBI1

J8

DR_A6 D

BI1_ E

D4 _

1_DDR

EBI

D1

4

DQ3

DQ

A3

A4J8A5

DDR_A6 _

EBI1

J7

J3

A8

A7 _

R_ D

DR

D

_

I1 EB

EBI1

D5

D6 _

_

1_DDR

EBI

D9

B1

6

5

DQ

A6

J3

J7

DDR_A7

DDR_A8

_

EBI1

K2

K8

0 A1

A9

R_

D

_ 1

EBI

EBI1_

D7 _

1_DDR

EBI

B9

7

DQ

A7

K2

K8

0

A9

A1 R_

R_ D

D D

D

_

EBI1

A9

K3

1 A1 R_

D

EBI1_D

EBI1 _

S0 Q D

B7

S

Q D

A8

A9

K3

1 A1 R_

D D _

EBI1

3

8

7

H

A3 _

DR_A2

DR_A4

DR

D

_ 1

EBI1_

EBI

1_DDR_D2

1_DDR_D0

1_DDR_D1

EBI

C2

C8

D7

DQ1

DQ0

AM

AM R

R SD

SD

MN8

2

2 R

R DD

DD

A1

A0

H8

H3

H7

_A2 R

DDR_A4 _

EBI1_DDR_A3

EBI1_DD

EBI1

] 5

15] .

1 ..

0. [

A[1..21] _

A[2

_D

_

R

DR

DD

FLASH

D

_

EBI1

DDR_VREF

EBI1_NCS0

Optional 16bits DATA BUS

With AT29F2G16ABD Micron

C103 100nFC103 100nF

C104 100nFC104 100nF

C106 100nFC106 100nF

C105 100nFC105 100nF

EBI1_NAND_FSH_D4

EBI1_NAND_FSH_D3

EBI1_NAND_FSH_D1

EBI1_NAND_FSH_D5

EBI1_NAND_FSH_D0

EBI1_NAND_FSH_D2

D8

E7

D2

VSSQ

VSSDL

RFU2

RFU1

RFU3

L3

L7

D2

E7

D8

VSSQ

VSSDL

2

1 U

U F

F R

R

RFU3

7 L

L3

H4

K4

K7

K6

K5

J7

J4

I/O3

I/O5

I/O0

I/O2

I/O6

I/O4

I/O1

SH

8ABD

A

G0

29F2

NAND FL

MT

1

WE

CE

RE

R/B

CLE

ALE

MN1

6

C7

C4

C

D4

C8

D5

REWECE

RB EBI1_NAND_FSH_D6

R

R 0

0

0R

R430RR43

R46 470KR46 470K

R420RR42

R44

1V8

JP10JP10

)

E

DAL

DCLE)

AN

(RDY/BSY

(N

(NCS3)

E

PC8

O

W

PC4

PC5

PC14

EBI1_NAND

1_NAND_FSH_D[0..15]

EBI

EBI1_NAND_FSH_D7

J8

K

K 1

1

5

5 4

4 R

R

EBI1_NAND_FSH_D14

EBI1_NAND_FSH_D8

EBI1_NAND_FSH_D12

EBI1_NAND_FSH_D11

EBI1_NAND_FSH_D9

EBI1_NAND_FSH_D13

EBI1_NAND_FSH_D15

EBI1_NAND_FSH_D10

G6

H7

H6

H3

G7

J5

J3

I/O7

N.C32

N.C29

N.C27

N.C31

N.C33

N.C28H5N.C30

N.C26

P

OCK

N.C1

N.C3

W

N.C2

L

N.C4

A2

B1

A9

A1

C3

G5

A10

WP

470K

R47

DNP

1

1 4

4 R

R

1V8

L9

M2

G4

J6

K3

D3

VCC

N.C13

N.C15

N.C14

E6

E7

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Ther .

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C5

F7

H8

E8

K8

VSS

VCC

VFBGA-63

4

5 2

2

.C22

.C

.C19

.C21

.C23

.C

.C20

N.C16

F3

CC. E

N

N.C17

F4

N

N.C18

F5

MT29F2G08ABDHC:D

1

2

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F6

F8

G3

G8

with

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Flas nd

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M9

M1

L10

M10

N.C34

N.C38

N.C35

N.C37

N.C39

N.C36

1

2

1

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.C9

.C8

.C10

.C N

N

N.C5

N.C7

N

N.C6

N

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E5

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D8

D6

D7

B10

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4-6 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

4.2.5 Power Supplies

The SAM9M10 Board contains four regulated power supplies:

 3.3 VDC Supply

 1.8 VDC Supply

 1.0 VDC Core Supply

 1.0 VDC Core UTMI Supply, PLL

The outputs of these regulated power supplies1 are distributed as necessary to each part of the circuit board.

 The 3.3 VDC Supply is generated by an adjustable LDO. It accepts VIN 5 VCC power and outputs a

regulated +3.3 V to most other circuits on the board.

 The 1.8 VDC Supply (VDDIOM0, VDDIOM1) is generated by an adjustable LDO. It is powered by VIN

5 VCC power and outputs a regulated +1.8V.

 The 1.0 VDC Core Supply (VDDCORE) is generated by an adjustable LDO. It is powered by the

output of the 3.3 VDC Supply.

 The 1.0 VDC Core Supply (VDDUTMIC, VDDPLLUTMI and VDDPLLA) is generated by an adjustable

LDO RT9186A series. It is powered by the output of the 3.3 VDC Supply.

Board Description

Note: 1. Corresponding test points (TP1 to TP4, GND) are used with jumpers (JP1.1 to JP7) to

permit probing of these voltages.

AT91SAM9M10-G45-EK User Guide 4-7

6495B–ATARM–21-Apr-10

Board Description

1V_VDDUTMIC

3V3

1V

1V8

1V_VDDUTMIC

VDDUTMII

VDDANA

VDDOSC

VDDIOP0

VDDIOP1

VDDIOP2

VDDISI

VDDUTMIC

VDDPLLUTMI

VDDPLLA

VDDCORE

VDDIOM0

VDDIOM1

VDDBU

J3J3

JP3JP3

1

2

3

C29

4.7u

C29

4.7u

J1-1J1-1

1

2

C2

4.7uC24.7u

JP1JP1

1

2

3

C14

4.7u

C14

4.7u

R201RR20 1R

C221uC22 1u

JP2JP2

1

2

3

C1 100nC1100n

J1-3J1-3

5 6

R13

100k

R13

100k

R10 100k

C15

2.2u

C15

2.2u

R121RR12 1R

JP7JP7

1

2

3

C18 100n

JP6JP6

1

2

3

C251uC25

1u

C20

4.7u

C20

4.7u

MN3 RT9186A

VIN

1

VIN

2

PGOOD

3

EN

4

GND

5

ADJ

6

VOUT

7

VOUT

8

EP

9

C30 100n

JP5JP5

1

2

3

C28 100n

L4 10uHL4 10uH

R51RR5 1R

J1-2J1-2

3 4

C21 10u

C19

10n

C19

10n

L3 10uHL3 10uH

L1 10uHL1 10uH

R19 47k

R14 12k

C8 100nC8100n

J1-4J1-4

7

8

L2 10uHL2 10uH

R11RR1 1R

Figure 4-5. Power Supply

4-8 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Figure 4-6. Management Power Block

PWR_EN

5V

1V

5V

1V8

5V

3V3

5V

3V3

SHDN

FORCE POWER ON

REGULATED

5V ONLY

MN4 RT9018A

PGOOD

1

EN

2

VIN

3

VDD

4

NC

5

VOUT

6

ADJ

7

GND

8

EP

9

C9 10uC910u

C12 10u

R9 100kR9100k

R18 12k

C111uC11 1u

C261uC26 1u

R11 100k

C23 10u

R16 10k

C3 10nC3 10n

MN1 RT9186A

VIN

1

VIN

2

PGOOD

3

EN

4

GND

5

ADJ

6

VOUT

7

VOUT

8

EP

9

R2 100kR2100k

C16 10nC16 10n

C5 10nC510n

C4

33u

+

C4

33u

R6 12kR612k

R4 47kR4 47k

C17

15p

C17

15p

R15 15kR15 15k

C71uC7

1u

R7 15kR715k

JP4

SIP2

JP4

SIP2

12

CR15VCR1 5V

MN2 RT9018A

PGOOD

1

EN

2

VIN

3

VDD4NC

5

VOUT

6

ADJ

7

GND

8

EP

9

Q1

Si1563EDH

Q1

Si1563EDH

1 3

2

4

5

6

C6 10uC610u

R199

100k

R199

100k

J2

DC POWER JACK

J2

DC POWER JACK

1

2

3

R8 47kR847k

C131uC13 1u

R17 10k

C27 10u

C101uC10 1u

C241uC24 1u

R3 100kR3100k

Board Description

AT91SAM9M10-G45-EK User Guide 4-9

6495B–ATARM–21-Apr-10

Board Description

TDI

RTCK TDO

TMS TCK

NTRST

NRST

3V3 3V3

3V3

NTRST

RTCK

TDI TMS TCK

TDO NRST

ICE INTERFACE

R92 0RR92 0R

J13

HTST-110-01-SM-D

J13

HTST-110-01-SM-D

12

3

4

5

6

7

8

9

10

11

12

13 15 17 19

14 16 18 20

R94 0R

DNP

R94 0R

DNP

R93 0RR93 0R

R91 0R

DNP

R91 0R

DNP

RR43

100k

RR43

100k

123

4 5

678

3V3

PB13

PB12

SERIAL DEBUG PORT

C1+

V+

VCC

C1C2+

C2-V-

T

R

GND

MN15

ADM3202ARNZ

C1+

V+

VCC

C1C2+

C2-V-

GND

MN15

ADM3202ARNZ

1

16

3

4

5

15

11

10

12

98

13

7

14

2

6

R87 100k

C159 100n

R90 0RR90 0R

C163 100n

C157 100nC157 100n

R88 100k

C158 100nC158 100n

J10J10

5

4

3

2

1

9

8

7

6

10

11

C165 100nC165 100n

4.2.6 Debug Interface

4.2.6.1 JTAG/ICE

Software debug is accessed by a standard 20-pin JTAG connection. This allows connection to a standard USB-to-JTAG in-circuit emulator.

Figure 4-7. JTAG Interface

4.2.6.2 DBGU Com Port

This UART is connected to the DB-9 male socket through an RS-232 Transceiver (TXD and RXD only).

Figure 4-8. DBGU Com Port

4-10 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

4.2.6.3 User Serial Com Port

3V3

PB5

PD17

PB4

PD16

RS232 COM PORT

C161 100n

C1+V+VCC

C1C2+

C2- V-

T

R

GND

MN16

ADM3202ARNZ

C1+V+VCC

C1C2+

C2- V-

GND

MN16

ADM3202ARNZ

1 16

3

4

5

15

11

10

12

9 8

13

7

14

2

6

C166 100nC166 100n

C162 100nC162 100n

C160 100n

J11J11

5

4

3

2

1

9

8

7

6

10

11

R86 100k

C164 100n

R89 100k

The USART1 is used as a user serial communication port. This USART1 is buffered with an RS-232 Transceiver (TXD, RXD and handshake CTS/RTS control) and connected to the DB-9 male socket. Soft ware must assign the appropriate PIO pins (PB5 = RXD1, PB4 = TXD1, PD16 = RTS1, PD17 = CTS1) to enable the UART1 function.

Figure 4-9. User Serial Com Port

Refer to the SAM9M10 datasheet for more information about the SAM9M10 USARTs.

Board Description

-

4.2.6.4 USB Port

The SAM9M10-G45-EK features USB communication ports:

 Two Host Ports: Full speed OHCI and High speed EHCI

 One Device Port: High speed.

USB Host Port0 is directly connected to the first UTMI transceiver. The second Host Port (Port1) is multiplexed with the USB Device High speed and connected to the second UTMI port.

 One USB high/full speed type standard A connector

 One USB interface Host/Device Micro AB connector

Refer to the SAM9M10 datasheet for detailed programming information.

AT91SAM9M10-G45-EK User Guide 4-11

6495B–ATARM–21-Apr-10

Board Description

5V

3V3

PD2

PD4

PD1

HDMA

HDPA

PD3

HDMB HDPB PD28

PB19

USB HOST/DEVICE INTERFACE

USB HOST INTERFACE

(ENA)

(ENB)

(FLGA)

(FLGB)

(VBUS)

(IDUSB)

C171 10p

R96 68k

R95 47kR95 47k

+

C170

33u

+

C170

33u

C169 100n

J12 G3505-4NBT1S1W

1

4

5

2

3

6

SHIELD

J14

G3515-09010101-00

VBUS

DM DP

ID

GND

USB-A

J14

G3515-09010101-00

1 2

3

4 5

7

6

+

C168

33u

+

C168

33u

R97 47k

L14

220ohm at 100MHz

L14

220ohm at 100MHz

1

2

C167 100n

MN17

AIC1526-0GS

MN17

AIC1526-0GS

ENA

1

FLGA

2

ENB

4

OUTA

8

GNG6FLGB

3

IN

7

OUTB

5

L13

220ohm at 100MHz

L13

220ohm at 100MHz

1 2

C172

100n

C172

100n

Figure 4-10. USB Port

4.2.6.5 Ethernet 10/100 (EMAC) Port

The port is compatible with IEEE® Standard 802.3.

The SAM9M10-G45-EK is equipped with a Davicom DM9161AEP 10/100 Mbps Fast Ethernet Physical Layer TX/FX Single Chip Transceiver. It contains the entire physical layer functions of 100BASE-TX as defined by IEEE 802.3u, including the Physical Coding Sublayer (PCS), Physical Medium attachment (PMA), Twisted Pair Physical Medium Dependent Sublayer (TP-PMD), 10BASE-TX Encoder/Decoder (ENC/DEC), and Twisted Pair Media Access Unit (TPMAU).

The Ethernet interface integrates an RJ45 connector with an embedded transformer, and three status LEDs.

The Ethernet interface provides two selectable modes, MII or RMII (Reduced MII), for 100Base-TX or 10Base-TX. The MII and RMII interfaces are capable of both 10Mb/s and 100Mb/s data rates as described in the IEEE 802.3u standard. The signals used by MII and RMII interfaces are described in the table below.

4-12 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Board Description

Table 4-2. Pin Mapping for Normal MII and Reduced MII

Pin Name Normal MII Mode Reduced MII Mode

SAM9M10 DM9161 SAM9M10 DM9161

ETX0-ETX1 ETX[0:1] transmit data TXD [0:1] ETX[0:1] TXD [0:1]

ETX2-ETX3 ETX[2:3] transmit data TXD [2:3] NC NC

ETXEN ETXEN: transmit enable TXEN ETXEN: transmit enable TXEN

ETXER ETXER: transmit error TXER/TXD[4] NC NC

ETXCK/REFCK ETXCK: transmit clock TXCLK REFCK: reference clock REF_CLK

ERX0-ERX1 ERX[0:1]: receive data RXD [0:1] ERX[0:1]: receive data RXD [0:1]

ERX2-ERX3 ERX[2:3]: receive data RXD [2:3] NC NC

ERXER ERXER: receive error

ERXDV ERXDV: receive valid data RXDV

RXER/RXD[4]/ RPTR/NODE

ERXER: receive error RPTR/NODE

ECRSDV: carrier sense / data valid

CRS DV

ERXCK ERXCK: receive clock RXCLK NC NC

ECOL ECOL: collision detect COL NC NC

ECRS

EMDC EMDC: management data clock MDC

EMDIO

NRST NRST: microcontroller reset

ECRS: carrier sense / data valid

EMDIO: management data input / output

CRS (PHYAD[2:4] NC NC

MDIO

RESET# XT1 (25 MHz)

EMDC: management data clock

EMDIO: management data input / output

NRST: microcontroller reset

MDC

MDIO

RESET# XT1 (REF_CLK 50MHz)

AT91SAM9M10-G45-EK User Guide 4-13

6495B–ATARM–21-Apr-10

Board Description

Figure 4-11. Ethernet Port

GND_ETH

C176

100n

C176

100n

R107

R102

49.9R

1

TX+

16

15

J15

TD+

1

3

AVDDT

RX+

RD+

365

6

RX-

RD-

CT

2

TX-

TD-

CT

2

4

5

7

4

8

75

7575

1nF

J00-0061NL

NC

7

C178

100n

C178

100n

49.9R

R113

R111

49.9R

R111

49.9R

AVDDT

2

L15

2200R

L15

2200R

1

J00-0061NL

8

RJ45 ETHERNET CONNECTOR

GND_ETH

C183

100n

C183

100n

GND_ETH

10V

C181

10u

C181

10u

GND_ETH

3V3

C180

10u

10V

C180

10u

10V

6 7

8

3V3

R118

10k

RR47

SPEED 100

FULL DUPLEX

470R

R119

1

12

D4 YellowD4 Yellow

D5 GreenD5 Green

2

4 5

3

2 1

R121

LINK&ACT

470R

GreenD6Green

12

D6

R117

6.8k

R117

6.8k

AVDDT

MDC

R116 0RR116 0R

C182 100nC182 100n

11

48

31

BGRES

LEDMODE

DGND

15

33

RR46

RR45

RR44

10k

44

DGND

45

14

N.C

LED2/OP213LED1/OP112LED0/OP0

CABLESTS/LINKSTS

C187

PWRDWN10DGND

RESET

40

R120 0RR120 0R

NRST

C187

3V3

GND_ETH

R123 0RR123 0R

10u

10V

R122 0RR122 0R

9

6

46

47

AGND5AGND

AGND

AVDDT

BGRESG

DM9161AEP

MDIO25MDINTR

DVDD

DISMDIX

32

39

3V3

2

JP16JP16

6 7

8

6 7

8

6 7

8

41

C184100nC184100n

1

DVDD

23

30

C186100nC186100n

C185100nC185100n

4 5

3

2 1

3V3

4 5

3

2 1

4 5

3

2 1

C177 100nC177 100n

C179 100nC179 100n

4

3

TXD317TXD2

DNP

R108 0R

R103 0R DNPR103 0R DNP

7

18

TX+

TX_EN

TXD020TXD119TX_CLK/ISOLATE

21

22

R106 0R DNPR106 0R DNP

8

TX-

RX+

RXD0/PHYAD029RXD1/PHYAD128RXD2/PHYAD227RXD3/PHYAD3

26

DNP

R104 0R DNPR104 0R DNP

R105 0R

43

C175

22p

DNP

C175

22p

DNP

Y5

24

1 3

C174

22p

DNP

C174

22p

DNP

R100 0R

C173

100n

C173

3V3

100n

32

41

VDD

50MHz

VSS OUT

OE

VSS OUT

OE

R98 10kR98 10k

Y4

XT1

25MHz

DNPY525MHz

DNP

REF_CLK/XT2

MN18

42

R101 0RR101 0R

R990RR99

0R

34

DNP

R109 0R

RX_CLK/10BTSER

37

RX-

RX_DV/TESTMODE

R110 0R DNPR110 0R DNP

16

TX_ER/TXD4

38

RX_ER/RXD4/RPTR

1

AVDDR

COL/RMII

36

R112 0R DNPR112 0R DNP

R114 0R DNPR114 0R DNP

35

2

AVDDR

CRS/PHYAD4

24

R115 1.5kR115 1.5k

3V3

(TX_CLK)

PA17

(TXD3)

(TXD2)

PA7

(RXD2)

(TXD1)

(TXD0)

(TX_EN)

(RXD3)

PA14

PA6

PA11

PA9

PA10

(TX_ER)

(RXD1)

PA8

(RX_ER)

(RXD0)

(RX_CLK)

(RX_DV)

PA27

PA15

PA28

PA12

PA13

(MDINTR)

(COL)

(CRS)

(MDC)

(MDIO)

PD5

PA19

PA16

PA18

PA29

PA30

For more information about the Ethernet controller device, refer to the Davicom DM9161 controller manufacturer's datasheet.

4-14 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

4.2.7 Audio Stereo Interface

The SAM9M10-G45-EK includes a WM9711L AC97 CODEC for digital sound input and output. This interface includes audio jacks for MIC input (J9), line audio input (J8), headphone line output (J7) and a 2-point speaker output connector (JP15).

It is compliant with AC97 Component Specification V2.2.

Board Description

AT91SAM9M10-G45-EK User Guide 4-15

6495B–ATARM–21-Apr-10

Board Description

Figure 4-12. Audio Stereo Interface

R73 10kR73 10k

JP17/JP18 are used

as testpoints

3V3

C136

C136 100n

100n

R74 100kR74 100k

3V3

AGND_AC97

1 2

3

4 5 6 7

8

9 10 11 12

MN14

DBVDD XTLIN XTLOUT DGND1 SDATAOUT BITCLK DGND2 SDATAIN DCVDD SYNC RESET CREF

PE31

PD7 PD9

PD6

PD8 NRST

(EXT_CLK)

C133 22pC133 22p

C137 22pC137 22p

DNP

R75 0R

Y3

2 4

24.576MHzY324.576MHz

1 3

(AC97TX) (AC97CK)

(AC97RX)

(AC97FS)

C134

C135

10u

10V

100n

R78 49.9RR78 49.9R

AVDD_AC97

JP17 DNPJP17 DNP

12

DNP

JP18

12

48

47

46

49

GPIO4

THERMAL

GPIO5/SPDIF

44

45

43

42

GPIO3

GPIO1

HPVDD

GPIO2/IRQ

WM9711L

41

AGND2

HP_OUT_R

40

HP_GND

38

39

SPKVDD

HP_OUT_L

C130

100n

37

C131

100n

AGND_AC97

OUT3

ROUT2

LOUT2

SPKGND

MONOOUT

CAP2 COMP3 COMP2 COMP1

MICBIAS

VREF

AGND

AVDD1

10u

10V

36 35 34 33 32 31 30

29 28 27 26 25

C132

R69 0RR69 0R

R70 0RR70 0R

1 2

JP14

DNP

C138

C138 100n

100n

C126 100u/6.3V

C127 100u/6.3V

AGND_AC97

C139

C139 100n

100n

C140

C140 10u

10u

10V

+

C141

C141 100n

100n

R71

R71 47k

47k

R76 0RR76 0R

R77 0RR77 0R

C142

C142 10u

10u

10V

C143

C143 100n

100n

R72

R72 47k

47k

AGND_AC97

C144

C144 10u

10u

10V

L6

L6 220ohm at 100MHz

220ohm at 100MHz

2

1

1 2

L7

L7 220ohm at 100MHz

220ohm at 100MHz

12

JP15

8 Ohm SPEAKER

DNP

OUTPUT

C128

C128 470p

470p

C129

C129 470p

470p

1

HEADPHONE LINE-OUT

2 5

3

STEREO_3.5mm

J7

4

AVDD_AC97

C145

C145 100n

100n

AGND_AC97

3V3 AVDD_AC97

L11

L11 10uH

10uH

C152

C153

10u

100n

10V

R850RR850R

C154

C154 10u

10u

10V

AGND_AC97

NC114NC215PHONE20PCBEEP19AGND118LINE_IN_L23LINE_IN_R

MIC121MIC2

AVDD2

NC417NC3

22

13

16

AGND_AC97

R83

R83 680R

680R

AGND_AC97

R84

R84 680R

680R

R81

8.2K

R82

8.2K

AGND_AC97

R79 8.2KR79 8.2K

R80 8.2KR80 8.2K

L8

L8 220ohm at 100MHz

220ohm at 100MHz

1 2

L9

1 2

220ohm at 100MHz

L10

L10 220ohm at 100MHz

220ohm at 100MHz

2

1

1 2

L12

L12 220ohm at 100MHz

220ohm at 100MHz

C148

C148 470p

470p

C155

C155 470p

470p

C149

C149 470p

470p

C156

C156 470p

470p

2 5

1

3 4

STEREO_3.5mm

MONO / STEREO MICROPHONE INPUT

2 5

1

3 4

STEREO_3.5mm

LINE-IN

J8

J9

24

C1461uC146 1u

C1471uC147 1u

C1501uC150 1u

C1511uC151 1u

AGND_AC97

For more information about the AC97 codec device, refer to the Wolfson WM9711L controller manufacturer's datasheet.

4-16 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

4.2.8 TV-Out Extension

PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14

PE6

PE17

PE12

PE28

PE23

PE7

PE1

PE18

PE13

PE29

PE24

PE8

PE2

PE0

PE19

PE3

PE14

PE25

PE9

PE20

PE4

PE15

PE26

PE10

PE21

PE5

PE16

PE11

PE27

PE30

PE22

1V8

3V3

PE[0..30]

PA21

NRST

PA20

TV_XCLK

TV_HSYNC

TV_VSYNC

Composite

Video

Output

(LCDMOD)

(G4)

(R6)

(B3)

(LCDPWR)

(G5)

(LCDDEN)

(LCDCC)

(R7)

(G0)

(B4)

(G6)

(B5)

(R2)

(G7)

(B0)

(G1)

(B6)

(R3)

(G2)

(B7)

(R1)

(R4)

(B1)

(G3)

(LCDDOTCK)

(R5)

(R0)

(B2)

(HSYNC) (VSYNC)

(TW DO) (TW CK0)

L21 2200R

1

2

C197 100n

MN20

CH7024B

MN20

CH7024B

D7

1

D8

2

D9

3

D10

4

D11

5

D12

6

D13

7

D14

8

D15

9

D16

10

D17

11

D18

12

D19

13

D20

14

D21

15

D22

17

D23

19

D0

42

D1

43

D2

44

D3

45

D4

46

D5

47

D6

48

V

39

H

40

XCLK

41

DE

20

RESET

23

VDDIO

38

AVDD_DAC

25

DVDD

16

AVDD_PLL

32

AVDD

33

DGND

18

AGND_DAC

29

AGND_PLL

31

AGND

36

SPD

21

SPC

22

NC

24

C/CVBS

26

Y

27

CVBS

28

ISET

30

XI/FIN34XO

35

P-OUT

37

D8

BAT54SLT1G

D8

BAT54SLT1G

1 2

3

R1804.7kR1804.7k

C204 33pC204 33p

C206 100p

C200 100n

R183 75RR183 75R

C205 100p

C208 10p

R178 1.2k

1%

R178 1.2k

1%

L18 2200R

1

2

J20J20

RCA JACK

3

1

C203 100n

C199 10u

10V

C199 10u

10V

C202 100n

R1860R

DNP

R1860R

DNP

VDD

VSS OUT

OE

Y6

13MHz

DNP

VDD

VSS OUT

OE

Y6

13MHz

DNP

41

32

C207 100n

DNP

C207 100n

DNP

R18175RR18175R

TP6TP6

R1850RR185 0R

L17 2200R

1

2

L22

1.8uH

L22

1.8uH

R179 4.7kR179 4.7k

R182 75R

C198 10u

10V

C198 10u

10V

L19 2200R

1

2

L20 2200R

1

2

C196 100n

Y7

13MHzY713MHz

1 3

24

C209 10p

R18410kDNPR18410kDNP

C201 10u

10V

C201 10u

10V

The Chrontel™ CH7024 chip provides an interface between the SAM9M10 LCD Controller and a TV set by converting LCD signals to TV signals.

The CH7024 is a TV encoder device which encodes the video signals and generates synchronization signals for NTSC and PAL standards. Supported TV output formats are NTSC-M, NTSC-J, NTSC-433, PAL-B/D/G/A/I, PAL-M, PAL-N and PAL-60. The CH7024 provides video output support for CVBS or Svideo.

Figure 4-13. TV-Out Extension Port

Board Description

AT91SAM9M10-G45-EK User Guide 4-17

6495B–ATARM–21-Apr-10

Board Description

4.2.9 Software Controlled LEDs

Three users LED are provided for general use. The LEDs are connected to PIO port lines, allowing their control through either GPIO or PWM control.

 LEDs D1 to D3 are software controlled by PIO pins.

 LEDs D4 to D6 indicate Ethernet traffic and link status. These are automatically managed by on-chip

microcontroller hardware. See Section 7.1 ”Schematics” .

Table 4-3. Discrete LEDs

LED Description Comment

D1 Green LED User software controlled

D2 Green LED User software controlled

D3 Red LED User software controlled

D4 Yellow LED Indicates transmission or reception via Ethernet

D5 Green LED Indicates speed 100

D6 Green LED Is lit when a good link test has been detected

Figure 4-14. Software Controlled LEDs

USER INTERFACE

3V3

R25

470R

12

IRLML2402

D3 RedD3Red

3

Q2

2

R26

R26 100k

100k

1

PD30

POWER LED

PB[14..18]

3V3

GreenD1Green

D1

1

D2

1 2

GreenD2Green

PB15 PB16

PB14 PB18

PB17

C32

10n

R21 470RR21 470R

R22 470RR22 470R

LEFT PUSH

C34

10n

BP3BP3

1

2

3

JOYSTICK

R28

R28 100R

100R

4 5 6

UP RIGHT DOWN

C35

10n

PD0

PD31

C36

10n

2

C33

10n

4-18 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

4.2.10 Serial Peripheral Interface Controller (SPI)

3V3

PB1 PB2 PB3

PB0

NRST

SERIAL DATAFLASH

(test points)

(SPI0_MISO) (SPI0_MOSI) (SPI0_SPCK) (SPI0_NPCS0)

JP12 SIP2

1

2

C124 100n

JP11

DNP

JP11

DNP

1

2

3

R67 470k

MN13MN13

RESET

3

GND

7

VCC

6

CS

4

SCK

2

SI

1

SO

8

WP

5

R68 0R

DNP

R68 0R

DNP

3V3

PA21

PA20

SERIAL EEPROM

(TW CK0) (TW DO)

JP13

SIP2

JP13

SIP2

12

R66 10k

C125 100nC125 100n

MN12MN12

A0

1

A1

2

WP

7

SCL

6

VCC

8

A3

3

SDA

5

GND

4

Board Description

The SAM9M10 provides two high-speed Serial Peripheral Interface (SPI) controllers. One port is used to interface with the on-board serial DataFlash

Figure 4-15. SPI

4.2.11 Two Wire Interface (TWI)

The SAM9M10 has a full speed (400 kHz) master/slave I2C Serial Controller. The controller is fully compatible with the industry standard I2C and SMBus Interfaces. This port is used to interface with the onboard Serial EEPROM, ISI and TV encoder interface.

Figure 4-16. TWI

®

.

4.2.12 SD/MMC Interface

The SAM9M10-G45-EK has two high-speed 8-bit multimedia interfaces MMC/MMCPlus v4.1. The first interface is used as an 8-bit interface (MCI1), connected to a CE-ATA connector footprint and an 8-bit SD/MMC card slot. The second interface is used as a 4-bit interface (MCI0), connected to a 4-bit SD/MMC card slot.

The users must provide their own compatible cards for use with these connectors.

Please note that the power is connected to VCC, which is 3.3 volts.

AT91SAM9M10-G45-EK User Guide 4-19

6495B–ATARM–21-Apr-10

Board Description

PA26 PA25

PA27 PA28 PA29 PA30

PA24 PA23

PA31

PA22

3V3

PD29 PD11

PA[22..31]

SD/MMCPlus CARD INTERFACE - MCI1

(MCI1_DA1) (MCI1_DA0)

(MCI1_CK)

(MCI1_CDA) (MCI1_DA3) (MCI1_DA2)

(MCI1_DA4) (MCI1_DA5)

(MCI1_DA7)

(MCI1_DA6)

(MCI1_CD)

(MCI1_W P)

RR36 10k

123

4 5

678

R192

68k

R192

68k

RR39

27R

RR39

27R

1 2

3

4

5

6

7

8

R193

68k

R193

68k

C123 100n

R194

68k

R194

68k

RR41 27RRR41 27R

1 2

3

4

5

6

7

8

R195

68k

R195

68k

RR42

27R

RR42

27R

1 2

3

4 5

6

7

8

R196

68k

R196

68k

R197

68k

R197

68k

R198

68k

R198

68k

J5J5

8

5

7 6

4

3

2 1 9

14

15

16

13 12 11 10

R191

68k

R191

68k

PA1 PA5 PA4

PA

3

PA2

PA0

3V3

PD10

PA[0..5]

SD/MMC CARD INTERFACE - MCI0

(MCI0_DA1) (MCI0_DA0)

(MCI0_CK)

(MCI0_CDA) (MCI0_DA3) (MCI0_DA2)

(MCI0_CD)

R188

68k

R188

68k

R189

68k

R189

68k

R187

68k

R187

68k

R64 10k

R190

68k

R190

68k

R65 10k

RR38 27RRR38 27R

1 2

3

4

5

6

7

8

J6J6

8

5

7 6

4

3

2 1 9

10

11

12

RR40 27RRR40 27R

1 2

3

4

5

6

7

8

C122 100nC122 100n

Figure 4-17. SD/MMC0

Figure 4-18. SD/MMC1

4.2.13 TFT LCD with Touch Panel

The SAM9M10 features an LCD controller. A 4.3" 480x272 Portrait Mode LCD provides the SAM9M10G45-EK with a low power LCD display, back light unit and a touch panel, similar to that used on commer cial PDAs.

The TFT LCD component is a truly model number TFT1N4633.

Graphics and text can be displayed on the dot matrix panel with up to 16 million colors by supplying 24bit data signals (8bitxRGB by default) or 16-bit data signals (5+6+5bitxRGB in option). This allows the user to develop graphical user interfaces for a wide variety of end applications.

Warning: never connect/disconnect the LCD display from the board while the power supply is on. Doing so may damage both units and is not covered by warranty.

The back light voltage is generated from a CP2122ST boost converter. It is powered directly by the VIN 5

VCC power (the control for the back light voltages is separated from the main board voltages due to

the specific voltage requirements of the LCD panel).

4-20 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

-

Figure 4-19. TFT LCD

pin1

pin2

pin3

pin29

pin4

pin37

4.3" 480x272 TFT LCD DISPLAY

pin38

pin39

pin32

pin40

pin33

pin42

pin43

20mA MAX

(LCDPWR)

pin35

9 LEDs Back Light

pin36

pin41

pin34

pin5

pin6

pin7

pin8

pin9

pin10

pin11

pin12

pin13

pin14

pin15

pin16

pin17

pin18

pin19

pin20

pin21

pin22

pin23

pin24

pin25

pin26

pin27

pin28

pin30

pin31

pin44

pin45

(pinxx = display pin number )

(LCDDEN)

(G4)

(R6)

(B3)

(LCDPWR)

(G5)

(LCDDEN)

(LCDCC)

(R7)

(G0)

(B4)

(G6)

(B5)

(R2)

(G7)

(B0)

(G1)

(B6)

(R3)

(G2)

(B7)

(R1)

(R4)

(B1)

(G3)

(LCDDOTCK)

(R5)

(R0)

(B2)

(AD1Xm) (AD3Ym) (AD0Xp)

(AD2Yp)

(LCDCC)

R48 is placed near processor

YpLCD

VLED-

XmLCD YmLCD

VLED+

XpLCD YmLCD XmLCD

YpLCD

VLED-

VLED+

XpLCD

BLUE6

BLUE7

RED0

BLUE2

BLUE3

BLUE4

BLUE5

BLUE0

BLUE1

GREEN5

GREEN6

GREEN7

GREEN2

GREEN3

GREEN4

RED6

RED7

GREEN0

GREEN1

RED2

RED3

RED4

RED5

RED1

PE0 LCDDOTCK

PE2

RED3

PE8 PE10

RED4

PE9 PE11

RED5

PE10 PE12

RED6

PE11 PE13

RED7

PE12 PE14

GREEN2

PE13 PE17

PE14

GREEN3

PE18

PE19

GREEN4

PE15

PE20

GREEN5

PE16

PE21

GREEN6

PE17

PE22

GREEN7

PE18

PE26

PE20

BLUE3

PE27

BLUE4

PE21

PE28

BLUE5

PE22

PE29

BLUE6

PE23

PE30

BLUE7

PE24

PE7

PE8

PE9

PE15

PE16

PE23

PE24

PE25

PE6

PE17

PE12

PE28

PE23

PE7

PE1

PE18

PE13

PE29

PE24

PE8

PE2

PE0

PE19

PE3

PE14

PE25

PE9

PE20

PE4

PE15

PE26

PE10

PE21

PE5

PE16

PE11

PE27

PE30

PE22

3V3

5V

PE[0..30]

PD22 PD21 PD23 PD20

LCDDOTCK

C188

100nF

C188

100nF

Conductors

on

TOP SIDE

LG PHILIPS

Z7

LB043WQ1

Conductors

on

TOP SIDE

PIN 1

PIN 45

LG PHILIPS

Z7

LB043WQ1

R1720RR172

0R

R184 DNPR184 DNP

RR53ARR53A

1

8

RR49CRR49C

3 6

R155 DNPR155 DNP

RR48ARR48A

1

8

RR49DRR49D

4 5

RR53CRR53C

3

6

RR52ARR52A

1 8

C209

DNP

C209

DNP

C210

DNP

C210

DNP

R157 DNPR157 DNP

R178 0RR178 0R

R161 DNPR161 DNP

R154 0RR154 0R

RR49ARR49A

1 8

R148 0RR148 0R

RR50DRR50D

4 5

R164 0RR164 0R

D12

STPS0540Z

D12

STPS0540Z

R130 0RR130 0R

R176 0RR176 0R

C201

2.2uF

C201

2.2uF

RR50CRR50C

3 6

R175 0RR175 0R

R160 0RR160 0R

R123

10R

R123

10R

RR49BRR49B

2 7

RR48DRR48D

4

5

R149 DNPR149 DNP

R182 DNPR182 DNP

R158 0RR158 0R

C189

10V

10uF

C189

10V

10uF

RR51DRR51D

4 5

R48 33RR48 33R

R151 DNPR151 DNP

R180

10K

R180

10K

RR52CRR52C

3 6

RR53BRR53B

2

7

R1500RR150

0R

R152 0RR152 0R

RR48BRR48B

2

7

R173 0RR173 0R

R177 0RR177 0R

RR52DRR52D

4

5

R1740RR174

0R

RR50ARR50A

1 8

R153 DNPR153 DNP

RR50BRR50B

2 7

R50 27RR50 27R

R168 0RR168 0R

R169 DNPR169 DNP

R1620RR162

0R

R136

4.7K

R136

4.7K

R137

10K

R137

10K

RR51BRR51B

2 7

R183 0RR183 0R

C211

DNP

C211

DNP

R144 0RR144 0R

C203

220nF

C203

220nF

R145

DNP

R145

DNP

R1660RR166

0R

R133 0RR133 0R

R179 0RR179 0R

R181 0RR181 0R

R167 DNPR167 DNP

RR51CRR51C

3 6

R163 DNPR163 DNP

RR52BRR52B

2 7

L23

22uH

L23

22uH

J24

XF2M45151A

J24

XF2M45151A

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45

R159 DNPR159 DNP

R165 DNPR165 DNP

RR53DRR53D

4

5

R1320RR132

0R

R156 0RR156 0R

RR48CRR48C

3

6

R170 0RR170 0R

R147 DNPR147 DNP

MN25 TPS61161DRVTMN25 TPS61161DRVT

SW

4

GND

3

FB

1

CTRL

5

COMP

2

VIN

6

THP

7

R131 0RR131 0R

RR51ARR51A

1 8

R171 DNPR171 DNP

R1460RR146

0R

C202

1uF

C202

1uF

C208

DNP

C208

DNP

Board Description

6495B–ATARM–21-Apr-10

AT91SAM9M10-G45-EK User Guide 4-21

Board Description

4.2.14 Push Buttons

The SAM9M10-G45-EK is equipped with two system push buttons, two user push buttons and one joystick. The push buttons consist of momentary push button switches mounted directly to the board. When any switch is depressed, a low (zero) appears at the associated input pin.

 System push buttons:

– Reset, perform system reset

– Wakeup, perform system wake up

 User push button:

– Right click

– Left click

 Joystick:

– One touch, 5-way switching,

– Normally open momentary contacts,

– Push down to select in any position.

Figure 4-20. Push Buttons

4.2.15 Expansion Slot

 GPIO1 & GPIO2, LCD signals (PIO E) are routed to the connectors extension J23

 All I/Os of the SAM9M10 Image Sensor Interface are routed to connectors J17

 Touch screen signals and analog I/O are connected to J18

This allows the developer to extend the features of the board by adding external hardware components or boards.

NRST

WAKE UP

RIGHT CLICK

LEFT CLICK

C31

10n

C37

10n

BP1BP1

BP2BP2

BP4BP4

BP5BP5

R27

100R

R29

100R

VDDBU

R23

R23 100k

100k

3V3

R241kR24 1k

NRST

WAKE UP

PB7

PB6

4-22 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Figure 4-21. Expansion Slot

PE27 PE29

PE25

PE23

PE2 PE1

PE16

PE20

PE18

PE14

PE22

PE10 PE12

PE26

PE30

PE28

PE24

PE6

PE7

PE0

PE9

PE8

PE11 PE13 PE15 PE17

PE21

PE19

PB21 PB23 PB25 PB27 PB9 PB11

PA21

PB31 PB29 PB30 PB28 PB20 PB22 PB24 PB26 PB8 PB10

PA20

3V3

5V

3V3

VDDISI

PD25 PD27 PD19

PD24 PD26 PD18

PD15

PD14

PD21 PD23

PD20 PD22

PD12

PD13

LCDDOTCK

LCDHSYNC

LCDVSYNC

IMAGE SENSOR CONNECTOR

CONNECTOR EXTENSION FOR LARGE LCD

(AD1Xm) (AD3Ym) (AD2Yp)

(AD0Xp)

(GPIO2)(GPIO1)

)2LRTC()1LRTC(

J17

HDR_2x15_SMT

J17

HDR_2x15_SMT

1 2 3 4 5 6 7 8

9 10 11 12 13 15 17 19

14 16 18

20 21 22 23 24 25 26 27 28 29 30

C212 100n

J23

HDR_2x20_SMT

DNP

J23

HDR_2x20_SMT

DNP

1 2 3 4 5

6

7

8

9

10

11 12 13 15 17 19

14

16

18

20

21 22 23 24 25 26 27 28 29

30

31 32 33

34

35 36 37 38 39 40

C210 100n

C211 10u

10V

C211 10u

10V

J18

HDR_2x10_SMT

DNP

J18

HDR_2x10_SMT

DNP

1 2 3 4 5 6 7 8 9

10

11 12 13 15 17 19

14

16

18

20

R175 0R

DNP

R175 0R

DNP

R176 0R

DNP

R176 0R

DNP

Board Description

AT91SAM9M10-G45-EK User Guide 4-23

6495B–ATARM–21-Apr-10

5.1 JTAG/ICE Configuration

Table 5-1. JTAG/ICE Configuration

Designation Default Setting Feature

R91 Not populated Disables the ICE NTRST input

R92 Soldered Enables the ICE RTCK return. R94 must be opened

R93 Soldered Enables the ICE NRST input

R94 Not populated Disables TCK <-> RTCK local loop

5.2 ETHERNET Configuration

RMII is the factory default mode.

To evaluate the MII mode, the user has to unsolder R99 and solder R100, R103 to R105, R108 to R110, R112, R114, C174, C175, Y5.

Section 5

Configuration

AT91SAM9M10-G45-EK User Guide 5-1

6495B–ATARM–21-Apr-10

Configuration

5.3 Jumpers Configuration

Two types of jumpers are used on the SAM9M10-G45-EK board:

 2-pin jumpers with two possible settings:

– Fitted: the circuit is closed

– Not fitted: the circuit is open

 3-pin jumpers with two possible positions, for which settings are presented in the following tables.

Table 5-2. Jumpers Configuration

Default

Designation

J1

(combined

jumper array)

JP1 1-2 JP1

Setting Feature

Closed J1-1 1-2 VDDUTMII 3V3

Closed J1-2 3-4 VDDUTIMC 1V

Closed J1-3 5-6 VDDCORE 1V

Closed J1-4 7-8 VDDPLLUTMI 1V

1-2 VDDIOP0 3V3

2-3 External power to VDDIOP0 3V3 nominal

JP2 1-2 JP2

JP3 1-2 JP3

Forces power on.

JP4 Opened

JP5 1-2 JP5

JP6 1-2 JP6

JP7 1-2 JP7

JP8 Opened

JP9 Closed Enables chip select access, Boot on the NCS0 (MN10 Flash)

JP10 Closed Enables chip select access, Boot on the NCS3 (MN11 NAND Flash)

JP11 Test point JP11.1: SO JP11.2: SI JP11.3: SCK

To use the software shutdown control, JP4 must be opened. 3V battery backup must be present and JP7 jumper set in position 1-2

BMS Enables Boot on the internal ROM; closed selects the boot from the external device connected to NCS0

1-2 VDDIOP1 3V3

2-3 External power to VDDIOP1 3V3 nominal

1-2 VDDIOP2 3V3

2-3 External power to VDDIOP2 3V3 nominal

1-2 VDDIOM0 1V8

2-3 External power to VDDIOM0 1V8 nominal

1-2 VDDIOM1 1V8

2-3 External power to VDDIOM1 1V8 nominal

1-2 VDDBU Lithium 3V Battery

2-3 VDDBU 3.3V from regulator

JP12 Closed Enables chip select access, Boot on the SPIO_NPCS0 (Serial DataFlash MN13)

JP13 Opened Set address A0 low (MN12 Serial EEPROM), enable Boot access.

JP14 JP14.1 = Line_Out JP14.3 = AGND

JP15 Used to connect a Loudspeaker

JP16 Closed DISMDIX (MN18)

JP17-JP18 Test points Give access to the four GPIOs of WM9711L

5-2 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

5.4 Miscellaneous Configuration Items

N.P = not populated

P = populated

Table 5-3. Miscellaneous Configuration

Default

Designation

R34 N.P JTAGSEL

R35 P Connect TSADVREF to VDDANA (may be used for specific filtering)

R36 P Connect GNDANA to GND (may be used for specific filtering)

R38 P Force TST pin to GND (chip is set in non-test mode = normal operation mode)

R63 N.P

Setting Feature

Write protect NAND Flash (mount a 0-ohm resistor to write-protect the NAND Flash device)

Configuration

R68 N.P

R75 N.P External clock Audio AC97 (mount a 0-ohm resistor to connect it)

R91,R92 R93,R94

R100, R103

to R105,

R108 to R110, R112, R114, C174,

C175, Y5

Y6, R184,

R186

TP1 GND Test point

TP2 GND Test point

TP3 GND Test point

TP4 GND Test point

5.5 PIO Configuration

Write protect serial DataFlash (mount a 0-ohm resistor to write-protect the serial Flash device)

ICE interface reset and clocking schemes (see

Configuration”

Ethernet interface, MII mode (see

N.P External 13 MHz oscillator (option) for the on-board video composite encoder

)

Section 5.2 ”ETHERNET Configuration” )

Section 5.1 ”JTAG/ICE

5.5.1 Peripheral Signals Multiplexing on I/O Lines

The AT91SAM9M10 product features 5 PIO controllers, PIOA, PIOB, PIOC, PIOD and PIOE, which multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. The multiplexing tables in the following paragraphs define how the I/O lines of peripherals A and B are multiplexed on the PIO Controllers.

5.5.2 Multiplexing on PIO Controller A (PIOA)

"R.Select" = connection selectable via an on-board resistor (default not populated)

AT91SAM9M10-G45-EK User Guide 5-3

6495B–ATARM–21-Apr-10

Configuration

Table 5-4. PIO Multiplexing Port A

I/O Peripheral A Peripheral B Function and Comments Power

PA0 MCI0_CK TCLK3 MMCI0 Clock VDDIOP0

PA1 MCI0_CDA TIOA3 MMCI0 Command VDDIOP0

PA2 MCI0_DA0 TIOB3 MMCI0 Data0 VDDIOP0

PA3 MCI0_DA1 TCKL4 MMCI0 Data1 VDDIOP0

PA4 MCI0_DA2 TIOA4 MMCI0 Data2 VDDIOP0

PA5 MCI0_DA3 TIOB4 MMCI0 Data3 VDDIOP0

PA6 MCI0_DA4 ETX2 Ethernet MII VDDIOP0

PA7 MCI0_DA5 ETX3 Ethernet MII VDDIOP0

PA8 MCI0_DA6 ERX2 Ethernet MII VDDIOP0

PA9 MCI0_DA7 ERX3 Ethernet MII VDDIOP0

PA10 ETX0 Ethernet RMII Transmit data 0 VDDIOP0

PA11 ETX1 Ethernet RMII Transmit data 1 VDDIOP0

PA12 ERX0 Ethernet RMII Receive data 0 VDDIOP0

PA13 ERX1 Ethernet RMII Receive data 1 VDDIOP0

PA14 ETXEN Ethernet RMII Transmit enable VDDIOP0

PA15 ERXDV Ethernet RMII Receive data valid VDDIOP0

PA16 ERXER Ethernet RMII Receive Error VDDIOP0

PA17 ETXCK Ethernet RMII Transmit Clock VDDIOP0

PA18 EMDC Ethernet RMII Manag.Data Clock VDDIOP0

PA19 EMDIO Ethernet RMII Manag.Data In/Out VDDIOP0

PA20 TWD0 Two Wire Interface Data VDDIOP0

PA21 TWCK0 Two Wire Interface Clock VDDIOP0

PA22 MCI1_CDA SCK3 MMCI1 Command VDDIOP0

PA23 MCI1_DA0 RTS3 MMCI1 Data0 VDDIOP0

PA24 MCI1_DA1 CTS3 MMCI1 Data1 VDDIOP0

PA25 MCI1_DA2 PWM3 MMCI1 Data2 VDDIOP0

PA26 MCI1_DA3 TIOB2 MMCI1 Data3 VDDIOP0

PA27 MCI1_DA4 ETXER R.Select MMCI1 Data4 Ethernet MII VDDIOP0

PA28 MCI1_DA5 ERXCK R.Select MMCI1 Data5 Ethernet MII VDDIOP0

PA29 MCI1_DA6 ECRS R.Select MMCI1 Data6 Ethernet MII VDDIOP0

PA30 MCI1_DA7 ECOL R.Select MMCI1 Data7 Ethernet MII VDDIOP0

PA31 MCI1_CK PCK0 MMCI1_clock VDDIOP0

5-4 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Configuration

5.5.3 Multiplexing on PIO Controller B (PIOB)

Table 5-5. PIO Multiplexing Port B

I/O Peripheral A Peripheral B Function and Comments Power

PB0 SPI0_MISO SPI Slave Out Serial DataFlash VDDIOP0

PB1 SPI0_MOSI SPI Slave In Serial DataFlash VDDIOP0

PB2 SPI0_SPCK SPI Serial Clock Serial DataFlash VDDIOP0

PB3 SPI0_NPCS0 SPI Chip Select Serial DataFlash VDDIOP0

PB4 TXD1 USART1 Transmit Data VDDIOP0

PB5 RXD1 USART1 Receive Data VDDIOP0

PB6 TXD2 User Push Button Right click VDDIOP0

PB7 RXD2 User Push Button Left click VDDIOP0

PB8 TXD3 ISI_D8 Image Sensor Data 8 VDDIOP2

PB9 RXD3 ISI_D9 Image Sensor Data 9 VDDIOP2

PB10 TWD1 ISI_D10 Image Sensor Data 10 VDDIOP2

PB11 TWCK1 ISI_D11 Image Sensor Data 11 VDDIOP2

PB12 DRXD DBGU Receive Data VDDIOP0

PB13 DTXD DBGU Transmit Data VDDIOP0

PB14 SPI1_MISO Joystick Left VDDIOP0

PB15 SPI1_MOSI CTS0 Joystick Right VDDIOP0

PB16 SPI1_SPCK SCK0 Joystick Up VDDIOP0

PB17 SPI1_NPCS0 RTS0 Joystick Down VDDIOP0

PB18 RXD0 SPI0_NPCS1 Joystick Push VDDIOP0

PB19 TXD0 SPI0_NPCS2 UsbVbus VDDIOP0

PB20 ISI_D0 Image Sensor Data 0 VDDIOP2

PB21 ISI_D1 Image Sensor Data 1 VDDIOP2

PB22 ISI_D2 Image Sensor Data 2 VDDIOP2

PB23 ISI_D3 Image Sensor Data 3 VDDIOP2

PB24 ISI_D4 Image Sensor Data 4 VDDIOP2

PB25 ISI_D5 Image Sensor Data 5 VDDIOP2

PB26 ISI_D6 Image Sensor Data 6 VDDIOP2

PB27 ISI_D7 Image Sensor Data 7 VDDIOP2

PB28 ISI_PCK Image Sensor Data Clock VDDIOP2

PB29 ISI_VSYNC Image Sensor Vertical Synchro VDDIOP2

PB30 ISI_HSYNC Image Sensor Horizontal Synchro VDDIOP2

PB31 ISI_MCK PCK1 Image Sensor Reference Clock VDDIOP2

AT91SAM9M10-G45-EK User Guide 5-5

6495B–ATARM–21-Apr-10

Configuration

5.5.4 Multiplexing on PIO Controller C (PIOC)

Table 5-6. PIO Multiplexing Port C

I/O Peripheral A Peripheral B Function and Comments Power

PC0 DQM2 VDDIOM1

PC1 DQM3 VDDIOM1

PC2 A19 Add19 NAND Flash VDDIOM1

PC3 A20 Add20 NAND Flash VDDIOM1

PC4 A21/NANDALE ALE NAND Flash VDDIOM1

PC5 A22/NANDCLE CLE NAND Flash VDDIOM1

PC6 A23 VDDIOM1

PC7 A24 VDDIOM1

PC8 CFCE1 Ready/Busy NAND Flash VDDIOM1

PC9 CFCE2 RTS2 VDDIOM1

PC10 NCS4/CFCS0 TCLK2 VDDIOM1

PC11 NCS5/CFCS1 CTS2 VDDIOM1

PC12 A25/CFRNW VDDIOM1

PC13 NCS2 VDDIOM1

PC14 NCS3/NANDCS Chip select NAND Flash VDDIOM1

PC15 NWAIT VDDIOM1

PC16 D16 VDDIOM1

PC17 D17 VDDIOM1

PC18 D18 VDDIOM1

PC19 D19 VDDIOM1

PC20 D20 VDDIOM1

PC21 D21 VDDIOM1

PC22 D22 VDDIOM1

PC23 D23 VDDIOM1

PC24 D24 VDDIOM1

PC25 D25 VDDIOM1

PC26 D26 VDDIOM1

PC27 D27 VDDIOM1

PC28 D28 VDDIOM1

PC29 D29 VDDIOM1

PC30 D30 VDDIOM1

PC31 D31 VDDIOM1

5-6 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Configuration

5.5.5 Multiplexing on PIO Controller D (PIOD)

Table 5-7. PIO Multiplexing Port D

I/O Peripheral A Peripheral B Function and Comments Power

PD0 TK0 PWM3 Command LED2 VDDIOP0

PD1 TF0 Output ENA USB Host VDDIOP0

PD2 TD0 Input FLGA USB Host VDDIOP0

PD3 RD0 Output ENB USB Host VDDIOP0

PD4 RK0 Input FLGB USB Host VDDIOP0

PD5 RF0 Int. Ethernet 10/100 MDINTR VDDIOP0

PD6 AC97RX AC97 Receive Signal VDDIOP0

PD7 AC97TX TIOA5 AC97 Transmit Signal VDDIOP0

PD8 AC97FS TIOB5 AC97 Frame Sync Signal VDDIOP0

PD9 AC97CK TCLK5 AC97 Clock Signal VDDIOP0

PD10 TD1 Card Detect MMCI0 MCI0_CD VDDIOP0

PD11 RD1 Card Detect MMCI1 MCI1_CD VDDIOP0

PD12 TK1 PCK0 CTRL1 Image Sensor Interface VDDIOP0

PD13 RK1 CTRL2 Image Sensor Interface VDDIOP0

PD14 TF1 GPIO1 Large LCD (connector) VDDIOP0

PD15 RF1 GPIO2 Large LCD (connector) VDDIOP0

PD16 RTS1 USART1 Request to Send VDDIOP0

PD17 CTS1 USART1 Clear To Send VDDIOP0

PD18 SPI1_NPCS2 IRQ VDDIOP0

PD19 SPI1_NPCS3 FIQ VDDIOP0

PD20 TIOA0 TSAD0 Touch screen X_Right VDDANA

PD21 TIOA1 TSAD1 Touch screen X_Left VDDANA

PD22 TIOA2 TSAD2 Touch screen Y_Up VDDANA

PD23 TCLK0 TSAD3 Touch screen Y_Down VDDANA

PD24 SPI0_NPCS1 PWM0 GPAD4 General purpose A/D4 VDDANA

PD25 SPI0_NPCS2 PWM1 GPAD5 General purpose A/D5 VDDANA

PD26 PCK0 PWM2 GPAD6 General purpose A/D6 VDDIOP0

PD27 PCK1 SPI0_NPCS3 GPAD7 General purpose A/D7 VDDIOP0

PD28 TSADTRG SPI1_NPCS1 USB Plug-ID IDUSB VDDIOP0

PD29 TCLK1 SCK1 MCI1_WP VDDIOP0

PD30 TIOB0 SCK2 Command Power Led VDDIOP0

PD31 TIOB1 PWM1 Command LED1 VDDIOP0

AT91SAM9M10-G45-EK User Guide 5-7

6495B–ATARM–21-Apr-10

Configuration

5.5.6 Multiplexing on PIO Controller E (PIOE)

Table 5-8. PIO Multiplexing Port E

I/O Peripheral A Peripheral B Function and Comments Power

PE0 LCDPWR PCK0 LCD Panel Pow.Enab.Ctrl VDDIOP1

PE1 LCDMOD LCD Modulation Signal VDDIOP1

PE2 LCDCC LCD Contrast Control VDDIOP1

PE3 LCDVSYNC LCD Vertical Synch. VDDIOP1

PE4 LCDHSYNC LCD Horizontal Synch. VDDIOP1

PE5 LCDDOTCK LCD Dot Clock VDDIOP1

PE6 LCDDEN LCD Data Enable VDDIOP1

PE7 LCDD0 LCDD2 LCD-Red0 VDDIOP1

PE8 LCDD1 LCDD3 LCD-Red1 VDDIOP1

PE9 LCDD2 LCDD4 LCD-Red2 VDDIOP1

PE10 LCDD3 LCDD5 LCD-Red3 VDDIOP1

PE11 LCDD4 LCDD6 LCD-Red4 VDDIOP1

PE12 LCDD5 LCDD7 LCD-Red5 VDDIOP1

PE13 LCDD6 LCDD10 LCD-Red6 VDDIOP1

PE14 LCDD7 LCDD11 LCD-Red7 VDDIOP1

PE15 LCDD8 LCDD12 LCD-Green0 VDDIOP1

PE16 LCDD9 LCDD13 LCD-Green1 VDDIOP1

PE17 LCDD10 LCDD14 LCD-Green2 VDDIOP1

PE18 LCDD11 LCDD15 LCD-Green3 VDDIOP1

PE19 LCDD12 LCDD18 LCD-Green4 VDDIOP1

PE20 LCDD13 LCDD19 LCD-Green5 VDDIOP1

PE21 LCDD14 LCDD20 LCD-Green6 VDDIOP1

PE22 LCDD15 LCDD21 LCD-Green7 VDDIOP1

PE23 LCDD16 LCDD22 LCD-Blue0 VDDIOP1

PE24 LCDD17 LCDD23 LCD-Blue1 VDDIOP1

PE25 LCDD18 LCD-Blue2 VDDIOP1

PE26 LCDD19 LCD-Blue3 VDDIOP1

PE27 LCDD20 LCD-Blue4 VDDIOP1

PE28 LCDD21 LCD-Blue5 VDDIOP1

PE29 LCDD22 LCD-Blue6 VDDIOP1

PE30 LCDD23 LCD-Blue7 VDDIOP1

PE31 PWM2 PCK1 AC97 External Clock VDDIOP1

5-8 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

6.1 Power Supply

The SAM9M10-G45-EK evaluation board can be powered from a DC 5V power supply via the external power supply jack (J2) shown in

Figure 6-1. Power Supply Connector J2

Table 6-1. Power Supply Connector J2 Signal Description

Section 6

Connectors

Figure 6-1. The positive pole must be on J2 center pin.

Pin Mnemonic Signal description

1 Center +5 VCC

2Gnd

6.2 RS232 Connector with RTS/CTS Handshake Support

Connector J11 is the COM1 connector.

Figure 6-2. RS232 COM1 Connector J11

AT91SAM9M10-G45-EK User Guide 6-1

6495B–ATARM–21-Apr-10

Connectors

6.3 DBGU

Table 6-2. Serial COM1 Connector J11 Signal Descriptions

Pin Mnemonic Signal description

1, 4, 6, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5 GND GROUND

7 RTS READY TO SEND Active-positive RS232 input signal

8 CTS CLEAR TO SEND Active-positive RS232 output signal

Connector J10 is the DBGU connector.

Figure 6-3. RS232 DBGU Connector J10

Table 6-3. RS232 DBGU Connector J10 Signal Descriptions

Pin Mnemonic Signal description

1, 4, 6, 7, 8, 9 NC NO CONNECTION

2 TXD TRANSMITTED DATA RS232 serial data output signal

3 RXD RECEIVED DATA RS232 serial data input signal

5 GND GROUND

6-2 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

6.4 Ethernet

Connector J15 is the RJ-45 Ethernet Connector.

Figure 6-4. Ethernet RJ45 Connector J15

Table 6-4. Ethernet RJ45 Connector J15 Signal Descriptions

Connectors

Pin Mnemonic Pin Mnemonic

1 TxData+ DIFFERENTIAL OUTPUT PLUS 2 Txdata- DIFFERENTIAL OUTPUT MINUS

3 RxData+ DIFFERENTIAL INPUT PLUS 4 Shield

5 Shield 6 RxData- DIFFERENTIAL INPUT MINUS

7Shield 8Shield

6.5 USB Host

Connector J12 is the USB Host connector.

Figure 6-5. USB Host type A connector J12

Table 6-5. USB Host Type A Connector J12 Signal Descriptions

Pin Mnemonic Signal description

1 Vbus 5v power

2 DM Data minus

3 DP Data plus

4 Gnd Ground

5 Shield Shield

AT91SAM9M10-G45-EK User Guide 6-3

6495B–ATARM–21-Apr-10

Connectors

6.6 USB Host/Device

Connector J14 is the USB Host/Device connector.

Figure 6-6. USB Host/Device Micro AB connector J14

Table 6-6. USB Host/Device MicroAB Connector J14 Signal Descriptions

Pin Mnemonic Signal description

1 Vbus 5v power

2 DM Data minus

3 DP Data plus

4 ID On the Go Identification

5 Gnd Ground

6.7 JTAG Debugging Connector

Connector J13 is the JTAG/ICE connector.

A SAM-ICE connector is a 20-way Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that mates with IDC sockets mounted on a ribbon cable.

Figure 6-7. JTAG/ICE Connector J13

6-4 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Table 6-7. JTAG/ICE Connector J13 Signal Descriptions

Pin Mnemonic Description

This is the target reference voltage. It is used to check if the target has power, to create the logic-level reference for the input

1 VTref. 3.3V power

2 Vsupply. 3.3V power

3

nTRST TARGET RESET - Active-low output signal that resets the target

4 GND Common ground

5

TDI TEST DATA INPUT - Serial data output line, sampled on the rising edge of the TCK signal.

6 GND Common ground

comparators, and to control the output logic levels to the target. It is normally fed from VDD on the target board and must not have a series resistor.

This pin is not connected in SAM-ICE. It is reserved for compatibility with other equipment. Connect to VDD or leave open in target system.

JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port. Typically connected to nTRST on the target CPU. This pin is normally pulled HIGH on the target to avoid unintentional resets when there is no connection.

JTAG data input of target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TDI on target CPU.

Connectors

JTAG mode set input of target CPU. This pin should be pulled up on

7 TMS TEST MODE SELECT

the target. Typically connected to TMS on target CPU. Output signal that sequences the target's JTAG state machine, sampled on the rising edge of the TCK signal.

8 GND Common ground

TCK TEST CLOCK - Output timing signal, for

9

synchronizing test logic and control register access.

JTAG clock signal to target CPU. It is recommended that this pin is pulled to a defined state on the target board. Typically connected to TCK on target CPU.

10 GND Common ground

Some targets must synchronize the JTAG inputs to internal clocks. To assist in meeting this requirement, a returned and retimed TCK can

11

RTCK - Input Return test clock signal from the target.

be used to dynamically control the TCK rate. SAM-ICE supports adaptive clocking which waits for TCK changes to be echoed correctly before making further changes. Connect to RTCK if available, otherwise to GND

12 GND Common ground

13

TDO JTAG TEST DATA OUTPUT - Serial data input from the target.

JTAG data output from target CPU. Typically connected to TDO on target CPU.

14 GND Common ground

15 nSRST RESET Active-low reset signal. Target CPU reset signal

16 GND Common ground

17 RFU This pin is not connected in SAM-ICE.

18 GND Common ground

19 RFU This pin is not connected in SAM-ICE

20 GND Common ground

AT91SAM9M10-G45-EK User Guide 6-5

6495B–ATARM–21-Apr-10

Connectors

6.8 SD/MMC- MCI0

Connector J6 is the SD/MMC connector.

Figure 6-8. SD/MMC0 Connector J6

Table 6-8. SD/MMC0 Connector J6 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1RSV/DAT32 CDA

3 GND 4 VCC

5CLK6GND

7 D AT0 8 D AT1

9 DAT2 10 Card Detect

11 GND 12

6-6 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

6.9 SD/MMC- MCI1

Connector J5 is the SD/MMC connector.

Figure 6-9. SD/MMC1 Connector J5

Connectors

Table 6-9. SD/MMC1 Connector J5 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1RSV/DAT32 CMD

3 GND 4 VCC

5CLK6

7DAT08DAT1

9 DAT210DAT3

11 DAT4 12 DAT5

13 DAT6 14 DAT7

AT91SAM9M10-G45-EK User Guide 6-7

6495B–ATARM–21-Apr-10

Connectors

6.10 AC97

 Connector J7 is the Headphone connector.

 Connector J8 is the Line In connector.

 Connector J9 is the Microphone Input.

 Connector JP15 is the Speaker Output connector

Figure 6-10. Audio Connector J7, J8, J9

Table 6-10. J7, J8, J9 Signal Description

Pin Mnemonic

1Signal

2Signal

3Gnd

Table 6-11. Speaker JP15 Signal Descriptions

Pin Mnemonic

1 Speaker bridge output A

2 Speaker bridge output B

6-8 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

6.11 Image Sensor - ISI

Connector J17 is the ISI connector.

Figure 6-11. ISI Connector J17

Table 6-12. ISI Connector J17 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 VCC 3v3 2 Gnd

Connectors

3 VCC 3v3 4 Gnd

5Ctrl16Ctrl2

7SCL 8SDA

9Gnd10ISI_MCK

11 Gnd 12 ISI_VSYNC

13 Gnd 14 ISI_HSYNC

15 Gnd 16 ISI_PCK

17 Gnd 18 ISI_Data0

19 ISI_Data1 20 ISI_Data2

21 ISI_Data3 22 ISI_Data4

23 ISI_Data5 24 ISI_Data6

25 ISI_Data7 26 ISI_Data8

27 ISI_Data9 28 ISI_Data10

29 ISI_Data11 30 Gnd

AT91SAM9M10-G45-EK User Guide 6-9

6495B–ATARM–21-Apr-10

Connectors

6.12 Video

Connector J20 is the Video connector

Figure 6-12. Video Connector J20

Table 6-13. Video Connector J20 Signal Description

Pin Mnemonic Signal description

1 Center Composite video signal output

6.13 Display Devices

6.13.1 TFT LCD

Connector J24 is the TFT-LCD connector.

Figure 6-13. TFT LCD Connector J24

Table 6-14. TFT LCD Connector J24 Signal Descriptions

Pin Mnemonic Pin Mnemonic

1 VLED- 2 VLED+

3 GND 4 VDD 3V3

5R06 R1

7R28 R3

9R410 R5

6-10 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

Table 6-14. TFT LCD Connector J24 Signal Descriptions

Pin Mnemonic Pin Mnemonic

11 R6 12 R7

13 G0 14 G1

15 G2 16 G3

17 G4 18 G5

19 G6 20 G7

21 B0 14 B1

23 B2 16 B3

25 B4 18 B5

27 B6 20 B7

29 GND 30 DCLK

31 DISPON 32 HSYNC

33 VSYNC 34 LCDEN

35 NO CONNECT 36 GND

37 X2 38 Y1

39 X1 40 Y2

Connectors

6.14 LCD Extension

Connectors J23 and J18 are for an optional LCD extension (not populated).

Table 6-15. Connector J23 Signal Description for an LCD Extension

Pin Mnemonic Pin Mnemonic

1 PE8 RED Data Signal 2 PE7 RED Data Signal (LSB)

3 PE10 RED Data Signal 4 PE9 RED Data Signal

5 PE12 RED Data Signal 6 PE11 RED Data Signal

7 PE14 RED Data Signal (MSB) 8 PE13 RED Data Signal

9 PE16 GREEN Data Signal 10 PE15 GREEN Data Signal (LSB

11 PE18 GREEN Data Signal 12 PE17 GREEN Data Signal

13 PE20 GREEN Data Signal 14 PE19 GREEN Data Signal

15 PE22 GREEN Data Signal (MSB) 16 PE21 GREEN Data Signal

17 PE24 BLUE Data Signal 18 PE23 BLUE Data Signal (LSB)

19 PE26 BLUE Data Signal 20 PE25 BLUE Data Signal

21 PE28 BLUE Data Signal 22 PE27 BLUE Data Signal

23 PE30 BLUE Data Signal (MSB) 24 PE29 BLUE Data Signal

25 PE4 LCDHSYNC 26 PE3 LCDVSYNC

27 PE5 LCDDOTCK 28 GND (0V)

29 GND (0V) 30 NC

AT91SAM9M10-G45-EK User Guide 6-11

6495B–ATARM–21-Apr-10

Connectors

Table 6-15. Connector J23 Signal Description for an LCD Extension

Pin Mnemonic Pin Mnemonic

31 PE6 LCDDEN 32 PE2 LCDCC

33 PE0 DISPON 34 PE1 LCDMOD

35 PD14 GPIO1 36 PD15 GPIO2

37 GND (0V) 38 GND (0V)

39 VCC +3V3 power source 40 NC

Table 6-16. Connector J18 Signal Description for an LCD Extension

Pin Mnemonic Pin Mnemonic

1 XM AD1XM 2 XP AD0XP

3 YM AD3YM 4 YP AD2YP

5 GND (0V) 6 GND (0V)

7 PD25 PD25 8 PD24 PD24

9 PD27 PD27 10 PD26 PD26

11 PD19 PD19 12 PD18 PD18

13 GND (0V) 14 GND (0V)

15 GND (0V) 16 +5V

17 GND (0V) 18 GND (0V)

19 VCC +3V3 power source 20 VCC +3V3 power source

6-12 AT91SAM9M10-G45-EK User Guide

6495B–ATARM–21-Apr-10

7.1 Schematics

This section contains the following schematics:

 Top Level view, block architecture of the design

 Power Supply

 SAM Processor

 Bus impedance adaptor

 Main memory

 EBI memory

 MCI & TWI

 Audio AC97

 Serial interfaces

 Ethernet

 LCD

 Video interfaces and LCD extension

Section 7

Schematics

AT91SAM9M10-G45-EK User Guide 7-1

6495B–ATARM–21-Apr-10

8

7

6

5

4

3

2

1

5 V

POWER SUPPLY

POWER

USER

D D

INTERFACE

PIO

3V3

1V8

1V

EBI0 DDR2 INTERFACE

EBI0

DDR2

128MB

Sheet 2

DBGU

RS232

COM1

HOST

USB

HOST DEVICE

ICE INTERFACE

C C

Sheet 9

10/100 FAST ETHERNET

PIO

PIO A,...E

ATMEL ARM9 Processor SAM9M10 (LFBGA324)

EBI1 DATA INTERFACE

EBI1 ADDRESS INTERFACE

EBI1 BUS INTERFACE

RES.ARRAYS EBI0_EBI1 ADAPTER

Sheet 4

EBI1 DDR2 INTERFACE

EBI1 FLASH INTERFACE

EBI1 NANDFLASH INTERFACE

Sheet 5

EBI1

Sheet 6

DDR2

128MB

FLASHNAND

FLASH

RJ 45 HE 10HE 14

Sheet 10

CARD READER

SERIAL EEPROM

SERIAL DATA FLASH

Sheet 7

CARD READER

MMC SD

SDIO

MMC SD

SDIO

PIO CONNECTOR

PIO A,...E

LCD INTERFACE

4.3" 480x272 TFT

TOUCH SCREEN

B B

HE 14

RCA

ISI

CAMERA INTERFACE

TV INTERFACE

PIO

Sheet 3

MICOUT IN

AUDIO

Sheet 8

Sheet 11 12

NOTE

PIOA USAGE PA0

MCI0_CK

PA1

MCI0_CDA

PA2

MCI0_DA0 PA3 PA4 PA5 PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15

MCI0_DA1

(MCI0_DA2)

(MCI0_DA3)

TXD2

TXD3

RXD2

RXD3

TXD0

TXD1

RXD0

RXD1

TX_EN

RX_DV

8

A A

PIOA USAGE PA16

RX_ER

PA17

TX_CLK

PA18

MDC

PA19

MDIO

PA20

TWDO

PA21

TWCK0

PA22

MCI1_CDA

PA23

MCI1_DA0

PA24

MCI1_DA1

PA25

MCI1_DA2

PA26

MCI1_DA3

PA27

MCI1_DA4/TX_ER

PA28

MCI1_DA5/RX_CLK

PA29

MCI1_DA6/CRS

PA30

MCI1_DA7/COL

PA31

MCI1_CK

PIOB USAGE PB0

SPI0_MISO

PB1

SPI0_MOSI

PB2

SPI0_SPCK

PB3

SPI0_NPCS0

PB4

TXD1

PB5

RXD1

PB6

BP5_LEFT

PB7

BP4_RIGHT

PB8

ISI_D8

PB9

ISI_D9

PB10

ISI_D10

PB11

ISI_D11

PB12

DRXD

PB13

DTXD

PB14

BP3_LEFT

PB15

BP3_RIGHT

7

PIOB USAGE PB16

BP3_UP

PB17

BP3_DOWN

PB18

BP3_PUSH

PB19

VBUS

PB20

ISI_D0

PB21

ISI_D1

PB22

ISI_D2

PB23

ISI_D3

PB24

ISI_D4

PB25

ISI_D5

PB26

ISI_D6

PB27

ISI_D7

PB28

ISI_PCK

PB29

ISI_VSYNC

PB30

ISI_HSYNC

PB31

ISI_MCK

PIOC USAGE

NOT USED

PC0

NOT USED

PC1 PC2

A19

PC3

A20

PC4

NANDALE/A21

PC5

NANDCLE NOT USED

PC6

NOT USED

PC7 PC8

RDY/BSY NOT USED

PC9

NOT USED

PC10

NOT USED

PC11

NOT USED

PC12

NOT USED

PC13 PC14

NCS3 NOT USED

PC15

6

PIO MUXING

PIOC USAGE

NOT USED

PC16

NOT USED

PC17

NOT USED

PC18

NOT USED

PC19

NOT USED

PC20

NOT USED

PC21

NOT USED

PC22

NOT USED

PC23

NOT USED

PC24

NOT USED

PC25

NOT USED

PC26

NOT USED

PC27

NOT USED

PC28

NOT USED

PC29

NOT USED

PC30

NOT USED

PC31

5

PIOD USAGE PD0

USER LED D6

PD1

ENA

PD2

FLGA

PD3

ENB

PD4

FLGB

PD5

MDINTR

PD6

AC97RX

PD7

AC97TX

PD8

AC97FS

PD9

AC97CK

PD10

MCI0_CD

PD11

(MCI1_CD)

PD12

CTRL1

PD13

CTRL2

PD14

GPIO1

PD15

GPIO2

PIOD USAGE PD16

RTS1

PD17

CTS1 J18 12

PD18

J18 11

PD19 PD20

AD0Xp

PD21

AD1Xm

PD22

AD2Yp

PD23

AD3Ym J18_8

PD24

J18_7

PD25

J18_10

PD26

J18_9

PD27 PD28

IDUSB

PD29

(MCI1_WP)

PD30

POWER_LED

PD31

USER LED D7

4

PIOE USAGE PE0

LCDPWR

PE1

LCDMOD

PE2

LCDCC

PE3

LCDVSYNC

PE4

LCDHSYNC

PE5

LCDDOTCK

PE6

LCDDEN

PE7

R0

PE8

R1

PE9

R2

PE10

R3

PE11

R4

PE12

R5

PE13

R6

PE14

R7

PE15

G0

PIOE USAGE PE16

G1

PE17

G2

PE18

G3

PE19

G4

PE20

G5

PE21

G6

PE22

G7

PE23

B0

PE24

B1

PE25

B2

PE26

B3

PE27

B4

PE28

B5

PE29

B6

PE30

B7

PE31

EXT_CLK

3

"DNP" means the component is not populated by default

08-apr-10PPA2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

AT91SAM9M10-G 45-EK

TOP LEVE L

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

SCALE

MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

VER.

REV. SHEET

A2

11-FEB-10Derek PP

1

12

8

REGULATED

FORCE POWER ON

5V ONLY

J2

1 3 2

DC POWER JACK

Q1

Si1563EDH

12

JP4

SIP2

SHDN{3}

5V

R9 100kR9100k

C17

1 32

15p

5V

C4

+

33u

456

R16

R16 10k

10k

D D

C C

CR15VCR1 5V

PWR_EN

R17

R17 10k

10k

7

3V3

R3 100kR3100k

5V

C23

C23 10u

10u

MN2

MN2 RT9018A

RT9018A

1 2 3

C9

C101uC10 1u

10uC910u

1V8

R11

R11 100k

100k

MN4

MN4 RT9018A

RT9018A

1 2 3

C241uC24 1u

PGOOD

GND

EN

ADJ

VIN

VOUT

VDD4NC

EP

9

PGOOD

GND

EN

ADJ

VIN

VOUT

VDD4NC

EP

9

6

VOUT =

0.8V x (Rtop + Rbottom)/Rbottom

C3 10nC3 10n

R4 47kR4 47k R6

8 7 6 5

R7 15kR715k

VOUT =

0.8V x (Rtop + Rbottom)/Rbottom

C16 10nC16 10n

R15 15kR15 15k

8 7 6 5

R18

R18 12k

12k

5

1V

3V3

R199

3V3

R199

100k

C131uC13 1u

C251uC25

1u

1V_VDDUTMIC

R13

100k

3V3

C111uC11

C12

1u

10u

1V8

C261uC26 1u

C27

C27 10u

10u

R2 100kR2100k

1 2 3 4

R10

R10 100k

100k

1 2 3 4

MN1

MN1 RT9186A

RT9186A

VIN VIN PGOOD EN

MN3

MN3 RT9186A

RT9186A

VIN VIN PGOOD EN

4

8

VOUT

7

VOUT

6

ADJ

5

GND

EP

12kR612k

9

R8 47kR847k

VOUT =

0.8V x (Rtop + Rbottom)/Rbottom

8

VOUT

7

VOUT

6

ADJ

5

GND

EP

R14

R14 12k

12k

9

R19

R19 47k

47k

VOUT =

0.8V x (Rtop + Rbottom)/Rbottom

3

1V

C5 10nC510n

C71uC7

1u

C6 10uC610u

1V_VDDUTMIC

C19

10n

C221uC22

C21

1u

10u

2

3V3

L3 10uHL3 10uH

L4 10uHL4 10uH

L1 10uHL1 10uH

L2 10uHL2 10uH

JP1JP1

1

JP2JP2

2

1

JP3JP3

2

1

2

C15

2.2u

R121RR12 1R

C20

4.7u

R201RR20 1R

C29

4.7u

C1 100nC1100n

C8 100nC8100n

1

VDDUTMII {3}

VDDANA {3}

VDDOSC {3}

R11RR1 1R

C2

4.7uC24.7u

C14

4.7u

R51RR5 1R

J1-1J1-1

1 2

3

J1-2J1-2

3 4

J1-4J1-4

7 8

C18

C18 100n

100n

C28

C28 100n

100n

VDDIOP0 {3}

VDDIOP1 {3}

VDDIOP2 {3,12}

VDDISI {3,12}

VDDUTMIC {3}

VDDPLLUTMI {3}

VDDPLLA {3}

B B

USER INTERFACE

3V3

R25

470R

12

D3

R26

RedD3Red

100k

IRLML2402

3

Q2

1

PD30 {3}

A A

2

POWER LED

8

3V3

GreenD1Green

D1

1 2

D2

1 2

GreenD2Green

PB15 PB16

PB14 PB18

PB17

C32

10n

PB[14..18]{3}

7

C33

10n

R21 470RR21 470R

R22 470RR22 470R

LEFT

C34

10n

1 2 3

R28

R28 100R

100R

BP3

JoyStick

6

PD0 {3}

PD31 {3}

BP1BP1

NRST

BP2BP2

WAKE UP

4

UP

5

RIGHT

6

DOWNPUSH

C35

10n

C36

10n

RIGHT CLICK

LEFT CLICK

5

BP4BP4

R27

C31

100R

10n

BP5BP5

C37

R29

10n

100R

VDDBU

R23

R23 100k

100k

3V3

R241kR24 1k

NRST {3,7,8,9,10,12}

WAKE UP {3}

PB7 {3}

ADHESIVE FEET

Z2

BumponZ2Bumpon

Z4

BumponZ4Bumpon

Z5

BumponZ5Bumpon

BumponZ3Bumpon

BumponZ6Bumpon

Z3

Z6

GND TEST POINT

PB6 {3}

4

TP1TP1

TP3TP3

TP2TP2

3

TP4TP4

1V

1V8

J3J3

AT91SAM9M10-G 45-EK

POWE R SUPPLY

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

J1-3J1-3

5 6

JP5JP5

1

3

JP6JP6

2

1

3

2

1

C30

C30 100n

100n

A

REV DATE

MODIF.

1/1

DES.

REV DATE

SCALE

JP7JP7

2

08-apr-10PPA2

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

VDDCORE {3}

VDDIOM0 {3}

VDDIOM1 {3}

3

1

3V3

VDDBU {3}

11-FEB-10Derek PP

VER.

REV. SHEET

2

A2

12

8

PA[0..31]{7,10,12}

D D

EBI0_D[0..15]{4}

C C

EBI0_A[0..13]{4}

B B

EBI0_BA0{4} EBI0_BA1{4}

EBI0_CKE{4} EBI0_CLK{4} EBI0_NCLK{4}

EBI0_CS{4}

EBI0_CAS{4} EBI0_RAS{4}

EBI0_WE{4}

DDR_VREF{5,6}

EBI0_DQM0{4} EBI0_DQM1{4}

EBI0_DQS0{4} EBI0_DQS1{4}

A A

PA0 PA1 PA2 PA3 PA4

PA6 PA7 PA8 PA9 PA10 PA11 PA12 PA13 PA14 PA15 PA16 PA17 PA18 PA19 PA20 PA21 PA22 PA23 PA24 PA25 PA26 PA27 PA28 PA29 PA30 PA31

EBI0_D0 EBI0_D1 EBI0_D2 EBI0_D3 EBI0_D4 EBI0_D5 EBI0_D6 EBI0_D7 EBI0_D8 EBI0_D9 EBI0_D10 EBI0_D11 EBI0_D12 EBI0_D13 EBI0_D14 EBI0_D15

EBI0_A0 EBI0_A1 EBI0_A2 EBI0_A3 EBI0_A4 EBI0_A5 EBI0_A6 EBI0_A7 EBI0_A8 EBI0_A9 EBI0_A10 EBI0_A11 EBI0_A12 EBI0_A13

L1

PA0/MCI0_C K/TCLK3

M1

PA1/MCI0_C DA/TIOA3

L5

PA2/MCI0_D A0/TIOB3

N1

PA3/MCI0_D A1/TCKL4

L6

PA4/MCI0_D A2/TIOA4

M2

PA5/MCI0_D A3/TIOB4

M3

PA6/MCI0_D A4/ETX2

M4

PA7/MCI0_D A5/ETX3

L7

PA8/MCI0_D A6/ERX2

N2

PA9/MCI0_D A7/ERX3

M5

PA10/ETX 0

P1

PA11/ETX 1

N3

PA12/ERX 0

P2

PA13/ERX 1

M6

PA14/ETX EN

N4

PA15/ERX DV

N5

PA16/ERX ER

N6

PA17/ETX CK

R1

PA18/EMD C

P3

PA19/EMD IO

R2

PA20/TW D0

P4

PA21/TW CK0

T1

PA22/MCI1_ CDA/SCK3

P5

PA23/MCI1_ DA0/RTS3

R3

PA24/MCI1_ DA1/CTS3

T2

PA25/MCI1_ DA2/PWM3

T3

PA26/MCI1_ DA3/TIOB2

U1

PA27/MCI1_ DA4/ETXER

U3

PA28/MCI1_ DA5/ERXCK

U2

PA29/MCI1_ DA6/ECRS

R4

PA30/MCI1_ DA7/ECOL

V1

PA31/MCI1_ CK/PCK0

R16

EBI0_DDR_ D0

R15

EBI0_DDR_ D1

T14

EBI0_DDR_ D2

P15

EBI0_DDR_ D3

P16

EBI0_DDR_ D4

P17

EBI0_DDR_ D5

R14

EBI0_DDR_ D6

P14

EBI0_DDR_ D7

N15

EBI0_DDR_ D8

N16

EBI0_DDR_ D9

P18

EBI0_DDR_ D10

N17

EBI0_DDR_ D11

N18

EBI0_DDR_ D12

N14

EBI0_DDR_ D13

M15

EBI0_DDR_ D14

M16

EBI0_DDR_ D15

M17

EBI0_DDR_ A0

L14

EBI0_DDR_ A1

M18

EBI0_DDR_ A2

L15

EBI0_DDR_ A3

L16

EBI0_DDR_ A4

L18

EBI0_DDR_ A5

L17

EBI0_DDR_ A6

K14

EBI0_DDR_ A7

K15

EBI0_DDR_ A8

K16

EBI0_DDR_ A9

K18

EBI0_DDR_ A10

K17

EBI0_DDR_ A11

J14

EBI0_DDR_ A12

J15

EBI0_DDR_ A13

G17

EBI0_DDR_ BA0

G16

EBI0_DDR_ BA1

J16

EBI0_DDR_ CKE

J18

EBI0_DDR_ CLK

H18

EBI0_DDR_ NCLK

H14

EBI0_DDR_ CS

H17

EBI0_DDR_ CAS

J17

EBI0_DDR_ RAS

H15

EBI0_DDR_ WE

A16

EBI0_DDR_ VREF

G14

EBI0_DDR_ DQM0

H16

EBI0_DDR_ DQM1

G18

EBI0_DDR_ DQS0

G15

EBI0_DDR_ DQS1

MN5GMN5G

MN5AMN5A

7

MN5BMN5B

PB0/SPI0_M ISO PB1/SPI0_M OSI

PB2/SPI0_S PCK

PB3/SPI0_N PCS0

PB8/TXD3 /ISI_D8

PB9/RXD3 /ISI_D9

PB10/TW D1/ISI_D10

PB11/TW CK1/ISI_D11

PB14/SPI1_ MISO PB15/SPI1_ MOSI/CTS0 PB16/SPI1_ SPCK/SCK0

PB17/SPI1_ NPCS0/RTS0 PB18/RXD 0/SPI0_NPCS1 PB19/TXD 0/SPI0_NPCS2

PB29/ISI_VSYNC

PB30/ISI_HSYNC

PB31/ISI_MCK/P CK1

MN5FMN5F

EBI1_NBS0 /A0

EBI1_NBS2 /NWR2/A1

EBI1_BA0/A 16 EBI1_BA1/A 17

EBI1_SDA1 0

EBI1_SDCK E

EBI1_NSDC K

EBI1_NCS1 /SDCS

EBI1_NRD/C FOE

EBI1_NW E/NWR0/CF WE

EBI1_NBS1 /NWR1/CFIOR

EBI1_NBS3 /NWR3/CFIOW

EBI1_NAND OE

EBI1_NAND WE

PB4/TXD1 PB5/RXD1 PB6/TXD2 PB7/RXD2

PB12/DRX D PB13/DTX D

PB20/ISI_D0 PB21/ISI_D1 PB22/ISI_D2 PB23/ISI_D3 PB24/ISI_D4 PB25/ISI_D5 PB26/ISI_D6 PB27/ISI_D7 PB28/ISI_D8

EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8

EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15

EBI1_A2

EBI1_A3

EBI1_A4

EBI1_A5

EBI1_A6

EBI1_A7

EBI1_A8

EBI1_A9

EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15

EBI1_A18

EBI1_DQM0 EBI1_DQM1 EBI1_DQS0 EBI1_DQS1

EBI1_RAS EBI1_CAS

EBI1_SDW E

EBI1_SDCK

EBI1_NCS0

6

T4 V2 V3 U4 R5 V4 T5 U5 T12 N11 U13 M11 P6 R6 M7 V5 T6 U6 N7 P7 P12 T15 R12 T16 N12 M12 U14 M13 N13 R13 T13 P13

A17 D15 C15 B16 B15 D14 C14 A15 B14 D13 C13 E13 B13 E12 D12 C12

F13 F14 F18 F15 E14 F17 F16 E17 E15 E16 D18 D17 C18 B18 A18 B17 C10 B10 C17

B11 D11 A11 E11

A12 C11 F12 B9 B12

A13 A14

A10 F10

F11 C9 D9 A9

D10 E10

PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB8

PB9 PB10 PB11 PB12 PB13 PB14 PB15 PB16 PB17 PB18 PB19 PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31

EBI1_D0 EBI1_D1 EBI1_D2 EBI1_D3 EBI1_D4 EBI1_D5 EBI1_D6 EBI1_D7 EBI1_D8 EBI1_D9 EBI1_D10 EBI1_D11 EBI1_D12 EBI1_D13 EBI1_D14 EBI1_D15

EBI1_A0 EBI1_A1 EBI1_A2 EBI1_A3 EBI1_A4 EBI1_A5 EBI1_A6 EBI1_A7 EBI1_A8 EBI1_A9 EBI1_A10 EBI1_A11 EBI1_A12 EBI1_A13 EBI1_A14 EBI1_A15 EBI1_A16 EBI1_A17 EBI1_A18

PB[0..31] {2,7,9,12}

PC[2..5]{4,6}

EBI1_A0

EBI1_DQM0 {4} EBI1_DQM1 {4} EBI1_DQS0 {4} EBI1_DQS1 {4}

EBI1_RAS {4} EBI1_CAS {4} EBI1_SDWE {4} EBI1_SDA10 {4} EBI1_SDCKE {4}

EBI1_SDCK {4} EBI1_NSDCK {4}

EBI1_NCS0 {6} EBI1_NCS1/SDCS {4}

EBI1_NRD/CFOE {6} EBI1_NWE/NWR0/CFWE {6}

EBI1_NANDOE {6} EBI1_NANDWE {6}

PC8{6}

PC14{6}

EBI1_D[0..15] {4}

EBI1_A[1..18] {4}

TP5

TP pad

5

A8

PC0/DQM2

E9

PC1/DQM3

B8

PC8

PC14

PC2PA5 PC3 PC4 PC5

SUP1

PC2/A19

C8

PC3/A20

F9

PC4/A21/N ANDALE

A7

PC5/A22/N ANDCLE

D8

PC6/A23

A6

PC7/A24

E8

PC8/CFCE 1

C7

PC9/CFCE 2/RTS2

B6

PC10/NCS 4/CFCS0/TCLK2

B7

PC11/NCS 5/CFCS1/CTS2

A5

PC12/A25 /CFRNW

D7

PC13/NCS 2

F8

PC14/NCS 3/NANDCS

C6

PC15/NW AIT

E7

PC16/D16

B5

PC17/D17

D6

PC18/D18

F7

PC19/D19

A4

PC20/D20

C5

PC21/D21

B4

PC22/D22

E6

PC23/D23

D5

PC24/D24

A3

PC25/D25

C4

PC26/D26

A1

PC27/D27

A2

PC28/D28

B2

PC29/D29

B3

PC30/D30

B1

PC31/D31

HDPA{9} HDMA{9}

HDPB{9} HDMB{9}

VDDOSC{2}

NTRST{9} TDI{9} TMS{9} TCK{9} RTCK{9} TDO{9}

NRST{2,7,8,9,10,12}

DNPSUP1

DNP

MN5CMN5C

C46 22pC46 22p

2 4

C50 22pC50 22p

C53 15pC53 15p

C57 15pC57 15p

VDDBU

NTRST

SHDN{2}

WAKE UP{2}

4

PD24/SPI0_ NPCS1/PWM0 PD25/SPI0_ NPCS2/PWM1

PD28/TSA DTRG/SPI1_NPCS1

R30 39RR30 39R R31 39RR31 39R

R33 39RR33 39R R32 39RR32 39R

C44

100n

Y1

12MHzY112MHz

1 3

Y2

32.768KHz

DNP

R34 0R

TDI TMS TCK RTCK TDO NRST

MN5DMN5D

PD0/TK0/P WM3

PD1/TF0

PD2/TD0 PD3/RD0 PD4/RK0

PD5/RF0

PD6/AC97 RX PD7/AC97 TX/TIOA5 PD8/AC97 FS/TIOB5

PD9/97CK /TCLK5

PD10/TD1 PD11/RD1

PD12/TK1 /PCK0

PD13/RK1 PD14/TF1

PD15/RF1 PD16/RTS 1 PD17/CTS 1

PD18/SPI1_ NPCS2/IRQ PD19/SPI0_ NPCS3/FIQ

PD20/TIOA0 PD21/TIOA1 PD22/TIOA2

PD23/TCL K0

PD26/PCK 0/PWM2

PD27/PCK 1/SPI0_NPCS3

PD29/TCL K1/SCK1

PD30/TIOB0 /SCK2

PD31/TIOB1 /PWM1

MN5HMN5H

T18

HFSDPA

R18

HFSDMA

T17

HHSDPA

R17

HHSDMA

V15

DFSDP/HF SDPB

V16

DFSDM/HF SDMB

U15

DHSDP/HH SDPB

U16

DHSDM/HH SDMB

U11

VDDOSC

U12

GNDOSC

V12

XIN

V11

XOUT

C1

XIN32

D1

XOUT32

E4

JTAGSEL

N10

NTRST

R10

TDI

P10

TMS

U10

TCK

R11

RTCK

V10

TDO

M10

NRST

F3

SHDN

C3

3V3

R39

4.7k

3

GNDCORE

GNDCOREH9GNDCOREJ9GNDIOM

TST

G9

R38

10k

PD[0..31] {2,7,8,9,10,11,12}

GNDCORE

GNDIOM

J10

J12

J13

K11

K12

C16

H12

H13

H10

R7

PD0

T7

PD1

L8

PD2

V6

PD3

M8

PD4

V7

PD5

N8

PD6

U7

PD7

P8

PD8

R8

PD9

U8

PD10

T8

PD11

V8

PD12

L9

PD13

U9

PD14

M9

PD15

N9

PD16

V9

PD17

R9

PD18

T9

PD19

D2

PD20

E1

PD21

F1

PD22

G2

PD23

F2

PD24

G1

PD25

H1

PD26

H2

PD27

P9

PD28

L10

PD29

T10

PD30

L11

PD31

WKUP

VBG

BMS

E5

T11

V18

R37

C66

10p

6.8k

PE[0..31]{8,11,12}

VDDPLLU TMI

VDDUTMIC

VDDUTMII

VDDCORE VDDCORE VDDCORE VDDCORE

TSADVRE F

GNDIOP

J11

VDDBU

GNDBU

GNDUTMI

VDDIOP0 VDDIOP0

VDDIOP1

VDDIOP2

VDDIOM0 VDDIOM0 VDDIOM0 VDDIOM0

VDDIOM1 VDDIOM1 VDDIOM1 VDDIOM1

VDDPLLA

VDDANA

GNDANA

2

G4

D4 D3

V13 U18

U17

V17

K9 K10

H3

V14

E18 G12 G13 H11

K13 L12 L13 M14

D16 F6 G10 G11

P11

E2

E3

C2

PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PE8 PE9 PE10 PE11 PE12 PE13 PE14 PE15 PE16 PE17 PE18 PE19 PE20 PE21 PE22 PE23 PE24 PE25 PE26 PE27 PE28 PE29 PE30 PE31

R360RR36 0R

C64

100n

C40

C40 100n

100n

PE0/LCDP WR/PCK0

F4

PE1/LCDM OD

G5

PE2/LCDC C

F5

PE3/LCDV SYNC

G7

PE4/LCDH SYNC

H5

PE5/LCDD OTCK

G3

PE6/LCDD EN

H6

PE7/LCDD 0/LCDD2

G6

PE8/LCDD 1/LCDD3

H7

PE9/LCDD 2/LCDD4

H8

PE10/LCD D3/LCDD5

G8

PE11/LCD D4/LCDD6

J5

PE12/LCD D5/LCDD7

H4

PE13/LCD D6/LCDD10

J3

PE14/LCD D7/LCDD11

J4

PE15/LCD D8/LCDD12

J2

PE16/LCD D9/LCDD13

J6

PE17/LCD D10/LCDD14

J7

PE18/LCD D11/LCDD15

J1

PE19/LCD D12/LCDD18

J8

PE20/LCD D13/LCDD19

K1

PE21/LCD D14/LCDD20

K4

PE22/LCD D15/LCDD21

K2

PE23/LCD D16/LCDD22

K5

PE24/LCD D17/LCDD23

K6

PE25/LCD D18

K3

PE26/LCD D19

K7

PE27/LCD D20

K8

PE28/LCD D21

L3

PE29/LCD D22

L2

PE30/LCD D23

L4

PE31/PW M2/PCK1

C38 100nC38 100n C39 100nC39 100n

100n

C41

C42 100nC42 100n C43

C43

100n

C45

100n

C47

C48 100nC48 100n C49 100nC49 100n

100n

C51

100n

C52

C54 100nC54 100n

100n

C55

100n

C56

C56 C58 100nC58 100n

100n

C59

100n

C60

100n

C61

C61 C62 100nC62 100n

C63 100nC63 100n

R350RR35

0R

C65

100n

1

MN5EMN5E

VDDBU {2}

VDDPLLUTMI {2}

VDDUTMIC {2}

VDDUTMII {2}

VDDIOP0 {2}

VDDIOP1 {2}

VDDIOP2 {2,12}

VDDCORE {2}

VDDIOM0 {2}

VDDIOM1 {2}

VDDPLLA {2}

VDDANA {2}

BOOT MODE SELECT

Opened

SG-BGA-CA89405MF

8

7

6

5

Closed NCS0=

4

Internal ROM BOOT=

12

JP8

SIP2

3

AT91SAM9M10-G 45-EK

AT91SAM 9M10 chip

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

MODIF.

SCALE

1/1

DES.

08-apr-10PPA2

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

3

A2

12

8

7

6

5

4

3

2

1

EBI Bus Impedance Adaptor

EBI1_D[0..15]{3}

EBI0_D[0..15]{3}

D D

EBI0

EBI0_A[0..13]{3}

C C

B B

EBI0_CKE{3}

EBI0_CLK{3}

EBI0_NCLK{3}

EBI0_BA0{3 }

EBI0_BA1{3 }

EBI0_W E{3 }

EBI0_CS{3}

EBI0_RAS{3}

EBI0_CAS{3}

A A

EBI0_DQM0{3}

EBI0_DQM1{3}

EBI0_D0

EBI0_D1

EBI0_D2

EBI0_D3

EBI0_D4

EBI0_D5

EBI0_D6

EBI0_D7

EBI0_D8

EBI0_D9

EBI0_D10

EBI0_D11

EBI0_D12

EBI0_D13

EBI0_D14

EBI0_D15

EBI0_A0

EBI0_A1

EBI0_A2

EBI0_A3

EBI0_A4

EBI0_A5

EBI0_A6

EBI0_A7

EBI0_A8

EBI0_A9

EBI0_A10

EBI0_A11

EBI0_A12

EBI0_A13

RR4BRR4B27

RR2DRR2D45

RR2BRR2B27

RR4ARR4A18

RR4CRR4C36

RR4DRR4D45

RR2ARR2A18

RR2CRR2C36

RR6BRR6B27

RR8DRR8D45

RR6DRR6D45

RR8BRR8B27

RR8ARR8A18

RR6CRR6C36

RR6ARR6A18

RR8CRR8C36

RR10ARR10A18

RR10BRR10B27

RR10CRR10C36

RR12CRR12C36

RR10DRR10D45

RR12BRR12B27

RR12ARR12A18

RR14DRR14D45

RR14CRR14C36

RR14BRR14B27

RR12DRR12D45

RR14ARR14A18

RR16BRR16B27

RR16ARR16A18

RR26CRR26C36

RR26DRR26D45

R40 27RR40 27 R

R42 27RR42 27 R

R44 27RR44 27 R

RR16DRR16D45

RR26ARR26A18

RR16CRR16C36

RR26BRR26B27

RR29CRR29C36

RR29DRR29D45

RR29ARR29A18

RR29BRR29B27

DDR_D0

DDR_D1

DDR_D2

DDR_D3

DDR_D4

DDR_D5

DDR_D6

DDR_D7

DDR_D8

DDR_D9

DDR_D10

DDR_D11

DDR_D12

DDR_D13

DDR_D14

DDR_D15

DDR_A0

DDR_A1

DDR_A2

DDR_A3

DDR_A4

DDR_A5

DDR_A6

DDR_A7

DDR_A8

DDR_A9

DDR_A10

DDR_A11

DDR_A12

DDR_A13

DDR_D[0..1 5] {5}

DDR_A[0..1 3] {5}

DDR_CKE {5}

DDR_CLK {5}

DDR_NCL K {5}

DDR_BA0 {5}

DDR_BA1 {5}

DDR_W E {5}

DDR_CS {5}

DDR_RAS {5}

DDR_CAS {5}

DDR_DQM 0 {5 }

DDR_DQM 1 {5 }

EBI1_D0

EBI1_D1

EBI1_D2

EBI1_D3

EBI1_D4

EBI1_D5

EBI1_D6

EBI1_D7

EBI1_D8

EBI1_D9

EBI1_D10

EBI1_D11

EBI1_D12

EBI1_D13

EBI1_D14

EBI1_D15

EBI1_SDCK E{3}

EBI1_SDCK{3}

EBI1_NSDC K{3}

EBI1_A16

EBI1_A17

EBI1_NCS1 /SDCS{3}

EBI1_SDW E{3}

EBI1_RAS{3}

EBI1_CAS{3}

EBI1_DQM0{3}

EBI1_DQM1{3}

RR9ARR9A18

RR9BRR9B27

RR11ARR11A18

RR11BRR11B27

RR11DRR11D45

RR11CRR11C36

RR9CRR9C36

RR9DRR9D45

RR13ARR13A18

RR13BRR13B27

RR13CRR13C36

RR13DRR13D45

RR17ARR17A18

RR17BRR17B27

RR17CRR17C36

RR17DRR17D45

RR19DRR19D45

RR19CRR19C36

RR21BRR21B27

RR21ARR21A18

RR25CRR25C36

RR25DRR25D45

RR23BRR23B27

RR23ARR23A18

RR25ARR25A18

RR25BRR25B27

RR23CRR23C36

RR23DRR23D45

RR21DRR21D45

RR21CRR21C36

RR19BRR19B27

RR19ARR19A18

EBI1_FLAS H_D0

EBI1_NAND _FSH_D0

EBI1_FLAS H_D1

EBI1_NAND _FSH_D1

EBI1_FLAS H_D2

EBI1_NAND _FSH_D2

EBI1_FLAS H_D3

EBI1_NAND _FSH_D3

EBI1_FLAS H_D4

EBI1_NAND _FSH_D4

EBI1_FLAS H_D5

EBI1_NAND _FSH_D5

EBI1_FLAS H_D6EBI1_FLASH _D6

EBI1_NAND _FSH_D6

EBI1_FLAS H_D7

EBI1_NAND _FSH_D7

EBI1_FLAS H_D8

EBI1_NAND _FSH_D8

EBI1_FLAS H_D9

EBI1_NAND _FSH_D9

EBI1_FLAS H_D10

EBI1_NAND _FSH_D10

EBI1_FLAS H_D11

EBI1_NAND _FSH_D11

EBI1_FLAS H_D12

EBI1_NAND _FSH_D12

EBI1_FLAS H_D13

EBI1_NAND _FSH_D13

EBI1_FLAS H_D14

EBI1_NAND _FSH_D14

EBI1_FLAS H_D15

EBI1_NAND _FSH_D15

R41 27RR41 27 R

R43 27RR43 27 R

R45 27RR45 27 R

RR31ARR31A18

RR31CRR31C36

RR33BRR33B27

RR33ARR33A18

RR15BRR15B27

RR33CRR33C36

RR33DRR33D45

RR32ARR32A18

EBI1_D0

EBI1_D1

EBI1_D2

EBI1_D3

EBI1_D4

EBI1_D5

EBI1_D6

EBI1_D7

EBI1_D8

EBI1_D9

EBI1_D10 E BI1_DDR_D10

EBI1_D11

EBI1_D12

EBI1_D13

EBI1_D14 E BI1_DDR_D14

EBI1_D15

RR1DRR1D45

RR1ARR1A18

RR1BRR1B27

RR1CRR1C36

RR3BRR3B27

RR3ARR3A18

RR3DRR3D45

RR3CRR3C36

RR5CRR5C36

RR7ARR7A18

RR5BRR5B27

RR7DRR7D45

RR5ARR5A18

RR7CRR7C36

RR7BRR7B27

RR5DRR5D45

EBI1_FLAS H_D[0..15] {6}

CKE_EBI1 {6 }

CLK_EBI1 {6 }

NCLK_EB I1 {6}

BA0_EBI1 {6}

BA1_EBI1 {6}

CS_EBI1 {6}

WE_ EBI1 {6}

RAS_EBI1 {6 }

CAS_EBI1 {6 }

DQM0_EB I1 {6}

DQM1_EB I1 {6}

EBI1_DDR_ D0

EBI1_DDR_ D1

EBI1_DDR_ D2

EBI1_DDR_ D3

EBI1_DDR_ D4

EBI1_DDR_ D5

EBI1_DDR_ D6

EBI1_DDR_ D7

EBI1_DDR_ D8

EBI1_DDR_ D9

EBI1_DDR_ D11

EBI1_DDR_ D12

EBI1_DDR_ D13

EBI1_DDR_ D15

EBI1_NAND _FSH_D0 EBI1_NAND _FSH_D1 EBI1_NAND _FSH_D2 EBI1_NAND _FSH_D3 EBI1_NAND _FSH_D4 EBI1_NAND _FSH_D5 EBI1_NAND _FSH_D6 EBI1_NAND _FSH_D7 EBI1_NAND _FSH_D8 EBI1_NAND _FSH_D9 EBI1_NAND _FSH_D10 EBI1_NAND _FSH_D11 EBI1_NAND _FSH_D12 EBI1_NAND _FSH_D13 EBI1_NAND _FSH_D14 EBI1_NAND _FSH_D15

EBI1_A[1..18]{3}

PC2{3}

PC3{3}

PC4{3,6}

EBI1_DDR_ D[0..15] {6}

EBI1_NAND _FSH_D[0..15] {6}

EBI1_A1

EBI1_A2

EBI1_A3

EBI1_A4

EBI1_A5

EBI1_A6

EBI1_A7

EBI1_A8

EBI1_A9

EBI1_A10

EBI1_A11

SDA10

EBI1_A12

EBI1_A13

EBI1_A14

EBI1_A15

EBI1_A16

EBI1_A17

EBI1_A18

(A19)

(A20)

(A21)

RR30BRR30B27

RR30CRR30C36

RR18DRR18D45

RR18ARR18A18

RR28BRR28B27

RR28CRR28C36

RR30DRR30D45

RR15ARR15A18

RR18BRR18B27

RR18CRR18C36

RR20BRR20B27

RR20ARR20A18

RR22ARR22A18

RR22BRR22B27

RR30ARR30A18

RR28DRR28D45

RR24DRR24D45

RR28ARR28A18

RR20CRR20C36

RR20DRR20D45

RR27ARR27A18

RR27BRR27B27

RR22CRR22C36

RR22DRR22D45

RR27DRR27D45

RR27CRR27C36

RR15CRR15C36

RR24BRR24B27

RR15DRR15D45

RR24CRR24C36

RR31BRR31B27

RR31DRR31D45

RR24ARR24A18

RR32BRR32B27

RR32CRR32C36

RR32DRR32D45

EBI1_FLAS H_A1 EBI1_FLAS H_A2 EBI1_FLAS H_A3 EBI1_FLAS H_A4 EBI1_FLAS H_A5 EBI1_FLAS H_A6 EBI1_FLAS H_A7 EBI1_FLAS H_A8 EBI1_FLAS H_A9 EBI1_FLAS H_A10 EBI1_FLAS H_A11 EBI1_FLAS H_A12 EBI1_FLAS H_A13 EBI1_FLAS H_A14 EBI1_FLAS H_A15 EBI1_FLAS H_A16 EBI1_FLAS H_A17 EBI1_FLAS H_A18 EBI1_FLAS H_A19 EBI1_FLAS H_A20 EBI1_FLAS H_A21

EBI1_FLAS H_A1

EBI1_DDR_ A2

EBI1_FLAS H_A2

EBI1_DDR_ A3

EBI1_FLAS H_A3

EBI1_DDR_ A4

EBI1_FLAS H_A4

EBI1_DDR_ A5

EBI1_FLAS H_A5

EBI1_DDR_ A6

EBI1_FLAS H_A6

EBI1_DDR_ A7

EBI1_FLAS H_A7

EBI1_DDR_ A8

EBI1_FLAS H_A8

EBI1_DDR_ A9

EBI1_FLAS H_A9

EBI1_DDR_ A10

EBI1_FLAS H_A10

EBI1_DDR_ A11

EBI1_FLAS H_A11

EBI1_DDR_ A12

EBI1_FLAS H_A12

EBI1_DDR_ A13

EBI1_FLAS H_A13

EBI1_DDR_ A14

EBI1_FLAS H_A14

EBI1_DDR_ A15

EBI1_FLAS H_A15

EBI1_FLAS H_A16

EBI1_FLAS H_A17

EBI1_FLAS H_A18

EBI1_FLAS H_A19

EBI1_FLAS H_A20

EBI1_FLAS H_A21

EBI1_FLAS H_A[1..21] {6}

EBI1

EBI1_DDR_ A[2..15] {6}

(SDA10)

SDA10

R47 27RR47 27 R

R49 27RR49 27 R

5

DQS0_EB I1 {6}

DQS1_EB I1 {6}

4

08-apr-10PPA2

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RES.ARRA YS-EBI0_EBI1

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3

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2

SCALE

MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

4

A2

12

EBI0_DQS0{3}

EBI0_DQS1{3}

8

R46 27RR46 27 R

R48 27RR48 27 R

7

DDR_DQS 0 {5}

DDR_DQS 1 {5}

EBI1_DQS0{3}

EBI1_DQS1{3}

EBI1_SDA1 0{3}

6

8

7

6

5

4

3

2

1

D D

C C

B B

DDR_D[0..1 5]{4}

DDR_A[0..1 3]{4}

MN6

MT47H64 M8CF-3 -F

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13

DDR_BA0{4 } DDR_BA1{4 }

DDR_CKE{4}

DDR_CLK{4} DDR_NCL K{4}

DDR_CS{4}

DDR_CAS{4} DDR_RAS{4}

DDR_W E{4 }

BA0 BA1

CKE

CK NCK

CS

CAS RAS

NWE

H8

A0

DDR2 SDRAM

H3

A1

H7

A2

J2

A3

J8

A4

J3

A5

J7

A6

K2

A7

K8

A8

K3

A9

H2

A10

K7

A11

L2

A12

L8

A13

G2

BA0

G3

BA1

F9

ODT

F2

CKE

E8

CK

F8

CK

G8

CS

G7

CAS

F7

RAS

F3

WE

G1

RFU1

L3

RFU2

L7

RFU3

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS DQS

RDQS/DM

RDQS/NU

VDD VDD VDD VDD

VDDL

VDDQ VDDQ VDDQ VDDQ VDDQ

VREF

VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ

VSSDL

C8

DDR_D0

C2

DDR_D1

D7

DDR_D2

D3

DDR_D3

D1

DDR_D4

D9

DDR_D5

B1

DDR_D6

B9

DDR_D7

B7 A8

B3 A2

A1 E9 H9 L1

E1

A9 C1 C3 C7 C9

E2

DDR_VRE F DDR_VRE F

A3 E3 J1 K9

A7 B2 B8 D2 D8

1V8

C67 100nC67 1 00n C69 100nC69 1 00n C71 100nC71 1 00n C73 100nC73 1 00n

C75 100nC75 1 00n

C77 100nC77 1 00n C79 100nC79 1 00n C81 100nC81 1 00n C83 100nC83 1 00n C85 100nC85 1 00n

DDR_DQS 0 {4}

DDR_DQM 0 {4 }

C87

C87 100n

100n

BA0 BA1

CKE

CK NCK

CS

CAS RAS

NWE

DDR_A0 DDR_A1 DDR_A2 DDR_A3 DDR_A4 DDR_A5 DDR_A6 DDR_A7 DDR_A8 DDR_A9 DDR_A10 DDR_A11 DDR_A12 DDR_A13

E7

MN7

MT47H64 M8CF-3 -F

H8

A0

H3

A1

H7

A2

J2

A3

J8

A4

J3

A5

J7

A6

K2

A7

K8

A8

K3

A9

H2

A10

K7

A11

L2

A12

L8

A13

G2

BA0

G3

BA1

F9

ODT

F2

CKE

E8

CK

F8

CK

G8

CS

G7

CAS

F7

RAS

F3

WE

G1

RFU1

L3

RFU2

L7

RFU3

DDR2 SDRAM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS DQS

RDQS/DM RDQS/NU

VDD VDD VDD VDD

VDDL

VDDQ VDDQ VDDQ VDDQ VDDQ

VREF

VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ

VSSDL

C8 C2 D7 D3 D1 D9 B1 B9

B7 A8

B3 A2

A1 E9 H9 L1

E1

A9 C1 C3 C7 C9

E2

A3 E3 J1 K9

A7 B2 B8 D2 D8

E7

DDR_D8 DDR_D9 DDR_D10 DDR_D11 DDR_D12 DDR_D13 DDR_D14 DDR_D15

1V8

C68 100nC68 1 00n C70 100nC70 1 00n C72 100nC72 1 00n C74 100nC74 1 00n

C76 100nC76 1 00n

C78 100nC78 1 00n C80 100nC80 1 00n C82 100nC82 1 00n C84 100nC84 1 00n C86 100nC86 1 00n

DDR_DQS 1 {4}

DDR_DQM 1 {4 }

C88

C88 100n

100n

1V8

L5 10 uHL5 10uH

R51

R501RR50 1R

C90

4.7u

A A

8

7

6

5

C89

C89 100n

100n

C91

C91 100n

100n

R51

1.5k

R52

1.5k

DDR_VRE F

4

DDR_VRE F {3,6}

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EBI0_DDR2

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2

SCALE

MODIF.

1/1

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08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

5

A2

12

8

EBI1_FLAS H_D[0..15]{4}

EBI1_FLAS H_A[1..21]{4}

EBI1_DDR_ D[0..15]{4}

EBI1_DDR_ A[2..15]{4}

EBI1_DDR_ A2 EBI1_DDR_ A3 EBI1_DDR_ A4

D D

BA0_EBI1{4 } BA1_EBI1{4 }

CKE_EBI1{4}

CLK_EBI1{4} NCLK_EB I1{4}

CS_EBI1{4}

CAS_EBI1{4}

C C

RAS_EBI1{4}

WE_ EBI1{4 }

EBI1_DDR_ A5 EBI1_DDR_ A6 EBI1_DDR_ A7 EBI1_DDR_ A8 EBI1_DDR_ A9 EBI1_DDR_ A10 EBI1_DDR_ A11 EBI1_DDR_ A12 EBI1_DDR_ A13 EBI1_DDR_ A14 EBI1_DDR_ A15

BA0_EBI1 BA1_EBI1

CKE_EBI1

CLK_EBI1 NCLK_EB I1

CS_EBI1

CAS_EBI1 RAS_EBI1

WE_ EBI1

(SDA10) (SDA10)

(NCS1)

7

MN8

H8

A0

H3

A1

H7

A2

J2

A3

J8

A4

J3

A5

J7

A6

K2

A7

K8

A8

K3

A9

H2

A10

K7

A11

L2

A12

L8

A13

G2

BA0

G3

BA1

F9

ODT

F2

CKE

E8

CK

F8

CK

G8

CS

G7

CAS

F7

RAS

F3

WE

G1

RFU1

L3

RFU2

L7

RFU3

MT47H64 M8CF-3 -F

DDR2 SDRAM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS DQS

RDQS/DM RDQS/NU

VDD VDD VDD VDD

VDDL

VDDQ VDDQ VDDQ VDDQ VDDQ

VREF

VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ

VSSDL

6

C8

EBI1_DDR_ D0

C2

EBI1_DDR_ D1

D7

EBI1_DDR_ D2

D3

EBI1_DDR_ D3

D1

EBI1_DDR_ D4

D9

EBI1_DDR_ D5

B1

EBI1_DDR_ D6

B9

EBI1_DDR_ D7

B7 A8

B3 A2

1V8 1V8

A1

C92 100nC92 1 00n

E9

C94 100nC94 1 00n

H9

C96 100nC96 1 00n

L1

C98 100nC98 1 00n

E1

C100 100nC 100 100n

A9

C102 100nC 102 100n

C1

C104 100nC 104 100n

C3

C106 100nC 106 100n

C7

C108 100nC 108 100n

C9

C111 100nC 111 100n

E2

VREF1

A3 E3 J1 K9

A7 B2 B8 D2 D8

C116

C116 100n

100n

DQS0_EB I1 {4}

DQM0_EB I1 {4}

EBI1_DDR_ A2 EBI1_DDR_ A3 EBI1_DDR_ A4 EBI1_DDR_ A5 EBI1_DDR_ A6 EBI1_DDR_ A7 EBI1_DDR_ A8 EBI1_DDR_ A9 EBI1_DDR_ A10 EBI1_DDR_ A11 EBI1_DDR_ A12 EBI1_DDR_ A13 EBI1_DDR_ A14 EBI1_DDR_ A15

E7

5

BA0_EBI1 BA1_EBI1

CKE_EBI1

CLK_EBI1 NCLK_EB I1

CS_EBI1

CAS_EBI1 RAS_EBI1

WE_ EBI1

MN9

H8

A0

H3

A1

H7

A2

J2

A3

J8

A4

J3

A5

J7

A6

K2

A7

K8

A8

K3

A9

H2

A10

K7

A11

L2

A12

L8

A13

G2

BA0

G3

BA1

F9

ODT

F2

CKE

E8

CK

F8

CK

G8

CS

G7

CAS

F7

RAS

F3

WE

G1

RFU1

L3

RFU2

L7

RFU3

MT47H64 M8CF-3 -F

DDR2 SDRAM

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7

DQS DQS

RDQS/DM RDQS/NU

VDD VDD VDD VDD

VDDL

VDDQ VDDQ VDDQ VDDQ VDDQ

VREF

VSS VSS VSS VSS

VSSQ VSSQ VSSQ VSSQ VSSQ

VSSDL

4

C8 C2 D7 D3 D1 D9 B1 B9

B7 A8

B3 A2

A1 E9 H9 L1

E1

A9 C1 C3 C7 C9

E2

A3 E3 J1 K9

A7 B2 B8 D2 D8

E7

EBI1_DDR_ D8 EBI1_DDR_ D9 EBI1_DDR_ D10 EBI1_DDR_ D11 EBI1_DDR_ D12 EBI1_DDR_ D13 EBI1_DDR_ D14 EBI1_DDR_ D15

VREF1

C117

C117 100n

100n

DQS1_EB I1 {4}

DQM1_EB I1 {4}

100n

C93

100n

C95

100n

C97

100n

C99

100n

C101

100n

C103

100n

C105

100n

C107

100n

C109

100n

C112

3

1V8

EBI1_NRD/C FOE{3}

EBI1_NW E/NWR0/CF WE{3}

JP9JP9

EBI1_NCS0{3}

DDR_VRE F{3,5}

1 2

VREF1

2

EBI1_FLAS H_A1 EBI1_FLAS H_A2 EBI1_FLAS H_A3 EBI1_FLAS H_A4 EBI1_FLAS H_A5 EBI1_FLAS H_A6 EBI1_FLAS H_A7 EBI1_FLAS H_A8 EBI1_FLAS H_A9 EBI1_FLAS H_A10 EBI1_FLAS H_A11 EBI1_FLAS H_A12 EBI1_FLAS H_A13 EBI1_FLAS H_A14 EBI1_FLAS H_A15 EBI1_FLAS H_A16 EBI1_FLAS H_A17 EBI1_FLAS H_A18 EBI1_FLAS H_A19 EBI1_FLAS H_A20 EBI1_FLAS H_A21

R200 0RR200 0 R

R53 100kR 53 100k R54 0RR5 4 0R R55 100kR 55 100k

1V8

R56

470k

MN10

DNPMN 10

DNP

E8

A0

D8

A1

C8

A2

B8

A3

A8

A4

B7

A5

A7

A6

C7

A7

A2

A8

B2

A9

C2

A10

A1

A11

B1

A12

C1

A13

D2

A14

D1

A15

D4

A16

B6

A17

A6

A18

C6

A19

B3

A20

C3

NC/A21

B4

CLK

B5

RESET

C4

LATCH

D6

WP

E7

CE

F8

OE

C5

WE

A5

VPP

M58W R032KT_VFBGA 56

DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8

DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15

WAIT

VDD

VDDQ VDDQ

VSS

VSS VSSQ VSSQ

1

F7

EBI1_FLAS H_D0

E6

EBI1_FLAS H_D1

E5

EBI1_FLAS H_D2

G5

EBI1_FLAS H_D3

E4

EBI1_FLAS H_D4

G3

EBI1_FLAS H_D5

E3

EBI1_FLAS H_D6

G1

EBI1_FLAS H_D7

G7

EBI1_FLAS H_D8

F6

EBI1_FLAS H_D9

F5

EBI1_FLAS H_D10

F4

EBI1_FLAS H_D11

D5

EBI1_FLAS H_D12

F3

EBI1_FLAS H_D13

F2

EBI1_FLAS H_D14

E2

EBI1_FLAS H_D15

D3

D7

NC

1V8

A4

C110 100nC 110 100n

G4

C113 100nC 113 100n

E1

C114 100nC 114 100n

G6

C115 100nC 115 100n

A3 F1 G2 G8

EBI1_NAND _FSH_D[0..15]{4}

MN11

PC5{3}

PC4{3,4} EBI1_NAND OE{3} EBI1_NAND WE{3}

B B

IMPORTANT note about system booting: The bootROM allows booting from the block 0 of a NandFlash connected on CS3. However, the bootROM does not feature ECC (Error Checking and Correction) on NandFlash. Most of the NandFlash vendors do not guarantee anymore that block 0 is error free. Therefore we advise the bootstrap program to be located into another device supported by the bootrom (DataFlash, Serial Flash, SDCARD or EEPROM) and implement NandFlash access with ECC.

A A

8

7

PC14{3}

PC8{3}

(NANDCLE) (NANDALE)

(NCS3)

(RDY/BSY)

6

JP10

1 2

SIP2

1V8

0R

R570RR57

0R

R580RR58

R59 470kR 59 470k

0R

R600RR60

1k

R611kR61

R62 470kR 62 470k

D5

CLE

C4

NAND FLASH

ALE

D4

RE

C7

WE

C6

CE

C8

RB EBI1_ NAND_FSH_D6

R/B

C3

WP

G5

R63

R63 0R

0R

DNP

5

LOCK

A1

N.C1

A2

N.C2

A9

N.C3

A10

N.C4

B1

N.C5

B9

N.C6

B10

N.C7

D6

N.C8

D7

N.C9

D8

N.C10

E3

N.C11

E4

N.C12

E5

N.C13

E6

N.C14

E7

N.C15

E8

N.C16

F3

N.C17

F4

N.C18

F5

N.C19

F6

N.C20

F8

N.C21

G3

N.C22

G8

N.C23

L1

N.C24

L2

N.C25

MT29F2G 08ABDHC:D

I/O1 I/O2 I/O3 I/O4 I/O5 I/O6

I/O7 N.C26 N.C27 N.C28 N.C29 N.C30 N.C31 N.C32 N.C33

N.C34 N.C35 N.C36 N.C37 N.C38 N.C39

VCC VCC VCC VCC

VSS

I/O0

H4

EBI1_NAND _FSH_D0

J4

EBI1_NAND _FSH_D1

K4

EBI1_NAND _FSH_D2

K5

EBI1_NAND _FSH_D3

K6

EBI1_NAND _FSH_D4

J7

EBI1_NAND _FSH_D5

K7 J8

EBI1_NAND _FSH_D7

H3

EBI1_NAND _FSH_D8

J3

EBI1_NAND _FSH_D9

H5

EBI1_NAND _FSH_D10

J5

EBI1_NAND _FSH_D11

H6

EBI1_NAND _FSH_D12

G6

EBI1_NAND _FSH_D13

H7

EBI1_NAND _FSH_D14

G7

EBI1_NAND _FSH_D15

L9 L10 M1 M2 M9 M10

1V8

D3 G4 H8 J6

C5 F7 K3 K8

4

C118 100nC1 18 100 n C119 100nC1 19 100 n C120 100nC1 20 100 n C121 100nC1 21 100 n

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EBI1_MEMO RY

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MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

6

A2

12

8

D D

(MCI0_CD)

(MCI0_DA1)

PA3 PA2

(MCI0_DA0)

PA0

(MCI0_CK)

PA1

(MCI0_CDA)

PA5

(MCI0_DA3)

PA4

(MCI0_DA2)

C C

R64

R64 10k

10k

7

RR38 27RRR38 27R

1 2 3 4 5

RR40 27RRR 40 27R

6

3V3

R188

R189

R187

68k

8 7 6

R190

R65

R65 10k

10k

68k

C122 100nC 122 100n

3V3

SD/MMC CARD INTERFACE - MCI0

J6

8 7 6 5 4 3 2 1 9

FPS009-3 202-BL

5

PD29{3} PD11{3}PD10{3}

12 11 10

PA[22..31]{3,10}PA[0..5]{3 }

4

(MCI1_W P) (MCI1_CD)

PA24

(MCI1_DA1)

PA23

(MCI1_DA0)

PA31

(MCI1_CK)

PA22

(MCI1_CDA)

PA26

(MCI1_DA3)

PA25

(MCI1_DA2)

PA27

(MCI1_DA4)

PA28

(MCI1_DA5)

PA29

(MCI1_DA6)

PA30

(MCI1_DA7)

RR39

1 2 3 4 5

1

RR41 27RRR 41 27R

2 3 4 5

RR42

1 2 3 4 5

3

3V3

R192

R193

R194

R195

R196

R197

R191

68k

8 7 6

27R

8 7 6

27R

8 7 6

R197

68k

R198

68k

123

3V3

2

678

RR36

RR36 10k

10k

4 5

J5

8 7 6 5 4 3 2 1 9

7SDMM-B0 -2211

C123

C123 100n

100n

1

16 15 14

13 12 11 10

SD/MMCPlus CARD INTERFACE - MCI1

3V3

R66

R66 10k

B B

PA21{3,12}

PA20{3,12}

(TWCK 0) (TWDO )

3V3

C125 100nC 125 100n

MN12

6 5

8

4

SCL SDA

VCC

GND

AT24C51 2BN

1

A0

2

A1

3

A3

7

WP

10k

PB0{3} PB1{3}

12

JP13

SIP2

PB2{3} PB3{3}

(SPI0_MISO) (SPI0_MOSI) (SPI0_SPCK ) (SPI0_NPCS 0)

NRST{2,3,8,9,10 ,12}

SERIAL EEPROM

A A

8

7

6

5

Test point

DNP

JP11

1

R67

3

R67 470k

470k

2

1 2

JP12

JP12 SIP2

SIP2

SERIAL DATAFLASH

4

MN13

8

SO

1

SI

2

SCK

4

CS

3

RESET

AT45DB3 21D-SU

VCC

GND

WP

3V3

6

C124

C124 100n

100n

7

5

R68

R68 0R

0R

DNP

08-apr-10PPA2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

AT91SAM9M10-G 45-EK

MCI & TW I

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

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2

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MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

7

A2

12

8

D D

PE31{3}

C C

B B

A A

PD7{3} PD9{3}

PD6{3}

PD8{3} NRST{2,3,7,9,10,12}

(EXT_CLK)

C133 22pC133 22p

C137 22pC137 22p

R75 0R

2 4

(AC97TX) (AC97CK)

(AC97RX)

(AC97FS)

DNP

Y3

24.576MHz

1 3

7

JP17/JP18 are used as Testpoint

C134

C135

10u

10V

100n

R78 49.9RR78 49.9R

3V3 AVDD_AC97

C152

C152 10u

10u

10V

C136

C136 100n

100n

C145

C145 100n

100n

AGND_AC97

C153

C153 100n

100n

R85 0RR85 0R

6

3V3

AGND_AC97

AVDD_AC97

L11

L11 10uH

10uH

R73 10kR73 10k

R74 100kR74 100k

MN14

1

DBVDD

2

XTLIN

3

XTLOUT

4

DGND1

5

SDATAOU T

6

BITCLK

7

DGND2

8

SDATAIN

9

DCVDD

10

SYNC

11

RESET

12

CREF

C154

C154 10u

10u

10V

AGND_AC97

JP17 DNPJP17 DNP

JP18 DNPJP18 DNP

48

47

49

THERMAL

GPIO5/SPDIF

AVDD2

13

AVDD_AC97

12

43

45

46

44

GPIO4

GPIO3

GPIO1

GPIO2/IRQ

WM9711L

NC114NC2

NC417NC3

15

18

16

AGND_AC97

5

R69 0RR69 0R

R70 0RR70 0R

C131

C132

100n

ROUT2 LOUT2

SPKGND

CAP2 COMP3 COMP2 COMP1

MICBIAS

VREF

AGND

AVDD1

36 35 34 33 32 31 30 29 28 27 26 25

C132 10u

10u

10V

C130

100n

AGND_AC97

37

39

41

42

38

40

OUT3

AGND2

HPVDD

SPKVDD

HP_GND

HP_OUT_L

HP_OUT_R

MONOOUT

PHONE20PCBEEP19AGND1

LINE_IN_L23LINE_IN_R24MIC121MIC2

22

C1461uC146 1u

C1471uC147 1u

R83

R83 680R

680R

C1501uC150 1u

C1511uC151 1u

JP14

1 2

DNP

C138

C138 100n

100n

4

C139

C139 100n

100n

AGND_AC97

R84

R84 680R

680R

C126 100u/6.3V

C127 100u/6.3V

AGND_AC97

C140

C140 10u

10u

10V

R81

8.2K

+

C141

C141 100n

100n

R71

R71 47k

47k

R76 0RR76 0R

R77 0RR77 0R

C142

C142 10u

10u

10V

C143

C143 100n

100n

AGND_AC97

C144

C144 10u

10u

10V

R79 8.2KR79 8.2K

R80 8.2KR80 8.2K

R82

8.2K

R72

R72 47k

47k

3

L6

L6 220ohm at 100MHz

220ohm at 100MHz

1 2

L7

L7 220ohm at 100MHz

220ohm at 100MHz

12

L8

L8 220ohm at 100MHz

220ohm at 100MHz

1 2

L9

1 2

220ohm at 100MHz

L10

L10 220ohm at 100MHz

220ohm at 100MHz

1 2

L12

L12 220ohm at 100MHz

220ohm at 100MHz

JP15

8 Ohm SPEAKER

DNP

OUTPUT

C148

C148 470p

470p

C155

C155 470p

470p

C128

C128 470p

470p

AGND_AC97

C149

C149 470p

470p

C156

C156 470p

470p

C129

C129 470p

470p

2

1

2 5

3 4

STEREO_3.5mm

2 5

3 4

STEREO_3.5mm

2 5

3 4

STEREO_3.5mm

1

HEADPHONE LINE-OUT

J7

LINE-IN

J8

MONO / STEREO MICROPHONE INPUT

J9

08-apr-10PPA2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

AT91SAM9M10-G 45-EK

AUDIO AC97

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

8

7

6

5

4

3

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

SCALE

MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

8

A2

12

8

7

6

5

4

3

2

1

3V3

C158 100nC158 100n

SERIAL DEBUG PORT

J12

J12 G3505-4NBT1S1W

G3505-4NBT1S1W



5

L13

1 2

L14

1 2

C157 100nC157 100n

C165 100nC165 100n

6

J10J10

1

D D

C C

B B

6 2 7 3 8 4 9 5

10

11

1

+

33u

C168

C170

4

220ohm at 100MHz

C167

C167 100n

100n

MN15

VCC

15

GND

2

V+

6

14

7

13

ADM3202ARNZ

116

C1+

C159

C159 100n

100n

3

C1-

4

C2+

C163

C163 100n

100n

5

C2-V-

11

T

10

T

12

R

98

R

R90 0RR90 0R

3V3

R87

R88

100k

PB13 {3}

PB12 {3}

PB4{3}

PD16{3}

PB5{3}

PD17{3}

R89

R89 100k

100k

3V3

R86

R86 100k

100k

C160

C160 100n

100n

C164

C164 100n

100n

MN16

1 16

C1+V+VCC

GND

3

C1-

4

C2+

5

C2- V-

11

T

10

T

12

R

9 8

R

ADM3202ARNZ

USB HOST INTERFACE

2

3

5V

MN17

C169

C169 100n

100n

MN17

8

OUTA

7

IN

GNG6FLGB

5

OUTB

AIC1526-0GS

ENA

FLGA

ENB

1

2

3

4

(ENA)

(FLGA)

(FLGB)

(ENB)

HDMA {3}

HDPA {3}

PD1 {3}

PD2 {3}

PD4 {3}

PD3 {3}

3V3 3V3

J13

12 34 56 78 910 1112 13

14

15

16

17

18

19

20

HTST-110-01-SM-D

ICE INTERFACE

3V3

RR43

100k

R93 0RR93 0R

678

123

4 5

R91 0R

R92 0RR92 0R

R94

R94 0R

0R

DNP

3V3

C161

C161 100n

100n

15

2

6

14

7

13

DNP

C162 100nC162 100n

C166 100nC166 100n

NTRST TDI TMS TCK RTCK TDO NRST

RS232 COM PORT

1 6 2 7 3 8 4 9 5

10

NTRST {3} TDI {3} TMS {3} TCK {3} RTCK {3} TDO {3} NRST {2,3,7,8,10,12}

J11J11

11

R95 47kR95 47k

C171

C171 10p

J14

7

6

C172

100n

A A

100n

8

1

VBUS

2

DM

3

SHD

DP

4

ID

5

GND

G3515-09010101-00

10p

USB HOST/DEVICE INTERFACE

7

(VBUS)

R96

R96 68k

68k

PB19 {3}

6

3V3

R97

R97 47k

47k

HDMB {3}

(IDUSB)

5

HDPB {3} PD28 {3,11}

08-apr-10PPA2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

AT91SAM9M10-G 45-EK

SERIAL INTERF ACES

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2

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MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

9

A2

12

8

D D

PA17{3}

PA7{3} PA6{3} PA11{3} PA10{3} PA14{3}

PA9{3} PA8{3} PA13{3}

C C

B B

PA12{3}

PA28{3,7} PA15{3}

PA27{3,7} PA16{3}

PA30{3,7} PA29{3,7}

PA18{3}

PA19{3}

PD5{3}

(TX_CLK)

(TXD3) (TXD2) (TXD1) (TXD0) (TX_EN)

(RXD3) (RXD2) (RXD1) (RXD0)

(RX_CLK) (RX_DV)

(TX_ER) (RX_ER)

(COL) (CRS)

(MDC) (MDIO) (MDINTR)

7

R108 0R DNPR108 0R DNP R103 0R DNPR103 0R DNP

R104 0R DNPR104 0R DNP R105 0R DNPR105 0R DNP

R109 0R DNPR109 0R DNP

R110 0R DNPR110 0R DNP

R112 0R DNPR112 0R DNP R114 0R DNPR114 0R DNP

NRST{2,3,7,8,9,12}

123

RR44

RR44 10k

10k

6

3V3

R98 10kR98 10k

Y4

OE

VSS OUT

678

4 5

123

RR45

RR45 10k

10k

50MHz

4 5

41

VDD

32

678

3V3

123

4 5

RR46

RR46 10k

10k

3V3

JP16JP16

R990RR99 0R

R115 1.5kR115 1.5k

1 2

C173

C173 100n

100n

R100 0R

R101 0RR101 0R

R106 0R DNPR106 0R DNP

C184 100nC184 100n

C185 100nC185 100n

C186 100nC186 100n

R120 0RR120 0R

3V3

DNP

MN18

42

REF_CLK /XT2

17

TXD3

18

TXD2

19

TXD1

20

TXD0

21

TX_EN

22

TX_CLK/ISO LATE

26

RXD3/PHYAD3

27

RXD2/PHYAD2

28

RXD1/PHYAD1

29

RXD0/PHYAD0

34

RX_CLK/1 0BTSER

37

RX_DV/TE STMODE

16

TX_ER/TX D4

38

RX_ER/RX D4/RPTR

36

COL/RMII

35

CRS/PHYAD4

24

MDC

25

MDIO

32

MDINTR

39

DISMDIX

41

DVDD

30

DVDD

23

DVDD

15

DGND

33

DGND

44

DGND

10

PWRD WN

40

RESET

5

C174

C174 22p

22p

DNP

1 3

DM9161AEP

CABLEST S/LINKSTS

24

Y5

25MHz

DNP

BGRESG

LEDMODE

LED0/OP0 LED1/OP1 LED2/OP2

C175

C175 22p

22p

DNP

XT1

TX+

RX+

RX-

AVDDR

AVDDT

AGND AGND AGND

BGRES

N.C

4

43

7

8

TX-

3

4

1

2

9

5 6 46

47

48 31 11 12 13 14

AVDDT

C177 100nC177 100n

C179 100nC179 100n

C182 100nC182 100n

R116 0RR116 0R

R117

6.8k

L15

1 2

2200R

C180

C180 10u

10u

10V

123

3V3

GND_ETH

678

RR47

RR47 10k

10k

4 5

45

AVDDT

C181

C181 10u

10u

10V

D4 YellowD4 Yellow

D5 GreenD5 Green

D6

R111

49.9R

3

R102

49.9R

GND_ETH

12

GreenD6Green

C176

C176 100n

100n

C183

C183 100n

100n

AVDDT

R113

49.9R

R118

R119

R121

R107

49.9R

2

GND_ETH

J15

TD+

1

CT

4

TD-

2

RD+

3

CT

5

RD-

6

C178

GND_ETH

C178 100n

100n

NC

7

8

J00-0061NL

7575

1nF

RJ45 ETHERNET CONNECTOR

3V3

FULL DUPLEX

470R

SPEED 100

470R

LINK&ACT

470R

1

15

16

TX+

1

TX-

2

RX+

3

RX-

6

75

4

5

7

8

3V3

C187

C187 10u

10u

10V

R122 0RR122 0R

A A

8

7

6

R123 0RR123 0R

5

GND_ETH

08-apr-10PPA2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

AT91SAM9M10-G 45-EK

RMII_MII ETHERNET

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

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3

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MODIF.

1/1

DES.

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

10

A2

12

8

M1

D D

4.3" 480x272 TFT LCD DISPLAY

TRULY

TFT1N46 33-E

C C

LCD1

LCM_fix

7

PIN 40

TOP SIDE

on

TOP SIDE

Conductors

PIN 1

6

J24

54104-40 31

5

VLED+ VLED-

Y_UP X_LEFT Y_LOW X_RIGHT

DE VSYNC HSYNC DISP PCLK

B7 B6 B5 B4 B3 B2 B1 B0 G7 G6 G5 G4 G3 G2 G1 G0 R7 R6 R5 R4 R3 R2 R1 R0

LCDDEN LCDVSYNC LCDHSYNC

LCDDOTC K

LCDD23 LCDD22 LCDD21 LCDD20 LCDD19 LCDD18 LCDD17 LCDD16 LCDD15 LCDD14 LCDD13 LCDD12 LCDD11 LCDD10 LCDD9 LCDD8 LCDD7 LCDD6 LCDD5 LCDD4 LCDD3 LCDD2 LCDD1 LCDD0

C188

C188 100n

100n

C189

C189 10u

10u

(LCDDEN)

LCDVSYNC LCDHSYNC

1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5 1 2 3 4 5

3V3

LCDDOTC K

8

BLUE7

7

BLUE6

6

27R

BLUE5 BLUE4

RR48

8

BLUE3

7

BLUE2

6

27R

BLUE1 BLUE0

RR49

8

GREEN7

7

GREEN6

6

27R

GREEN5 GREEN4

RR50

8

GREEN3

7

GREEN2

6

27R

GREEN1 GREEN0

RR51

8

RED7

7

RED6

6

27R

RED5 RED4

RR52

8

RED3

7

RED2

6

27R

RED1 RED0

RR53

40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9 8 7 6 5 4 3 2 1

PE6

4

R125 27 RR125 2 7R

R127 0RR127 0 R R128 0RR128 0 R R129 0RR129 0 R

R130 0RR130 0 R R131 0RR131 0 R

R132 0RR132 0 R R133 0RR133 0 R R134 0RR134 0 R

(LCDPW R)

PE25 PE24 PE23

PE16 PE15

PE9 PE8 PE7

3

PE0

R126

4.7k

LCDDOTC K{12 } LCDHSYNC{12} LCDVSYNC{12}

TV_XCLK{12} TV_HSYNC{12} TV_VSYNC{12}

LCDDOTC K LCDHSYNC LCDVSYNC

RR54ARR54A18 RR54BRR54B27 RR54CRR54C36 RR54DRR54D45

R201 10 RR201 1 0R R202 10 RR202 1 0R R203 10 RR203 1 0R R204 10 RR204 1 0R

2

(B7)

PE30

(B6)

PE29 PE28

(B5)

PE27

(B4) (B3)

PE26

(B2)

PE25

(B1)

PE24

(B0)

PE23

(G7)

PE22 PE21

(G6) (G5)

PE20 PE19

(G4) (G3)

PE18

(G2)

PE17

(G1)

PE16

(G0)

PE15

(R7)

PE14 PE13

(R6) (R5)

PE12

(R4)

PE11

(R3)

PE10 PE9

(R2) (R1)

PE8

(R0)

PE7

(LCDDEN)

PE6

(LCDDOTC K)

PE5

(LCDHSYNC)

PE4 PE3

(LCDVSYNC) (LCDCC)

PE2 PE1

(LCDPW R)

PE0

1

PE[0..30] {3,12}

R136 0R DNPR136 0 R DNP R137 0RR137 0 R

R138 0R DNPR138 0 R DNP R139 0RR139 0 R

R140 0R DNPR140 0 R DNP

B B

BLUE3

5V

C190

C190 10u

10u

PE2{3,12}

BL_SHDN #

R162

R162 10k

10k

2 x 4 LEDs Back Light

A A

8

2*15mA, 12.6+/-0.6V MAX

5

4

L16

L16 22uH

22uH

MN19

VIN

SHDN#

CP2122S T

SW

GND

D7

RB160M-6 0

1 2 3

FB

300mV

7

VLED+

C191

2.2u

VLED-

R164

R164 10R

10R

LCDHSYNC

X_LEFT X_RIGHT Y_UP Y_LOW

6

PE4

R150 0R DNPR150 0R DNP

R153 0RR153 0R R154 0RR154 0R R156 0RR156 0R R158 0RR158 0R

C192

10n

DNP

C193

10n

DNP

C194

10n

DNP

TSADTRG

AD3Ym AD2Yp AD1Xm AD0Xp

R205

R205 220K

220K

5

PD28 {3,9}

PD23 {3,12} PD22 {3,12} PD21 {3,12} PD20 {3,12}

GREEN3 PE18

GREEN2

RED7

RED6

RED5

RED4

RED3

4

R141 0RR141 0 R

R142 0R DNPR142 0 R DNP R143 0RR143 0 R

R144 0R DNPR144 0 R DNP R145 0RR145 0 R

R146 0R DNPR146 0 R DNP R147 0RR147 0 R

R148 0R DNPR148 0 R DNP R149 0RR149 0 R

R151 0R DNPR151 0 R DNP R152 0RR152 0 R

R155 0R DNPR155 0 R DNP R157 0RR157 0 R

R159 0R DNPR159 0 R DNP R160 0RR160 0 R

R161 0R DNPR161 0 R DNP R163 0RR163 0 R

R165 0R DNPR165 0 R DNP R166 0RR166 0 R

R167 0R DNPR167 0 R DNP R168 0RR168 0 R

R169 0R DNPR169 0 R DNP R170 0RR170 0 R

R171 0R DNPR171 0 R DNP R172 0RR172 0 R

R173 0R DNPR173 0 R DNP R174 0RR174 0 R

PE24 PE30BLUE7

PE23 PE29BLUE6

PE22 PE28BLUE5

PE21 PE27BLUE4

PE20 PE26

PE18 PE22GREEN7

PE17 PE21GREEN6

PE16 PE20GREEN5

PE15 PE19GREEN4

PE14

PE13 PE17

PE12 PE14

PE11 PE13

PE10 PE12

PE9 PE11

PE8 PE10

3

AT91SAM9M10-G 45-EK

DISPLAY

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

2

A

REV DATE

MODIF.

REV DATE

MODIF.

REV DATE

MODIF.

SCALE

1/1

DES.

08-apr-10PPA2

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

11

A2

12

8

7

6

5

4

3

2

1

PE[0..30]{3,11}

(B7)

PE30

(B6)

PE29 PE28

(B5)

PE27

(B4) (B3)

3V3

PA20{3,7}

PA21{3,7}

NRST{2 ,3,7,8,9,10}

PE26 PE25 PE24 PE23 PE22 PE21 PE20 PE19 PE18 PE17 PE16 PE15 PE14 PE13 PE12 PE11 PE10 PE9 PE8 PE7

(LCDDEN)

PE6

(LCDDOTC K)

PE5

(HSYNC)

PE4

(VSYNC)

PE3

(LCDCC)

PE2

(LCDMOD)

PE1

(LCDPW R)

PE0

R180 4.7 kR180 4.7k

R184 10 k DNPR184 10k DNP

Y6

OE

VSS OUT

DNP

(B2) (B1) (B0) (G7) (G6) (G5) (G4) (G3) (G2) (G1) (G0) (R7) (R6) (R5) (R4) (R3) (R2) (R1) (R0)

TV_VSYNC{11} TV_HSYNC{11 } TV_XCLK{11 }

(TWDO ) (TWCK 0)

13MHz

L17

L17 2200R

2200R

R182

R182 75R

75R

1 2

C198

10u

10V

1 2

C204 33 pC204 3 3p

L22

1.8uH

1.8uHR179 4.7 kR179 4.7k

C205

C205 100p

100p

L18

L18 2200R

2200R

L19

L19 2200R

2200R

L20

L20 2200R

2200R

L21

L21 2200R

2200R

MN20

CH7024B

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23

V H XCLK DE

SPD SPC

RESET

NC

C208

C208 10p

10p

CH7024B

XI/FIN

34

R1850RR185 0R

1 3

24

AVDD_PLL

AGND_PLL

AVDD_DAC

AGND_DAC

35

Y7

13MHzY713MHz

C/CVBS

XO

VDDIO

DVDD

DGND

AVDD

AGND

ISET

CVBS

P-OUT

C209

C209 10p

10p

38 16

C197

C196

100n

18

32

31

33

36

25

29

30

28

27

Y

26

R181 75RR1 81 75R

R183 75RR1 83 75R

C200

C200 100n

100n

C202

C202 100n

100n

C203

C203 100n

100n

R178 1.2k

1%

37

TP6TP6

42

PE23

43

PE24

44

PE25

45

PE26

46

PE27

47

PE28

48

PE29

1

PE30

2

PE15

3

PE16

4

PE17

5

PE18

6

PE19

7

PE20

8

PE21

9

PE22

10

PE7

11

PE8

12

PE9

13

PE10

14

PE11

15

PE12

17

PE13

19

PE14

39 40 41 20

PE6

21 22

23

DNP

R186 0R

24

3V3

41

VDD

32

C207

C207 100n

100n

DNP

3V3

1V8

C199

10u

10V

3V3

C201

10u

10V

D8

C206

1 2

100p

BAT54SL T1G

Composite Video Output

3V3

J20

3

RCA JACk

3

RCA JACk

1

D D

C C

B B

CONNECTOR EXTENSION FOR LARGE LCD

J23

DNP

DNP PE8 PE10 PE12 PE14 PE16 PE18 PE20 PE22 PE24 PE26 PE28

LCDHSYNC{11} LCDDOTC K{11 }

PD21{3 ,11} PD23{3 ,11}

PD25{3} PD27{3} PD19{3}

PE30

PE6 PE0

3V3

(AD1Xm) (AD3Ym) (AD2Yp)

R175 0R

DNP

3V3

1 2 3 4 5 6 7 8

9 10 11 12 13 15 17 19 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

HDR_2x20_ SMT

J18

1 2

3 4

5 6

7 8

9 10 11 12 13 15 17 19

HDR_2x10_ SMT

DNP

14 16 18 20

IMAGE SENSOR CONNECTOR

C210

C210 100n

100n

PE7 PE9 PE11 PE13 PE15 PE17 PE19 PE21 PE23 PE25 PE27 PE29

PE2 PE1

(GPIO2)(GPIO1)

(AD0Xp)

R176 0R

DNP

3V3

C211

C211 10u

10u

10V

C212

C212 100n

100n

LCDVSYNC

PD15 {3}PD14{3}

PD20 {3,11} PD22 {3,11}

PD24 {3} PD26 {3} PD18 {3}

5V

3V3

{11}

J17

PB[8..11]{3}

PB[20..31]{3}

A A

8

7

6

5

PB8 PB9 PB10 PB11

PB20 PB21 PB22 PB23 PB24 PB25 PB26 PB27 PB28 PB29 PB30 PB31

4

(ISI_D8) (ISI_D09) (ISI_D10) (ISI_D11)

(ISI_D0) (ISI_D1) (ISI_D2) (ISI_D3) (ISI_D4) (ISI_D5) (ISI_D6) (ISI_D7) (ISI_PCK) (ISI_VSYNC) (ISI_HSYNC) (ISI_MCK)

VDDISI{2,3}

PD12{3}

3

(CTRL1) (CTRL2 )

PA21

PB21 PB23 PB25 PB27 PB9 PB11

J17

1 2 3 4 5 6 7 8

9 10 11 12 13 15 17 19 21 22 23 24 25 26 27 28 29 30

HDR_2x15_ SMT

AT91SAM9M10-G 45-EK

LCD & ISI & VIDEO INTERFACE

This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.

PA20 PB31 PB29

14

PB30

16

PB28

18

PB20

20

PB22 PB24 PB26 PB8 PB10

2

PD13 {3}

A

REV DATE

MODIF.

1/1

DES.

REV DATE

SCALE

08-apr-10PPA2

08-apr-10PPA2 05-Feb-10

05-Feb-10

DATE

1

11-FEB-10Derek PP

VER.

REV. SHEET

12

A2

12

8.1 Revision History

Table 8-1.

Document Comments

Main edits:

- Most Figures updated

- Hyperlinks to PDFs updated

- ‘Serial Synchronous Controller (SSC)’ removed

- ‘JTAG’ added

6495B

6495A First issue.

- ‘RJ45 crossed cable’ added

- Dimensions updated

- Most configuration tables (with LEDs, pins and connectors) updated

- ‘LG/Philips’ reference removed

Figure 4-4, ” EBI1 - DDR2 + Flash” and new Schematics in Section 7.1

New

”Schematics”

Section 8

Revision History

Change Request Ref.

6990

7169

AT91SAM9M10-G45-EK User Guide 8-1

6495B–ATARM–21-Apr-10

Headquarters International

Atmel Corporation

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Product Contact

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Literature Requests

www.atmel.com/literature

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Technical Support

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Atmel Japan

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Sales Contact

www.atmel.com/contacts

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

™

and others are trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

6495B–ATARM–21-Apr-10

Atmel AT91SAM9M10-G45-EK User guide

Specifications and Main Features

Frequently Asked Questions

User Manual

1.1 Scope

Section 1

Introduction

1.2 Applicable Documents

2.1 Deliverables

Section 2

Kit Contents

2.2 Evaluation Board Specifications

2.3 Electrostatic Warning

3.1 Power Up the Board

3.2 Battery

Section 3

Power up

3.3 DevStart

3.4 Recovery Procedure

3.5 Sample Code and Technical Support

4.1 Equipment on the Board

Section 4

Board Description

4.1.1 Interfaces

4.1.2 Board Interface Connection

4.1.3 Push Button Switches

4.1.4 Display LCD and LEDs

4.2 Hardware Layout and Configuration

4.2.1 Processor

4.2.2 Clock Circuitry

4.2.3 Reset Circuitry

4.2.4 Memory

4.2.5 Power Supplies

4.2.6 Debug Interface

4.2.7 Audio Stereo Interface

4.2.8 TV-Out Extension

4.2.9 Software Controlled LEDs

4.2.10 Serial Peripheral Interface Controller (SPI)

4.2.11 Two Wire Interface (TWI)

4.2.12 SD/MMC Interface

4.2.13 TFT LCD with Touch Panel

4.2.14 Push Buttons

4.2.15 Expansion Slot

5.1 JTAG/ICE Configuration

5.2 ETHERNET Configuration

Section 5

Configuration

5.3 Jumpers Configuration

5.4 Miscellaneous Configuration Items

5.5 PIO Configuration

5.5.1 Peripheral Signals Multiplexing on I/O Lines

5.5.2 Multiplexing on PIO Controller A (PIOA)

5.5.3 Multiplexing on PIO Controller B (PIOB)

5.5.4 Multiplexing on PIO Controller C (PIOC)

5.5.5 Multiplexing on PIO Controller D (PIOD)

5.5.6 Multiplexing on PIO Controller E (PIOE)

6.1 Power Supply

Section 6

Connectors

6.2 RS232 Connector with RTS/CTS Handshake Support

6.3 DBGU

6.4 Ethernet

6.5 USB Host

6.6 USB Host/Device

6.7 JTAG Debugging Connector

6.8 SD/MMC- MCI0

6.9 SD/MMC- MCI1

6.10 AC97

6.11 Image Sensor - ISI

6.12 Video

6.13 Display Devices

6.13.1 TFT LCD

6.14 LCD Extension

7.1 Schematics

Section 7

Schematics

8.1 Revision History

Section 8

Revision History