Datasheet AT91SAM7SE512, AT91SAM7SE256, AT91SAM7SE32 Datasheet (ATMEL)

Download

Features

• Incorporates the ARM7TDMI

– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – EmbeddedICE

• Internal High-speed Flash

– 512 Kbytes, Organized in Two Contiguous Banks of 1024 Pages of 256 Bytes Dual

Plane (AT91SAM7SE512)

– 256 Kbytes (AT91SAM7SE256) Organized in One Bank of 1024 Pages of 256 Bytes

Single Plane (AT91SAM7SE256)

– 32 Kbytes (AT91SAM7SE32) Organized in One Bank of 256 Pages of 128 Bytes

Single Plane (AT91SAM7SE32) – Single Cycle Access at Up to 30 MHz in Worst Case Conditions – Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed – Page Programming Time: 6 ms, Including Page Auto-erase, Full Erase Time: 15 ms – 10,000 Erase Cycles, 10-year Data Retention Capability, Sector Lock Capabilities,

Flash Security Bit – Fast Flash Programming Interface for High Volume Production

• 32 Kbytes (AT91SAM7SE512/256) or 8 Kbytes (AT91SAM7SE32) of Internal

High-speed SRAM, Single-cycle Access at Maximum Speed

• One External Bus Interface (EBI)

– Supports SDRAM, Static Memory, Glueless Connection to CompactFlash® and

ECC-enabled NAND Flash

• Memory Controller (MC)

– Embedded Flash Controller – Memory Protection Unit – Abort Status and Misalignment Detection

• Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout

Detector – Provides External Reset Signal Shaping and Reset Source Status

• Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and One PLL

• Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and

Idle Mode – Three Programmable External Clock Signals

• Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources – Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

• Debug Unit (DBGU)

– Two-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

• Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

• Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter – Provides Reset or Interrupt Signals to the System

™

In-circuit Emulation, Debug Communication Channel Support

ARM® Thumb® Processor

AT91 ARM Thumb-based Microcontrollers

AT91SAM7SE512 AT91SAM7SE256 AT91SAM7SE32

Preliminary

6222B–ATARM–26-Mar-07

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

• Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm – Runs Off the Internal RC Oscillator

• Three Parallel Input/Output Controllers (PIO)

– Eighty-eight Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os – Input Change Interrupt Capability on Each I/O Line – Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output – Schmitt Trigger on All inputs

• Eleven Peripheral DMA Controller (PDC) Channels

• One USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, Eight Endpoints, 2688-byte Configurable Integrated FIFOs

• One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter – I²S Analog Interface Support, Time Division Multiplex Support – High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

• Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation – Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support – Full Modem Line Support on USART1

• One Master/Slave Serial Peripheral Interfaces (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

• One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel – Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

• One Four-channel 16-bit PWM Controller (PWMC)

• One Two-wire Interface (TWI)

– Master, Multi-Master and Slave Mode Support, All Two-wire Atmel EEPROMs Supported – General Call Supported in Slave Mode

• One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

• SAM-BA

• IEEE

™

– Default Boot program – Interface with SAM-BA Graphic User Interface

1149.1 JTAG Boundary Scan on All Digital Pins

• Four High-current Drive I/O lines, Up to 16 mA Each

• Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components – 1.8V or 3,3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply – 1.8V VDDCORE Core Power Supply with Brownout Detector

• Fully Static Operation:

– Up to 55 MHz at 1.8V and 85°C Worst Case Conditions – Up to 48 MHz at 1.65V and 85°C Worst Case Conditions

• Available in a 128-lead LQFP Green Package, or a 144-ball LFBGA RoHS-compliant Package

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

1. Description

AT91SAM7SE512/256/32 Preliminary

Atmel's AT91SAM7SE Series is a member of its Smart ARM Microcontroller family based on the 32-bit ARM7

• AT91SAM7SE512 features a 512 Kbyte high-speed Flash and a 32 Kbyte SRAM.

• AT91SAM7SE256 features a 256 Kbyte high-speed Flash and a 32 Kbyte SRAM.

• AT91SAM7SE32 features a 32 Kbyte high-speed Flash and an 8 Kbyte SRAM.

It also embeds a large set of peripherals, including a USB 2.0 device, an External Bus Interface (EBI), and a complete set of system functions minimizing the number of external components.

The EBI incorporates controllers for synchronous DRAM (SDRAM) and Static memories and features specific circuitry facilitating the interface for NAND Flash, SmartMedia and CompactFlash.

The device is an ideal migration path for 8/16-bit microcontroller users looking for additional performance, extended memory and higher levels of system integration.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via a parallel interface on a production programmer prior to mounting. Built-in lock bits and a security bit protect the firmware from accidental overwrite and preserve its confidentiality.

™

RISC processor and high-speed Flash memory.

The AT91SAM7SE Series system controller includes a reset controller capable of managing the power-on sequence of the microcontroller and the complete system. Correct device operation can be monitored by a built-in brownout detector and a watchdog running off an integrated RC oscillator.

By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of peripheral functions, including USART, SPI, External Bus Interface, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the AT91SAM7SE512/256/32 is a powerful device that provides a flexible, cost-effective solution to many embedded control applications.

1.1 Configuration Summary of the AT91SAM7SE512, AT91SAM7SE256 and AT91SAM7SE32

The AT91SAM7SE512, AT91SAM7SE256 and AT91SAM7SE32 differ in memory sizes and organization. Table 1-1 below summarizes the configurations for the three devices.

Table 1-1. Configuration Summary

Device Flash Size Flash Organization RAM Size

AT91SAM7SE512 512K bytes dual plane 32K bytes

AT91SAM7SE256 256K bytes single plane 32K bytes

AT91SAM7SE32 32K bytes single plane 8K bytes

6222B–ATARM–26-Mar-07

2. Block Diagram

Figure 2-1. AT91SAM7SE512/256/32 Block Diagram Signal Description

TDO TMS TCK

JTAGSEL

TST

IRQ0-IRQ1

DRXD

DTXD

PCK0-PCK2

PLLRC

XOUT

VDDFLASH

VDDCORE

NRST

RXD0

TXD0

SCK0

RTS0 CTS0

RXD1

TXD1

SCK1

RTS1

CTS1 DCD1 DSR1 DTR1

NPCS0 NPCS1 NPCS2 NPCS3

MISO

MOSI SPCK

TCLK0 TCLK1 TCLK2

TIOA0 TIOB0 TIOA1 TIOB1 TIOA2 TIOB2

ADTRG

AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7

ADVREF

TDI

FIQ

XIN

RI1

JTAG

SCAN

System Controller

PIO

DBGU

PLL

OSC

RCOSC

BOD

Controller

POR

PIT

WDT

RTT

PIOA

PIOB

PIO

AIC

PDC PDC

PMC

Reset

PIOC

ICE

USART0

USART1

SPI

Timer Counter

TC0

TC1

TC2

ADC

ARM7TDMI

Processor

Memory Controller

Embedded

Flash

Controller

Abort

Status

Memory Protection

Peripheral Bridge

Peripheral DMA

Controller

11 Channels

APB

PDC

PDC PDC

PDC

Address Decoder

Misalignment

Detection

Unit

CompactFlash

NAND Flash

SDRAM

Controller

Static Memory

Controller

ECC

Controller

FIFO

USB Device

PWMC

PDC

SRAM

32 Kbytes (SE512/256)

8 Kbytes (SE32)

Flash

512 Kbytes (SE512) 256 Kbytes (SE256)

32 Kbytes (SE32)

ROM

Fast Flash

Programming

Interface

SAM-BA

EBI

SSC

TWI

1.8V

Voltage

Regulator

VDDIN GND VDDOUT

VDDCORE VDDIO

VDDFLASH

ERASE

PGMRDY PGMNVALID PGMNOE PGMCK PGMM0-PGMM3 PGMD0-PGMD15 PGMNCMD PGMEN0-PGMEN1

D[31:0] A0/NBS0 A1/NBS2 A[15:2], A[20:18] A21/NANDALE A22/REG/NANDCLE A16/BA0 A17/BA1 NCS0 NCS1/SDCS NCS2/CFCS1 NCS3/NANDCS NRD/CFOE NWR0/NWE/CFWE

PIO

NWR1/NBS1/CFIOR NBS3/CFIOW SDCKE RAS CAS SDWE SDA10 CFRNW NCS4/CFCS0 NCS5/CFCE1 NCS6/CFCE2 NCS7 NANDOE NANDWE NWAIT

SDCK

DDM

PIO

DDP

PWM0 PWM1 PWM2 PWM3 TF TK TD RD RK RF

TWD TWCK

Transciever

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

3. Signal Description

Table 3-1. Signal Description List

Active

Signal Name Function Type

Power

VDDIN

VDDOUT Voltage Regulator Output Power 1.85V VDDFLASH Flash and USB Power Supply Power 3V to 3.6V VDDIO I/O Lines Power Supply Power 3V to 3.6V or 1.65V to 1.95V VDDCORE Core Power Supply Power 1.65V to 1.95V VDDPLL PLL Power 1.65V to 1.95V GND Ground Ground

XIN Main Oscillator Input Input XOUT Main Oscillator Output Output PLLRC PLL Filter Input PCK0 - PCK2 Programmable Clock Output Output

TCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor. TDO Test Data Out Output TMS Test Mode Select Input No pull-up resistor. JTAGSEL JTAG Selection Input Pull-down resistor.

ERASE

NRST Microcontroller Reset I/O Low Pull-Up resistor TST Test Mode Select Input High Pull-down resistor

DRXD Debug Receive Data Input DTXD Debug Transmit Data Output

IRQ0 - IRQ1 External Interrupt Inputs Input FIQ Fast Interrupt Input Input

Voltage Regulator and ADC Power Supply Input

Clocks, Oscillators and PLLs

ICE and JTAG

Flash Memory

Flash and NVM Configuration Bits Erase Command

Reset/Test

Debug Unit

Power 3V to 3.6V

Input High Pull-down resistor

AIC

Level Comments

6222B–ATARM–26-Mar-07

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

PIO

PA0 - PA31 Parallel IO Controller A I/O Pulled-up input at reset PB0 - PB31 Parallel IO Controller B I/O Pulled-up input at reset PC0 - PC23 Parallel IO Controller C I/O Pulled-up input at reset

USB Device Port

DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog

USART

SCK0 - SCK1 Serial Clock I/O TXD0 - TXD1 Transmit Data I/O RXD0 - RXD1 Receive Data Input RTS0 - RTS1 Request To Send Output CTS0 - CTS1 Clear To Send Input DCD1 Data Carrier Detect Input DTR1 Data Terminal Ready Output DSR1 Data Set Ready Input RI1 Ring Indicator Input

Synchronous Serial Controller

TD Transmit Data Output RD Receive Data Input TK Transmit Clock I/O RK Receive Clock I/O TF Transmit Frame Sync I/O RF Receive Frame Sync I/O

Timer/Counter

TCLK0 - TCLK2 External Clock Inputs Input TIOA0 - TIOA2 Timer Counter I/O Line A I/O TIOB0 - TIOB2 Timer Counter I/O Line B I/O

PWM Controller

PWM0 - PWM3 PWM Channels Output

Serial Peripheral Interface

MISO Master In Slave Out I/O MOSI Master Out Slave In I/O SPCK SPI Serial Clock I/O NPCS0 SPI Peripheral Chip Select 0 I/O Low NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low

Level Comments

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

Two-Wire Interface

TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O

Analog-to-Digital Converter

AD0-AD3 Analog Inputs Analog Analog Inputs AD4-AD7 Analog Inputs Analog Digital pulled-up inputs at reset ADTRG ADC Trigger Input ADVREF ADC Reference Analog

Fast Flash Programming Interface

PGMEN0-PGMEN2 Programming Enabling Input PGMM0-PGMM3 Programming Mode Input PGMD0-PGMD15 Programming Data I/O PGMRDY Programming Ready Output High PGMNVALID Data Direction Output Low PGMNOE Programming Read Input Low PGMCK Programming Clock Input PGMNCMD Programming Command Input Low

External Bus Interface

D[31:0] Data Bus I/O A[22:0] Address Bus Output NWAIT External Wait Signal Input Low

Static Memory Controller

NCS[7:0] Chip Select Lines Output Low NWR[1:0] Write Signals Output Low NRD Read Signal Output Low NWE Write Enable Output Low NUB NUB: Upper Byte Select Output Low NLB NLB: Lower Byte Select Output Low

EBI for CompactFlash Support

CFCE[2:1] CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash I/O Read Signal Output Low CFIOW CompactFlash I/O Write Signal Output Low CFRNW CompactFlash Read Not Write Signal Output CFCS[1:0] CompactFlash Chip Select Lines Output Low

Level Comments

6222B–ATARM–26-Mar-07

Table 3-1. Signal Description List (Continued)

Active

Signal Name Function Type

EBI for NAND Flash Support

NANDCS NAND Flash Chip Select Line Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDCLE NAND Flash Command Line Enable Output Low NANDALE NAND Flash Address Line Enable Output Low

SDRAM Controller

SDCK SDRAM Clock Output Tied low after reset SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Line Output Low BA[1:0] Bank Select Output SDWE SDRAM Write Enable Output Low RAS - CAS Row and Column Signal Output Low NBS[3:0] Byte Mask Signals Output Low SDA10 SDRAM Address 10 Line Output

Level Comments

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

4. Package

The AT91SAM7SE512/256/32 is available in:

• 20 x 14 mm 128-lead LQFP package with a 0.5 mm lead pitch.

• 10x 10 x 1.4 mm 144-ball LFBGA package with a 0.8 mm lead pitch

4.1 128-lead LQFP Package Outline

Figure 4-1 shows the orientation of the 128-lead LQFP package and a detailed mechanical

description is given in the Mechanical Characteristics section of the full datasheet.

Figure 4-1. 128-lead LQFP Package Outline (Top View)

103

128

102

6222B–ATARM–26-Mar-07

4.2 128-lead LQFP Pinout

Table 4-1. Pinout in 128-lead LQFP Package

1 ADVREF 33 PB31 65 TDI 97 SDCK

2 GND 34 PB30 66 TDO 98 PC8

3 AD7 35 PB29 67 PB2 99 PC7

4 AD6 36 PB28 68 PB1 100 PC6

5 AD5 37 PB27 69 PB0 101 PC5

6 AD4 38 PB26 70 GND 102 PC4

7 VDDOUT 39 PB25 71 VDDIO 103 PC3

8 VDDIN 40 PB24 72 VDDCORE 104 PC2

9 PA20/PGMD8/AD3 41 PB23 73 NRST 105 PC1

10 PA19/PGMD7/AD2 42 PB22 74 TST 106 PC0

11 PA18/PGMD6/AD1 43 PB21 75 ERASE 107 PA31

12 PA17/PGMD5/AD0 44 PB20 76 TCK 108 PA30

13 PA16/PGMD4 45 GND 77 TMS 109 PA29

14 PA15/PGMD3 46 VDDIO 78 JTAGSEL 110 PA28

15 PA14/PGMD2 47 VDDCORE 79 PC23 111 PA27/PGMD15

16 PA13/PGMD1 48 PB19 80 PC22 112 PA26/PGMD14

17 PA12/PGMD0 49 PB18 81 PC21 113 PA25/PGMD13

18 PA11/PGMM3 50 PB17 82 PC20 114 PA24/PGMD12

19 PA10/PGMM2 51 PB16 83 PC19 115 PA23/PGMD11

20 PA9/PGMM1 52 PB15 84 PC18 116 PA22/PGMD10

21 VDDIO 53 PB14 85 PC17 117 PA21/PGMD9

22 GND 54 PB13 86 PC16 118 VDDCORE

23 VDDCORE 55 PB12 87 PC15 119 GND

24 PA8/PGMM0 56 PB11 88 PC14 120 VDDIO

25 PA7/PGMNVALID 57 PB10 89 PC13 121 DM

26 PA6/PGMNOE 58 PB9 90 PC12 122 DP

27 PA5/PGMRDY 59 PB8 91 PC11 123 VDDFLASH

28 PA4/PGMNCMD 60 PB7 92 PC10 124 GND

29 PA3 61 PB6 93 PC9 125 XIN/PGMCK

30 PA2/PGMEN2 62 PB5 94 GND 126 XOUT

31 PA1/PGMEN1 63 PB4 95 VDDIO 127 PLLRC

32 PA0/PGMEN0 64 PB3 96 VDDCORE 128 VDDPLL

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

4.3 144-ball LFBGA Package Outline

Figure 4-2 shows the orientation of the 144-ball LFBGA package and a detailed mechanical

description is given in the Mechanical Characteristics section.

Figure 4-2. 144-ball LFBGA Package Outline (Top View)

AT91SAM7SE512/256/32 Preliminary

12 11 10

9 8 7 6 5 4 3 2 1

Ball A1

ABCDEFGHJKLM

6222B–ATARM–26-Mar-07

4.4 144-ball LFBGA Pinout

Table 4-2. SAM7SE512/256/32 Pinout for 144-ball LFBGA Package

Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name

A1 PB7 D1 VDDCORE G1 PC18 K1 PC11

A2 PB8 D2 VDDCORE G2 PC16 K2 PC6

A3 PB9 D3 PB2 G3 PC17 K3 PC2

A4 PB12 D4 TDO G4 PC9 K4 PC0

A5 PB13 D5 TDI G5 VDDIO K5 PA27/PGMD15

A6 PB16 D6 PB17 G6 GND K6 PA26/PGMD14

A7 PB22 D7 PB26 G7 GND K7 GND

A8 PB23 D8 PA14/PGMD2 G8 GND K8 VDDCORE

A9 PB25 D9 PA12/PGMD0 G9 GND K9 VDDFLASH

A10 PB29 D10 PA11/PGMM3 G10 AD4 K10 VDDIO

A11 PB30 D11 PA8/PGMM0 G11 VDDIN K11 VDDIO

A12 PB31 D12 PA7/PGMNVALID G12 VDDOUT K12 PA18/PGMD6/AD1

B1 PB6 E1 PC22 H1 PC15 L1 SDCK

B2 PB3 E2 PC23 H2 PC14 L2 PC7

B3 PB4 E3 NRST H3 PC13 L3 PC4

B4 PB10 E4 TCK H4 VDDCORE L4 PC1

B5 PB14 E5 ERASE H5 VDDCORE L5 PA29

B6 PB18 E6 TEST H6 GND L6 PA24/PGMD12

B7 PB20 E7 VDDCORE H7 GND L7 PA21/PGMD9

B8 PB24 E8 VDDCORE H8 GND L8 ADVREF

B9 PB28 E9 GND H9 GND L9 VDDFLASH

B10 PA4/PGMNCMD E10 PA9/PGMM1 H10 PA19/PGMD7/AD2 L10 VDDFLASH

B11 PA0/PGMEN0 E11 PA10/PGMM2 H11 PA20/PGMD8/AD3 L11 PA17/PGMD5/AD0

B12 PA1/PGMEN1 E12 PA13/PGMD1 H12 VDDIO L12 GND

C1 PB0 F1 PC21 J1 PC12 M1 PC8

C2 PB1 F2 PC20 J2 PC10 M2 PC5

C3 PB5 F3 PC19 J3 PA30 M3 PC3

C4 PB11 F4 JTAGSEL J4 PA28 M4 PA31

C5 PB15 F5 TMS J5 PA23/PGMD11 M5 PA25/PGMD13

C6 PB19 F6 VDDIO J6 PA22/PGMD10 M6 DM

C7 PB21 F7 GND J7 AD6 M7 DP

C8 PB27 F8 GND J8 AD7 M8 GND

C9 PA6/PGMNOE F9 GND J9 VDDCORE M9 XIN/PGMCK

C10 PA5/PGMRDY F10 AD5 J10 VDDCORE M10 XOUT

C11 PA2/PGMEN2 F11 PA15/PGMD3 J11 VDDCORE M11 PLLRC

C12 PA3 F12 PA16/PGMD4 J12 VDDIO M12 VDDPLL

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

5. Power Considerations

5.1 Power Supplies

The AT91SAM7SE512/256/32 has six types of power supply pins and integrates a voltage regulator, allowing the device to be supplied with only one voltage. The six power supply pin types are:

• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,

3.3V nominal.

• VDDOUT pin. It is the output of the 1.8V voltage regulator.

• VDDIO pin. It powers the I/O lines; two voltage ranges are supported: – from 3.0V to 3.6V, 3.3V nominal – or from 1.65V to 1.95V, 1.8V nominal.

• VDDFLASH pin. It powers the USB transceivers and a part of the Flash. It is required for the

Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,

1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE is required for the device, including its embedded Flash, to operate correctly.

• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the

VDDOUT pin.

In order to decrease current consumption, if the voltage regulator and the ADC are not used, VDDIN, ADVREF, AD4, AD5, AD6 and AD7 should be connected to GND. In this case VDDOUT should be left unconnected.

AT91SAM7SE512/256/32 Preliminary

No separate ground pins are provided for the different power supplies. Only GND pins are provided and should be connected as shortly as possible to the system ground plane.

5.2 Power Consumption

The AT91SAM7SE512/256/32 has a static current of less than 60 µA on VDDCORE at 25°C, including the RC oscillator, the voltage regulator and the power-on reset when the brownout detector is deactivated. Activating the brownout detector adds 20 µA static current.

The dynamic power consumption on VDDCORE is less than 80 mA at full speed when running out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not exceed 10 mA.

5.3 Voltage Regulator

The AT91SAM7SE512/256/32 embeds a voltage regulator that is managed by the System Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100 mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 20 µA static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscillations. The best way to achieve this is to use two capacitors in parallel:

6222B–ATARM–26-Mar-07

• One external 470 pF (or 1 nF) NPO capacitor should be connected between VDDOUT and

GND as close to the chip as possible.

• One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT and

GND.

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability and reduce source voltage drop. The input decoupling capacitor should be placed close to the chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

5.4 Typical Powering Schematics

The AT91SAM7SE512/256/32 supports a 3.3V single supply mode. The internal regulator input connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 5-1 shows the power schematics to be used for USB bus-powered systems.

Figure 5-1. 3.3V System Single Power Supply Schematic

VDDFLASH

Power Source

ranges

from 4.5V (USB)

to 18V

DC/DC Converter

3.3V

VDDIO

VDDIN

VDDOUT

VDDCORE

VDDPLL

Voltage

Regulator

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

6. I/O Lines Considerations

6.1 JTAG Port Pins

TMS, TDI and TCK are Schmitt trigger inputs. TMS, TDI and TCK do not integrate a pull-up resistor.

TDO is an output, driven at up to VDDIO, and has no pull-up resistor.

The pin JTAGSEL is used to select the JTAG boundary scan when asserted at a high level. The pin JTAGSEL integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

6.2 Test Pin

The TST pin is used for manufacturing test or fast programming mode of the AT91SAM7SE512/256/32 when asserted high. The TST pin integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for normal operations.

To enter fast programming mode, the TST pin and the PA0 and PA1 pins should be tied high and PA2 tied low.

Driving the TST pin at a high level while PA0 or PA1 is driven at 0 leads to unpredictable results.

AT91SAM7SE512/256/32 Preliminary

6.3 Reset Pin

6.4 ERASE Pin

The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal to the external components or asserted low externally to reset the microcontroller. There is no constraint on the length of the reset pulse, and the reset controller can guarantee a minimum pulse length. This allows connection of a simple push-button on the NRST pin as system user reset, and the use of the NRST signal to reset all the components of the system.

An external power-on reset can drive this pin during the start-up instead of using the internal power-on reset circuit.

The NRST pin integrates a permanent pull-up of about 100 kΩ resistor to VDDIO.

This pin has Schmitt trigger input.

The ERASE pin is used to re-initialize the Flash content and some of its NVM bits. It integrates a permanent pull-down resistor of about 15 kΩ to GND, so that it can be left unconnected for nor- mal operations.

This pin is debounced by the RC oscillator to improve the glitch tolerance. When the pin is tied to high during less than 100 ms, ERASE pin is not taken into account. The pin must be tied high during more than 220 ms to perform the re-initialization of the Flash.

6.5 SDCK Pin

6222B–ATARM–26-Mar-07

The SDCK pin is dedicated to the SDRAM Clock and is an output-only without pull-up. Maximum Output Frequency of this pad is 48 MHz at 3.0V and 25 MHz at 1.65V with a maximum load of 30 pF.

6.6 PIO Controller lines

All the I/O lines PA0 to PA31, PB0 to PB31, PC0 to PC23 integrate a programmable pull-up resistor. Programming of this pull-up resistor is performed independently for each I/O line through the PIO controllers.

Typical pull-up value is 100 kΩ.

All the I/O lines have schmitt trigger inputs.

6.7 I/O Lines Current Drawing

The PIO lines PA0 to PA3 are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently.

The remaining I/O lines can draw only 8 mA.

However, the total current drawn by all the I/O lines cannot exceed 300 mA.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

7. Processor and Architecture

7.1 ARM7TDMI Processor

• RISC processor based on ARMv4T Von Neumann architecture – Runs at up to 55 MHz, providing 0.9 MIPS/MHz (core supplied with 1.8V)

• Two instruction sets –ARM –Thumb

• Three-stage pipeline architecture – Instruction Fetch (F) – Instruction – Execute (E)

7.2 Debug and Test Features

• EmbeddedICE™ (Integrated embedded in-circuit emulator) – Two watchpoint units – Test access port accessible through a JTAG protocol – Debug communication channel

• Debug Unit –Two-pin UART – Debug communication channel interrupt handling – Chip ID Register

• IEEE1149.1 JTAG Boundary-scan on all digital pins

high-performance 32-bit instruction set

high code density 16-bit instruction set

Decode (D)

AT91SAM7SE512/256/32 Preliminary

7.3 Memory Controller

• Programmable Bus Arbiter

• Address decoder provides selection signals for

• Abort Status Registers

• Misalignment Detector

• Remap Command

• 16-area Memory Protection Unit (Internal Memory and peripheral protection only)

– Handles requests from the ARM7TDMI and the Peripheral DMA Controller

– Four internal 1 Mbyte memory areas – One 256-Mbyte embedded peripheral area – Eight external 256-Mbyte memory areas

– Source, Type and all parameters of the access leading to an abort are saved – Facilitates debug by detection of bad pointers

– Alignment checking of all data accesses – Abort generation in case of misalignment

– Remaps the SRAM in place of the embedded non-volatile memory – Allows handling of dynamic exception vectors

6222B–ATARM–26-Mar-07

– Individually programmable size between 1K Byte and 1M Byte – Individually programmable protection against write and/or user access – Peripheral protection against write and/or user access

• Embedded Flash Controller – Embedded Flash interface, up to three programmable wait states – Prefetch buffer, buffering and anticipating the 16-bit requests, reducing the required

wait states – Key-protected program, erase and lock/unlock sequencer – Single command for erasing, programming and locking operations – Interrupt generation in case of forbidden operation

7.4 External Bus Interface

• Integrates Three External Memory Controllers: – Static Memory Controller – SDRAM Controller – ECC Controller

• Additional Logic for NAND Flash and CompactFlash – NAND Flash support: 8-bit as well as 16-bit devices are supported – CompactFlash support: all modes (Attribute Memory, Common Memory, I/O, True

IDE) are supported but the signals _IOIS16 (I/O and True IDE modes) and -ATA SEL (True IDE mode) are not handled.

• Optimized External Bus: – 16- or 32-bit Data Bus (32-bit Data Bus for SDRAM only) – Up to 23-bit Address Bus, Up to 8-Mbytes Addressable – Up to 8 Chip Selects, each reserved to one of the eight Memory Areas – Optimized pin multiplexing to reduce latencies on External Memories

• Configurable Chip Select Assignment: – Static Memory Controller on NCS0 – SDRAM Controller or Static Memory Controller on NCS1 – Static Memory Controller on NCS2, Optional CompactFlash Support – Static Memory Controller on NCS3, NCS5 - NCS6, Optional NAND Flash Support – Static Memory Controller on NCS4, Optional CompactFlash Support – Static Memory Controller on NCS7

Support

7.5 Static Memory Controller

• External memory mapping, 512-Mbyte address space

• 8-, or 16-bit Data Bus

• Up to 8 Chip Select Lines

• Multiple Access Modes supported – Byte Write or Byte Select Lines – Two different Read Protocols for each Memory Bank

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

• Multiple device adaptability

• Multiple Wait State Management

7.6 SDRAM Controller

• Numerous configurations supported

• Programming facilities

• Energy-saving capabilities

• Error detection

• SDRAM Power-up Initialization by software

• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)

• Auto Precharge Command not used

• Mobile SDRAM supported (except for low-power extended mode and deep power-down mode)

AT91SAM7SE512/256/32 Preliminary

– Compliant with LCD Module – Compliant with PSRAM in synchronous operations – Programmable Setup Time Read/Write – Programmable Hold Time Read/Write

– Programmable Wait State Generation – External Wait Request – Programmable Data Float Time

– 2K, 4K, 8K Row Address Memory Parts – SDRAM with two or four Internal Banks – SDRAM with 16- or 32-bit Data Path

– Word, half-word, byte access – Automatic page break when Memory Boundary has been reached – Multibank Ping-pong Access – Timing parameters specified by software – Automatic refresh operation, refresh rate is programmable

– Self-refresh, and Low-power Modes supported

– Refresh Error Interrupt

7.7 Error Corrected Code Controller

• Tracking the accesses to a NAND Flash device by triggering on the corresponding chip select

• Single bit error correction and 2-bit Random detection.

• Automatic Hamming Code Calculation while writing – ECC value available in a register

• Automatic Hamming Code Calculation while reading – Error Report, including error flag, correctable error flag and word address being

detected erroneous

– Supports 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-byte

pages

6222B–ATARM–26-Mar-07

7.8 Peripheral DMA Controller

• Handles data transfer between peripherals and memories

• Eleven channels – Two for each USART – Two for the Debug Unit – Two for the Serial Synchronous Controller – Two for the Serial Peripheral Interface – One for the Analog-to-digital Converter

• Low bus arbitration overhead – One Master Clock cycle needed for a transfer from memory to peripheral – Two Master Clock cycles needed for a transfer from peripheral to memory

• Next Pointer management for reducing interrupt latency requirements

• Peripheral DMA Controller (PDC) priority is as follows (from the highest priority to the lowest):

Receive DBGU

Receive USART0

Receive USART1

Receive SSC

Receive ADC

Receive SPI

Tr an s m it D B GU

Transmit USART0

Transmit USART1

Transmit SSC

Transmit SPI

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

8. Memories

AT91SAM7SE512/256/32 Preliminary

• 512 Kbytes of Flash Memory (AT91SAM7SE512) – dual plane – two contiguous banks of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 write cycles, 10-year data retention capability – 32 lock bits, each protecting 32 lock regions of 64 pages – Protection Mode to secure contents of the Flash

• 256 Kbytes of Flash Memory (AT91SAM7SE256) – single plane – one bank of 1024 pages of 256 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 cycles, 10-year data retention capability – 16 lock bits, each protecting 16 lock regions of 64 pages – Protection Mode to secure contents of the Flash

• 32 Kbytes of Flash Memory (AT91SAM7SE32) – single plane – one bank of 256 pages of 128 bytes – Fast access time, 30 MHz single-cycle access in Worst Case conditions – Page programming time: 6 ms, including page auto-erase – Page programming without auto-erase: 3 ms – Full chip erase time: 15 ms – 10,000 cycles, 10-year data retention capability – 8 lock bits, each protecting 8 lock regions of 32 pages – Protection Mode to secure contents of the Flash

• 32 Kbytes of Fast SRAM (AT91SAM7SE512/256) – Single-cycle access at full speed

• 8 Kbytes of Fast SRAM (AT91SAM7SE32) – Single-cycle access at full speed

6222B–ATARM–26-Mar-07

Figure 8-1. AT91SAM7SE Memory Mapping

Address Memory Space Internal Memory Mapping

0x0000 0000

0x0FFF FFFF

0x1000 0000

0x1FFF FFFF

0x2000 0000

0x2FFF FFFF

0x3000 0000

0x3FFF FFFF

0x4000 0000

0x4FFF FFFF

0x5000 0000

0x5FFF FFFF

0x6000 0000

0x6FFF FFFF

0x7000 0000

0x7FFF FFFF

0x8000 0000

0x8FFF FFFF

0x9000 0000

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

Internal Memories

EBI

Chip Select 0

SMC

EBI

Chip Select 1/

SMC or SDRAMC

EBI

Chip Select 2

SMC

EBI

Chip Select 3

SMC/NANDFlash/

SmartMedia

EBI

Chip Select 4

SMC

Compact Flash

EBI

Chip Select 5

SMC

Compact Flash

EBI

Chip Select 6

EBI

Chip Select 7

Undefined

(Abort)

Internal Peripherals

256 MBytes

6 x 256 MBytes 1,536 MBytes

256 MBytes

0xF000 0000

0xFFF9 FFFF

0xFFFA 0000

0xFFFA 3FFF

0xFFFA 4000

0xFFFA FFFF

0xFFFB 0000

0xFFFB 3FFF

0xFFFB 4000

0xFFFB 7FFF

0xFFFB 8000

0xFFFB BFFF 0xFFFB C000

0xFFFB FFFF

0xFFFC 0000

0xFFFC 3FFF

0xFFFC 4000

0xFFFC 7FFF

0xFFFC 8000

0xFFFC BFFF

0xFFFC C000 0xFFFC FFFF

0xFFFD 0000

0xFFFD 3FFF

0xFFFD 4000

0xFFFD 7FFF

0xFFFD 8000

0xFFFD BFFF

0xFFFD C000 0xFFFD FFFF

0xFFFE 0000

0xFFFE 3FFF

0xFFFE 4000

0xFFFF EFFF 0xFFFF F000

0xFFFF FFFF

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

0x003F FFFF

0x0040 0000

0x0FFF FFFF

Peripheral Mapping

TC0, TC1, TC2

Boot Memory (1)

Flash before Remap

SRAM after Remap

Internal Flash

Internal SRAM

Internal ROM

Reserved

ReservedReserved

Reserved

UDP

Reserved

TWI

Reserved

USART0

USART1

ReservedReserved

PWMC

ReservedReserved

SSC

ADC

ReservedReserved

SPI

Reserved

SYSC

16 Kbytes

1 MBytes

252 MBytes

Note: (1) Can be ROM, Flash or SRAM

depending on GPNVM2 and REMAP

System Controller Mapping

0xFFFF F000

0xFFFF F1FF

0xFFFF F200

DBGU

0xFFFF F3FF

0xFFFF F400

PIOA

0xFFFF F5FF

0xFFFF F600

PIOB

0xFFFF F7FF

0xFFFF F800

PIOC

0xFFFF F9FF

0xFFFF FA00

Reserved

0xFFFF FBFF

0xFFFF FC00

0xFFFF FCFF

0xFFFF FD00

0xFFFF FD0F

0xFFFF FD20

0xFFFF FC2F

0xFFFF FD30

0xFFFF FC3F

0xFFFF FD40

0xFFFF FD4F

0xFFFF FD60

0xFFFF FC6F

0xFFFF FD70

0xFFFF FEFF

0xFFFF FF00

0xFFFF FFFF

PMC

RSTC

Reserved

WDT

Reserved

VREG

Reserved

AIC

RTT

PIT

512 Bytes/128 registers

256 Bytes/64 registers

16 Bytes/4 registers

4 Bytes/1 register

256 Bytes/64 registers

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

A first level of address decoding is performed by the Memory Controller, i.e., by the implementation of the Advanced System Bus (ASB) with additional features.

Decoding splits the 4G bytes of address space into 16 areas of 256M bytes. The areas 1 to 8 are directed to the EBI that associates these areas to the external chip selects NC0 to NCS7. The area 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1M byte of internal memory area. The area 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master requesting such an access.

8.1 Embedded Memories

8.1.1 Internal Memories

8.1.1.1 Internal SRAM

The AT91SAM7SE512/256 embeds a high-speed 32-Kbyte SRAM bank. The AT91SAM7SE32 embeds a high-speed 8-Kbyte SRAM bank. After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0020 0000. After Remap, the SRAM also becomes available at address 0x0.

AT91SAM7SE512/256/32 Preliminary

8.1.1.2 Internal ROM

8.1.1.3 Internal Flash

The AT91SAM7SE512/256/32 embeds an Internal ROM. At any time, the ROM is mapped at address 0x30 0000. The ROM contains the FFPI and the SAM-BA boot program.

• The AT91SAM7SE512 features two banks of 256 Kbytes of Flash.

• The AT91SAM7SE256 features one bank of 256 Kbytes of Flash.

• The AT91SAM7SE32 features one bank of 32 Kbytes of Flash.

At any time, the Flash is mapped to address 0x0010 0000.

A general purpose NVM (GPNVM) bit is used to boot either on the ROM (default) or from the Flash.

This GPNVM bit can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

Setting the GPNVM bit 2 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM bit 2 and thus selects the boot from the ROM by default.

6222B–ATARM–26-Mar-07

Figure 8-2. Internal Memory Mapping with GPNVM Bit 2 = 0 (default)

256M Bytes

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

0x003F FFFF 0x0040 0000

0x0FFF FFFF

ROM Before Remap

SRAM After Remap

Internal FLASH

Internal SRAM

Internal ROM

Undefined Areas

(Abort)

Figure 8-3. Internal Memory Mapping with GPNVM Bit 2 = 1

256M Bytes

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

0x003F FFFF 0x0040 0000

Flash Before Remap

SRAM After Remap

Internal FLASH

Internal SRAM

Internal ROM

Undefined Areas

(Abort)

1 M Bytes

252 M Bytes

1 M Bytes

252 M Bytes

8.1.2 Embedded Flash

8.1.2.1 Flash Overview

The Flash of the AT91SAM7SE512 is organized in two banks (dual plane) of 1024 pages of 256 bytes. It reads as 131,072 32-bit words.

The Flash of the AT91SAM7SE256 is organized in 1024 pages (single plane) of 256 bytes. It reads as 65,536 32-bit words.

The Flash of the AT91SAM7SE32 is organized in 256 pages (single plane) of 128 bytes. It reads as 32,768 32-bit words.

The Flash of the AT91SAM7SE32 contains a 128-byte write buffer, accessible through a 32-bit interface.

The Flash of the AT91SAM7SE512/256 contains a 256-byte write buffer, accessible through a 32-bit interface.

AT91SAM7SE512/256/32 Preliminary

0x0FFF FFFF

6222B–ATARM–26-Mar-07

The Flash benefits from the integration of a power reset cell and from the brownout detector. This prevents code corruption during power supply changes, even in the worst conditions.

8.1.2.2 Embedded Flash Controller

The Embedded Flash Controller (EFC) manages accesses performed by the masters of the system. It enables reading the Flash and writing the write buffer. It also contains a User Interface, mapped within the Memory Controller on the APB. The User Interface allows:

• programming of the access parameters of the Flash (number of wait states, timings, etc.)

• starting commands such as full erase, page erase, page program, NVM bit set, NVM bit

clear, etc.

• getting the end status of the last command

• getting error status

• programming interrupts on the end of the last commands or on errors

The Embedded Flash Controller also provides a dual 32-bit Prefetch Buffer that optimizes 16-bit access to the Flash. This is particularly efficient when the processor is running in Thumb mode.

• Two EFCs (EFC0 and EFC1) are embedded in the SAM7SE512 to control each plane of 256

KBytes. Dual plane organization allows concurrent Read and Program.

• One EFC (EFC0) is embedded in the SAM7SE256 to control the single plane 256 KBytes.

• One EFC (EFC0) is embedded in the SAM7SE32 to control the single plane 32 KBytes.

AT91SAM7SE512/256/32 Preliminary

8.1.2.3 Lock Regions

The AT91SAM7SE512 Embedded Flash Controller manages 32 lock bits to protect 32 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7SE512 contains 32 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

The AT91SAM7SE256 Embedded Flash Controller manages 16 lock bits to protect 16 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7SE256 contains 16 lock regions and each lock region contains 64 pages of 256 bytes. Each lock region has a size of 16 Kbytes.

The AT91SAM7SE32 Embedded Flash Controller manages 8 lock bits to protect 8 regions of the flash against inadvertent flash erasing or programming commands. The AT91SAM7SE32 contains 8 lock regions and each lock region contains 32 pages of 128 bytes. Each lock region has a size of 4 Kbytes.

If a locked-region’s erase or program command occurs, the command is aborted and the EFC trigs an interrupt.

The 32 (AT91SAM7SE512), 16 (AT91SAM7SE256) or 8 (AT91SAM7SE32) NVM bits are software programmable through the EFC User Interface. The command “Set Lock Bit” enables the protection. The command “Clear Lock Bit” unlocks the lock region.

Asserting the ERASE pin clears the lock bits, thus unlocking the entire Flash.

8.1.2.4 Security Bit Feature

The AT91SAM7SE512/256/32 features a security bit, based on a specific NVM-bit. When the security is enabled, any access to the Flash, either through the ICE interface or through the Fast Flash Programming Interface, is forbidden.

6222B–ATARM–26-Mar-07

The security bit can only be enabled through the Command “Set Security Bit” of the EFC User Interface. Disabling the security bit can only be achieved by asserting the ERASE pin at 1 and after a full flash erase is performed. When the security bit is deactivated, all accesses to the flash are permitted.

It is important to note that the assertion of the ERASE pin should always be longer than 200 ms.

As the ERASE pin integrates a permanent pull-down, it can be left unconnected during normal operation. However, it is safer to connect it directly to GND for the final application.

8.1.2.5 Non-volatile Brownout Detector Control

Two general purpose NVM (GPNVM) bits are used for controlling the brownout detector (BOD), so that even after a power loss, the brownout detector operations remain in their state.

These two GPNVM bits can be cleared or set respectively through the commands “Clear General-purpose NVM Bit” and “Set General-purpose NVM Bit” of the EFC User Interface.

• GPNVM bit 0 is used as a brownout detector enable bit. Setting the GPNVM bit 0 enables the

BOD, clearing it disables the BOD. Asserting ERASE clears the GPNVM bit 0 and thus disables the brownout detector by default.

• GPNVM bit 1 is used as a brownout reset enable signal for the reset controller. Setting the

GPNVM bit 1 enables the brownout reset when a brownout is detected, Clearing the GPNVM bit 1 disables the brownout reset. Asserting ERASE disables the brownout reset by default.

8.1.2.6 Calibration Bits

Sixteen NVM bits are used to calibrate the brownout detector and the voltage regulator. These bits are factory configured and cannot be changed by the user. The ERASE pin has no effect on the calibration bits.

8.1.3 Fast Flash Programming Interface

The Fast Flash Programming Interface allows programming the device through either a serial JTAG interface or through a multiplexed fully-handshaked parallel port. It allows gang-programming with market-standard industrial programmers.

The FFPI supports read, page program, page erase, full erase, lock, unlock and protect commands.

The Fast Flash Programming Interface is enabled and the Fast Programming Mode is entered when the TST pin and the PA0 and PA1 pins are all tied high and PA2 tied to low.

• The Flash of the AT91SAM7SE512 is organized in 2048 pages of 256 bytes (dual plane). It

reads as 131,072 32-bit words.

• The Flash of the AT91SAM7SE256 is organized in 1024 pages of 256 bytes (single plane). It

reads as 65,536 32-bit words.

• The Flash of the AT91SAM7SE32 is organized in 256 pages of 128 bytes (single plane). It

reads as 32,768 32-bit words.

• The Flash of the AT91SAM7SE512/256 contains a 256-byte write buffer, accessible through

a 32-bit interface.

• The Flash of the AT91SAM7SE32 contains a 128-byte write buffer, accessible through a 32-

bit interface.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

8.1.4 SAM-BA™ Boot

The SAM-BA Boot is a default Boot Program which provides an easy way to program in-situ the on-chip Flash memory.

The SAM-BA Boot Assistant supports serial communication via the DBGU or the USB Device Port.

• Communication via the DBGU supports a wide range of crystals from 3 to 20 MHz via

software auto-detection.

• Communication via the USB Device Port is limited to an 18.432 MHz crystal.

The SAM-BA Boot provides an interface with SAM-BA Graphic User Interface (GUI).

The SAM-BA Boot is in ROM and is mapped in Flash at address 0x0 when GPNVM bit 2 is set to

8.2 External Memories

The external memories are accessed through the External Bus Interface.

Refer to the memory map in Figure 8-1 on page 22.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

9. System Controller

The System Controller manages all vital blocks of the microcontroller: interrupts, clocks, power, time, debug and reset.

The System Controller peripherals are all mapped to the highest 4 Kbytes of address space, between addresses 0xFFFF F000 and 0xFFFF FFFF.

Figure 9-1 on page 29 shows the System Controller Block Diagram.

Figure 8-1 on page 22 shows the mapping of the User Interface of the System Controller periph-

erals. Note that the Memory Controller configuration user interface is also mapped within this address space.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

Figure 9-1. System Controller Block Diagram

NRST

irq0-irq1

periph_irq[2..18]

pit_irq

rtt_irq

wdt_irq

dbgu_irq

pmc_irq

rstc_irq

periph_nreset

dbgu_rxd

debug

periph_nreset

SLCK

periph_nreset

SLCK

debug

proc_nreset

cal gpnvm[0]

BOD

POR

SLCK

fiq

MCK

idle

flash_wrdis

power_on_reset

jtag_nreset

flash_poe

System Controller

Advanced

Interrupt

Controller

Debug

Unit

Periodic

Interval

Timer

Real-Time

Timer

Watchdog

Timer

gpnvm[1]

bod_rst_en

Reset

Controller

wdt_fault WDRPROC

int

dbgu_irq force_ntrst

dbgu_txd

pit_irq

rtt_irq

wdt_irq

periph_nreset proc_nreset

rstc_irq

Voltage

Regulator

Mode

Controller

jtag_nreset

nirq nfiq

proc_nreset

PCK

debug

power_on_reset

force_ntrst

security_bit

flash_poe

flash_wrdis

cal

gpnvm[0..2]

MCK

proc_nreset

standby

cal

Boundary Scan

TAP Controller

ARM7TDMI

Embedded

Flash

Memory

Controller

Voltage

Regulator

XIN

XOUT

PLLRC

PA0-PA31

PB0-PB31

PC0-PC29

RCOSC

OSC

PLL

periph_nreset usb_suspend

periph_clk[2-3]

MAINCK

PLLCK

dbgu_rxd

SLCK

int

Power

Management

Controller

PIO

Controller

periph_clk[2..18] pck[0-3]

PCK UDPCK MCK

pmc_irq

idle

periph_irq{2-3]periph_nreset irq0-irq1 fiq dbgu_txd

UDPCK

periph_clk[11]

periph_nreset

periph_irq[11]

usb_suspend

periph_clk[4..18]

periph_nreset

periph_irq[4..18]

out

enable

USB Device

Por t

Embedded Peripherals

6222B–ATARM–26-Mar-07

9.1 Reset Controller

• Based on one power-on reset cell and a double brownout detector

• Status of the last reset, either Power-up Reset, Software Reset, User Reset, Watchdog

Reset, Brownout Reset

• Controls the internal resets and the NRST pin output

• Allows to shape a signal on the NRST line, guaranteeing that the length of the pulse meets

any requirement.

9.1.1 Brownout Detector and Power On Reset

The AT91SAM7SE512/256/32 embeds one brownout detection circuit and a power-on reset cell. The power-on reset is supplied with and monitors VDDCORE.

Both signals are provided to the Flash to prevent any code corruption during power-up or powerdown sequences or if brownouts occur on the VDDCORE power supply.

The power-on reset cell has a limited-accuracy threshold at around 1.5V. Its output remains low during power-up until VDDCORE goes over this voltage level. This signal goes to the reset controller and allows a full re-initialization of the device.

The brownout detector monitors the VDDCORE and VDDFLASH levels during operation by comparing it to a fixed trigger level. It secures system operations in the most difficult environments and prevents code corruption in case of brownout on the VDDCORE or VDDFLASH.

When the brownout detector is enabled and VDDCORE decreases to a value below the trigger level (Vbot18-, defined as Vbot18 - hyst/2), the brownout output is immediately activated.

When VDDCORE increases above the trigger level (Vbot18+, defined as Vbot18 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDCORE threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 1.68V with an accuracy of ± 2% and is factory calibrated.

When the brownout detector is enabled and VDDFLASH decreases to a value below the trigger level (Vbot33-, defined as Vbot33 - hyst/2), the brownout output is immediately activated.

When VDDFLASH increases above the trigger level (Vbot33+, defined as Vbot33 + hyst/2), the reset is released. The brownout detector only detects a drop if the voltage on VDDCORE stays below the threshold voltage for longer than about 1µs.

The VDDFLASH threshold voltage has a hysteresis of about 50 mV, to ensure spike free brownout detection. The typical value of the brownout detector threshold is 2.80V with an accuracy of ± 3.5% and is factory calibrated.

The brownout detector is low-power, as it consumes less than 20 µA static current. However, it can be deactivated to save its static current. In this case, it consumes less than 1µA. The deactivation is configured through the GPNVM bit 0 of the Flash.

9.2 Clock Generator

The Clock Generator embeds one low-power RC Oscillator, one Main Oscillator and one PLL with the following characteristics:

• RC Oscillator ranges between 22 KHz and 42 KHz

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

• Main Oscillator frequency ranges between 3 and 20 MHz

• Main Oscillator can be bypassed

• PLL output ranges between 80 and 220 MHz

It provides SLCK, MAINCK and PLLCK.

Figure 9-2. Clock Generator Block Diagram

Clock Generator

9.3 Power Management Controller

The Power Management Controller uses the Clock Generator outputs to provide:

• the Processor Clock PCK

• the Master Clock MCK

• the USB Clock UDPCK

• all the peripheral clocks, independently controllable

• three programmable clock outputs

The Master Clock (MCK) is programmable from a few hundred Hz to the maximum operating frequency of the device.

XIN

XOUT

PLLRC

Embedded

Oscillator

Main

Oscillator

PLL and

Divider

Status

Power

Management

Controller

Control

Slow Clock SLCK

Main Clock MAINCK

PLL Clock PLLCK

6222B–ATARM–26-Mar-07

The Processor Clock (PCK) switches off when entering processor idle mode, thus allowing reduced power consumption while waiting for an interrupt.

Figure 9-3. Power Management Controller Block Diagram

9.4 Advanced Interrupt Controller

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM Processor

• Individually maskable and vectored interrupt sources – Source 0 is reserved for the Fast Interrupt Input (FIQ) – Source 1 is reserved for system peripherals (RTT, PIT, EFC, PMC, DBGU, etc.) – Other sources control the peripheral interrupts or external interrupts – Programmable edge-triggered or level-sensitive internal sources – Programmable positive/negative edge-triggered or high/low level-sensitive external

sources

• 8-level Priority Controller – Drives the normal interrupt nIRQ of the processor – Handles priority of the interrupt sources – Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring – Optimizes interrupt service routine branch and execution – One 32-bit vector register per interrupt source – Interrupt vector register reads the corresponding current interrupt vector

•Protect Mode – Easy debugging by preventing automatic operations

•Fast Forcing – Permits redirecting any interrupt source on the fast interrupt

• General Interrupt Mask – Provides processor synchronization on events without triggering an interrupt

SLCK

MAINCK

PLLCK

SLCK

MAINCK

PLLCK

Master Clock Controller

Programmable Clock Controller

PLLCK

Prescaler

/1,/2,/4,...,/64

Prescaler

/1,/2,/4,...,/64

USB Clock Controller

ON/OFF

Divider /1,/2,/4

Processor

Clock

Controller

Idle Mode

Peripherals

Clock Controller

ON/OFF

PCK

int

MCK

periph_clk[2..14]

pck[0..2]

usb_suspend

UDPCK

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

9.5 Debug Unit

AT91SAM7SE512/256/32 Preliminary

• Comprises: – One two-pin UART – One Interface for the Debug Communication Channel (DCC) support – One set of Chip ID Registers – One Interface providing ICE Access Prevention

•Two-pin UART – USART-compatible User Interface – Programmable Baud Rate Generator – Parity, Framing and Overrun Error – Automatic Echo, Local Loopback and Remote Loopback Channel Modes

• Debug Communication Channel Support – Offers visibility of COMMRX and COMMTX signals from the ARM Processor

• Chip ID Registers – Identification of the device revision, sizes of the embedded memories, set of

peripherals – Chip ID is 0x272A 0A40 (VERSION 0) for AT91SAM7SE512 – Chip ID is 0x272A 0940 (VERSION 0) for AT91SAM7SE256 – Chip ID is 0x2728 0340 (VERSION 0) for AT91SAM7SE32

9.6 Periodic Interval Timer

• 20-bit programmable counter plus 12-bit interval counter

9.7 Watchdog Timer

• 12-bit key-protected Programmable Counter running on prescaled SLCK

• Provides reset or interrupt signals to the system

• Counter may be stopped while the processor is in debug state or in idle mode

9.8 Real-time Timer

• 32-bit free-running counter with alarm running on prescaled SLCK

• Programmable 16-bit prescaler for SLCK accuracy compensation

9.9 PIO Controllers

• Three PIO Controllers. PIO A and B each control 32 I/O lines and PIO C controls 24 I/O lines.

• Fully programmable through set/clear registers

• Multiplexing of two peripheral functions per I/O line

• For each I/O line (whether assigned to a peripheral or used as general-purpose I/O) – Input change interrupt – Half a clock period glitch filter – Multi-drive option enables driving in open drain – Programmable pull-up on each I/O line – Pin data status register, supplies visibility of the level on the pin at any time

6222B–ATARM–26-Mar-07

• Synchronous output, provides Set and Clear of several I/O lines in a single write

9.10 Voltage Regulator Controller

The purpose of this controller is to select the Power Mode of the Voltage Regulator between Normal Mode (bit 0 is cleared) or Standby Mode (bit 0 is set).

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

10. Peripherals

10.1 User Interface

The User Peripherals are mapped in the 256 MBytes of the address space between 0xF000 0000 and 0xFFFF EFFF. Each peripheral is allocated 16 Kbytes of address space.

A complete memory map is presented in Figure 8-1 on page 22.

10.2 Peripheral Identifiers

The AT91SAM7SE512/256/32 embeds a wide range of peripherals. Table 10-1 defines the Peripheral Identifiers of the AT91SAM7SE512/256/32. Unique peripheral identifiers are defined for both the Advanced Interrupt Controller and the Power Management Controller.

Table 10-1. Peripheral Identifiers

Peripheral ID

0 AIC Advanced Interrupt Controller FIQ

1 SYSC

2 PIOA Parallel I/O Controller A

3 PIOB Parallel I/O Controller B

4 PIOC Parallel I/O Controller C

5 SPI Serial Peripheral Interface 0

6 US0 USART 0

7 US1 USART 1

8 SSC Synchronous Serial Controller

9 TWI Two-wire Interface

10 PWMC PWM Controller

11 UDP USB Device Port

12 TC0 Timer/Counter 0

13 TC1 Timer/Counter 1

14 TC2 Timer/Counter 2

15 ADC

16-28 reserved

29 AIC Advanced Interrupt Controller IRQ0

30 AIC Advanced Interrupt Controller IRQ1

AT91SAM7SE512/256/32 Preliminary

Peripheral Mnemonic

(1)

Peripheral Name

Analog-to Digital Converter

External Interrupt

6222B–ATARM–26-Mar-07

Note: 1. Setting SYSC and ADC bits in the clock set/clear registers of the PMC has no effect. The Sys-

tem Controller is continuously clocked. The ADC clock is automatically started for the first conversion. In Sleep Mode the ADC clock is automatically stopped after each conversion.

10.3 Peripheral Multiplexing on PIO Lines

The AT91SAM7SE512/256/32 features three PIO controllers, PIOA, PIOB and PIOC, that multiplex the I/O lines of the peripheral set.

PIO Controller A and B control 32 lines; PIO Controller C controls 24 lines. Each line can be assigned to one of two peripheral functions, A or B. Some of them can also be multiplexed with the analog inputs of the ADC Controller.

Table 10-2 on page 37 defines how the I/O lines of the peripherals A and B or the analog inputs

are multiplexed on the PIO Controller A, B and C. The two columns “Function” and “Comments” have been inserted for the user’s own comments; they may be used to track how pins are defined in an application.

Note that some peripheral functions that are output only may be duplicated in the table.

At reset, all I/O lines are automatically configured as input with the programmable pull-up enabled, so that the device is maintained in a static state as soon as a reset is detected.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

10.4 PIO Controller A Multiplexing

Table 10-2. Multiplexing on PIO Controller A

PIO Controller A Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PA0 PWM0 A0/NBS0 High-Drive

PA1 PWM1 A1/NBS2 High-Drive

PA2 PWM2 A2 High-Drive

PA3 TWD A3 High-Drive

PA 4 T WC K A 4

PA 5 R XD 0 A 5

PA 6 T XD 0 A 6

PA 7 RT S 0 A 7

PA 8 C TS 0 A 8

PA9 DRXD A9

PA 10 D TX D A 1 0

PA11 NPCS0 A11

PA12 MISO A12

PA13 MOSI A13

PA14 SPCK A14

PA 15 T F A 1 5

PA16 TK A16/BA0

PA17 TD A17/BA1 AD0

PA18 RD NBS3/CFIOW AD1

PA 19

PA 20

PA21 RXD1 NCS6/CFCE2

PA22 TXD1 NCS5/CFCE1

PA23 SCK1 NWR1/NBS1/CFIOR

PA24 RTS1 SDA10

PA25 CTS1 SDCKE

PA26 DCD1 NCS1/SDCS

PA27 DTR1 SDWE

PA28 DSR1 CAS

RK NCS4/CFCS0 AD2

RF NCS2/CFCS1 AD3

PA 29 R I1 R A S

PA30 IRQ1 D30

PA31 NPCS1 D31

6222B–ATARM–26-Mar-07

10.5 PIO Controller B Multiplexing

Table 10-3. Multiplexing on PIO Controller B

PIO Controller B Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PB0 TIOA0 A0/NBS0

PB1 TIOB0 A1/NBS2

PB2 SCK0 A2

PB3 NPCS3 A3

PB4 TCLK0 A4

PB5 NPCS3 A5

PB6 PCK0 A6

PB7 PWM3 A7

PB8 ADTRG A8

PB9 NPCS1 A9

PB10 NPCS2 A10

PB11 PWM0 A11

PB12 PWM1 A12

PB13 PWM2 A13

PB14 PWM3 A14

PB15 TIOA1 A15

PB16 TIOB1 A16/BA0

PB17 PCK1 A17/BA1

PB18 PCK2 D16

PB19 FIQ D17

PB20 IRQ0 D18

PB21 PCK1 D19

PB22 NPCS3 D20

PB23 PWM0 D21

PB24 PWM1 D22

PB25 PWM2 D23

PB26 TIOA2 D24

PB27 TIOB2 D25

PB28 TCLK1 D26

PB29 TCLK2 D27

PB30 NPCS2 D28

PB31 PCK2 D29

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

10.6 PIO Controller C Multiplexing

Multiplexing on PIO Controller C

PIO Controller C Application Usage

I/O Line Peripheral A Peripheral B Comments Function Comments

PC0 D0

PC1 D1

PC2 D2

PC3 D3

PC4 D4

PC5 D5

PC6 D6

PC7 D7

PC8 D8 RTS1

PC9 D9 DTR1

PC10 D10 PCK0

PC11 D11 PCK1

PC12 D12 PCK2

PC13 D13

PC14 D14 NPCS1

PC15 D15 NCS3/NANDCS

PC16 A18 NWAIT

PC17 A19 NANDOE

PC18 A20 NANDWE

PC19 A21/NANDALE

PC20 A22/REG/NANDCLE NCS7

PC21 NWR0/NWE/CFWE

PC22 NRD/CFOE

PC23 CFRNW NCS0

10.7 Serial Peripheral Interface

• Supports communication with external serial devices – Four chip selects with external decoder allow communication with up to 15

peripherals – Serial memories, such as DataFlash – Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and

Sensors – External co-processors

• Master or slave serial peripheral bus interface

and 3-wire EEPROMs

6222B–ATARM–26-Mar-07

10.8 Two Wire Interface

• Master, Multi-Master and Slave Mode Operation

• Compatibility with standard two-wire serial memories

• One, two or three bytes for slave address

• Sequential read/write operations

• Bit Rate: Up to 400 Kbit/s

• General Call Supported in Slave Mode

10.9 USART

• Programmable Baud Rate Generator

• 5- to 9-bit full-duplex synchronous or asynchronous serial communications

• RS485 with driver control signal

• ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards

•IrDA

• Test Modes

– 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays per chip select, between consecutive transfers and

between clock and data – Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency at up to Master Clock

– 1, 1.5 or 2 stop bits in Asynchronous Mode – 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB or LSB first – Optional break generation and detection – By 8 or by 16 over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard – Multi-drop Mode with address generation and detection

– NACK handling, error counter with repetition and iteration limit

modulation and demodulation

– Communication at up to 115.2 Kbps

– Remote Loopback, Local Loopback, Automatic Echo

10.10 Serial Synchronous Controller

• Provides serial synchronous communication links used in audio and telecom applications

• Contains an independent receiver and transmitter and a common clock divider

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

10.11 Timer Counter

AT91SAM7SE512/256/32 Preliminary

• Offers a configurable frame sync and data length

• Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal

• Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal

• Three 16-bit Timer Counter Channels

– Three output compare or two input capture

• Wide range of functions including:

– Frequency measurement – Event counting – Interval measurement – Pulse generation – Delay timing – Pulse Width Modulation – Up/down capabilities

• Each channel is user-configurable and contains:

– Three external clock inputs – Five internal clock inputs, as defined in Table 10-4

Table 10-4. Timer Counter Clocks Assignment

10.12 PWM Controller

TC Clock input Clock

TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 MCK/1024

– Two multi-purpose input/output signals – Two global registers that act on all three TC channels

• Four channels, one 16-bit counter per channel

• Common clock generator, providing thirteen different clocks

– One Modulo n counter providing eleven clocks – Two independent linear dividers working on modulo n counter outputs

• Independent channel programming

– Independent enable/disable commands – Independent clock selection – Independent period and duty cycle, with double buffering – Programmable selection of the output waveform polarity – Programmable center or left aligned output waveform

6222B–ATARM–26-Mar-07

10.13 USB Device Port

• USB V2.0 full-speed compliant,12 Mbits per second.

• Embedded USB V2.0 full-speed transceiver

• Embedded 2688-byte dual-port RAM for endpoints

• Eight endpoints

– Endpoint 0: 64bytes – Endpoint 1 and 2: 64 bytes ping-pong – Endpoint 3: 64 bytes – Endpoint 4 and 5: 512 bytes ping-pong – Endpoint 6 and 7: 64 bytes ping-pong – Ping-pong Mode (two memory banks) for Isochronous and bulk endpoints

• Suspend/resume logic

• Integrated Pull-up on DDP

10.14 Analog-to-Digital Converter

• 8-channel ADC

• 10-bit 384 Ksamples/sec. or 8-bit 583 Ksamples/sec. Successive Approximation Register ADC

• ±2 LSB Integral Non Linearity, ±1 LSB Differential Non Linearity

• Integrated 8-to-1 multiplexer, offering eight independent 3.3V analog inputs

• External voltage reference for better accuracy on low voltage inputs

• Individual enable and disable of each channel

• Multiple trigger sources

– Hardware or software trigger – External trigger pin – Timer Counter 0 to 2 outputs TIOA0 to TIOA2 trigger

• Sleep Mode and conversion sequencer

– Automatic wakeup on trigger and back to sleep mode after conversions of all

enabled channels

• Each analog input shared with digital signals

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

11. ARM7TDMI Processor Overview

11.1 Overview

The ARM7TDMI core executes both the 32-bit ARM and 16-bit Thumb instruction sets, allowing the user to trade off between high performance and high code density.The ARM7TDMI processor implements Von Neuman architecture, using a three-stage pipeline consisting of Fetch, Decode, and Execute stages.

The main features of the ARM7tDMI processor are:

• ARM7TDMI Based on ARMv4T Architecture

• Two Instruction Sets

– ARM High-performance 32-bit Instruction Set – Thumb High Code Density 16-bit Instruction Set

• Three-Stage Pipeline Architecture

– Instruction Fetch (F) – Instruction – Execute (E)

Decode (D)

6222B–ATARM–26-Mar-07

11.2 ARM7TDMI Processor

For further details on ARM7TDMI, refer to the following ARM documents:

ARM Architecture Reference Manual (DDI 0100E)

ARM7TDMI Technical Reference Manual (DDI 0210B)

11.2.1 Instruction Type

Instructions are either 32 bits long (in ARM state) or 16 bits long (in THUMB state).

11.2.2 Data Type

ARM7TDMI supports byte (8-bit), half-word (16-bit) and word (32-bit) data types. Words must be aligned to four-byte boundaries and half words to two-byte boundaries.

Unaligned data access behavior depends on which instruction is used where.

11.2.3 ARM7TDMI Operating Mode

The ARM7TDMI, based on ARM architecture v4T, supports seven processor modes:

User: The normal ARM program execution state FIQ: Designed to support high-speed data transfer or channel process IRQ: Used for general-purpose interrupt handling Supervisor: Protected mode for the operating system

Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User mode. The non-user modes, or privileged modes, are entered in order to service interrupts or exceptions, or to access protected resources.

11.2.4 ARM7TDMI Registers

The ARM7TDMI processor has a total of 37registers:

• 31 general-purpose 32-bit registers

• 6 status registers

These registers are not accessible at the same time. The processor state and operating mode determine which registers are available to the programmer.

At any one time 16 registers are visible to the user. The remainder are synonyms used to speed up exception processing.

Register 15 is the Program Counter (PC) and can be used in all instructions to reference data relative to the current instruction.

R14 holds the return address after a subroutine call.

Abort mode: Implements virtual memory and/or memory protection System: A privileged user mode for the operating system Undefined: Supports software emulation of hardware coprocessors

R13 is used (by software convention) as a stack pointer.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

Table 11-1. ARM7TDMI ARM Modes and Registers Layout

User and System Mode

R0 R0 R0 R0 R0 R0

R1 R1 R1 R1 R1 R1

R2 R2 R2 R2 R2 R2

R3 R3 R3 R3 R3 R3

R4 R4 R4 R4 R4 R4

R5 R5 R5 R5 R5 R5

R6 R6 R6 R6 R6 R6

R7 R7 R7 R7 R7 R7

R8 R8 R8 R8 R8

R9 R9 R9 R9 R9

R10 R10 R10 R10 R10

R11 R11 R11 R11 R11 R11_FIQ

R12 R12 R12 R12 R12

R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ

R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ

PC PC PC PC PC PC

Supervisor Mode Abort Mode

Undefined Mode

Interrupt Mode

Fast Interrupt Mode

R8_FIQ

R9_FIQ

R10_FIQ

R12_FIQ

CPSR CPSR CPSR CPSR CPSR CPSR

Registers R0 to R7 are unbanked registers. This means that each of them refers to the same 32bit physical register in all processor modes. They are general-purpose registers, with no special uses managed by the architecture, and can be used wherever an instruction allows a generalpurpose register to be specified.

Registers R8 to R14 are banked registers. This means that each of them depends on the current mode of the processor.

11.2.4.1 Modes and Exception Handling

All exceptions have banked registers for R14 and R13.

After an exception, R14 holds the return address for exception processing. This address is used to return after the exception is processed, as well as to address the instruction that caused the exception.

R13 is banked across exception modes to provide each exception handler with a private stack pointer.

The fast interrupt mode also banks registers 8 to 12 so that interrupt processing can begin without having to save these registers.

SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ

Mode-specific banked registers

6222B–ATARM–26-Mar-07

A seventh processing mode, System Mode, does not have any banked registers. It uses the User Mode registers. System Mode runs tasks that require a privileged processor mode and allows them to invoke all classes of exceptions.

11.2.4.2 Status Registers

All other processor states are held in status registers. The current operating processor status is in the Current Program Status Register (CPSR). The CPSR holds:

• four ALU flags (Negative, Zero, Carry, and Overflow)

• two interrupt disable bits (one for each type of interrupt)

• one bit to indicate ARM or Thumb execution

• five bits to encode the current processor mode

All five exception modes also have a Saved Program Status Register (SPSR) that holds the CPSR of the task immediately preceding the exception.

11.2.4.3 Exception Types

The ARM7TDMI supports five types of exception and a privileged processing mode for each type.

The types of exceptions are:

• fast interrupt (FIQ)

• normal interrupt (IRQ)

• memory aborts (used to implement memory protection or virtual memory)

• attempted execution of an undefined instruction

• software interrupts (SWIs)

Exceptions are generated by internal and external sources.

More than one exception can occur in the same time.

When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save state.

To return after handling the exception, the SPSR is moved to the CPSR, and R14 is moved to the PC. This can be done in two ways:

• by using a data-processing instruction with the S-bit set, and the PC as the destination

• by using the Load Multiple with Restore CPSR instruction (LDM)

11.2.5 ARM Instruction Set Overview

The ARM instruction set is divided into:

• Branch instructions

• Data processing instructions

• Status register transfer instructions

• Load and Store instructions

• Coprocessor instructions

• Exception-generating instructions

ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bit[31:28]).

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

Table 11-2 gives the ARM instruction mnemonic list.

Table 11-2. ARM Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move CDP Coprocessor Data Processing

ADD Add MVN Move Not

SUB Subtract ADC Add with Carry

RSB Reverse Subtract SBC Subtract with Carry

CMP Compare RSC Reverse Subtract with Carry

TST Test CMN Compare Negated

AND Logical AND TEQ Test Equivalence

EOR Logical Exclusive OR BIC Bit Clear

MUL Multiply ORR Logical (inclusive) OR

SMULL Sign Long Multiply MLA Multiply Accumulate

SMLAL Signed Long Multiply Accumulate UMULL Unsigned Long Multiply

MSR Move to Status Register UMLAL Unsigned Long Multiply Accumulate

B Branch MRS Move From Status Register

BX Branch and Exchange BL Branch and Link

LDR Load Word SWI Software Interrupt

LDRSH Load Signed Halfword STR Store Word

LDRSB Load Signed Byte STRH Store Half Word

LDRH Load Half Word STRB Store Byte

LDRB Load Byte STRBT Store Register Byte with Translation

LDRBT Load Register Byte with Translation STRT Store Register with Translation

LDRT Load Register with Translation STM Store Multiple

LDM Load Multiple SWPB Swap Byte

SWP Swap Word MRC Move From Coprocessor

MCR Move To Coprocessor STC Store From Coprocessor

LDC Load To Coprocessor

11.2.6 Thumb Instruction Set Overview

The Thumb instruction set is a re-encoded subset of the ARM instruction set.

The Thumb instruction set is divided into:

• Branch instructions

• Data processing instructions

• Load and Store instructions

• Load and Store Multiple instructions

• Exception-generating instruction

In Thumb mode, eight general-purpose registers, R0 to R7, are available that are the same physical registers as R0 to R7 when executing ARM instructions. Some Thumb instructions also

6222B–ATARM–26-Mar-07

access to the Program Counter (ARM Register 15), the Link Register (ARM Register 14) and the Stack Pointer (ARM Register 13). Further instructions allow limited access to the ARM registers 8 to 15.

Table 11-3 gives the Thumb instruction mnemonic list.

Table 11-3. Thumb Instruction Mnemonic List

Mnemonic Operation Mnemonic Operation

MOV Move MVN Move Not

ADD Add ADC Add with Carry

SUB Subtract SBC Subtract with Carry

CMP Compare CMN Compare Negated

TST Test NEG Negate

AND Logical AND BIC Bit Clear

EOR Logical Exclusive OR ORR Logical (inclusive) OR

LSL Logical Shift Left LSR Logical Shift Right

ASR Arithmetic Shift Right ROR Rotate Right

MUL Multiply

B Branch BL Branch and Link

BX Branch and Exchange SWI Software Interrupt

LDR Load Word STR Store Word

LDRH Load Half Word STRH Store Half Word

LDRB Load Byte STRB Store Byte

LDRSH Load Signed Halfword LDRSB Load Signed Byte

LDMIA Load Multiple STMIA Store Multiple

PUSH Push Register to stack POP Pop Register from stack

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

12. Debug and Test Features

12.1 Overview

The AT91SAM7SE Series Microcontrollers feature a number of complementary debug and test capabilities. A common JTAG/ICE (Embedded ICE) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel.

A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment.

12.2 Block Diagram

Figure 12-1. Debug and Test Block Diagram

AT91SAM7SE512/256/32 Preliminary

TMS

TCK

Boundary

TA P

ICE

ARM7TDMI

PDC DBGU

ICE/JTAG

TA P

Reset

and Test

PIO

TDI

JTAGSEL

TDO

POR

TST

DTXD

DRXD

6222B–ATARM–26-Mar-07

12.3 Application Examples

12.3.1 Debug Environment

Figure 12-2 shows a complete debug environment example. The ICE/JTAG interface is used for

standard debugging functions, such as downloading code and single-stepping through the program.

Figure 12-2. Application Debug Environment Example

Host Debugger

ICE/JTAG Interface

ICE/JTAG

Connector

AT91SAMSExx

AT91SAM7Sxx-based Application Board

RS232

Connector

Terminal

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

12.3.2 Test Environment

Figure 12-3 shows a test environment example. Test vectors are sent and interpreted by the

tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain.

Figure 12-3. Application Test Environment Example

AT91SAM7SE512/256/32 Preliminary

Test Adaptor

JTAG

Interface

ICE/JTAG

Connector

AT91SAM7SExx

AT91SAM7SExx-based Application Board In Test

Chip n

Chip 2

Chip 1

Tester

6222B–ATARM–26-Mar-07

12.4 Debug and Test Pin Description

Table 12-1. Debug and Test Pin List

Pin Name Function Type Active Level

NRST Microcontroller Reset Input/Output Low

TST Test Mode Select Input High

TCK Test Clock Input

TDI Test Data In Input

TDO Test Data Out Output

TMS Test Mode Select Input

JTAGSEL JTAG Selection Input

DRXD Debug Receive Data Input

DTXD Debug Transmit Data Output

Reset/Test

ICE and JTAG

Debug Unit

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

12.5 Functional Description

12.5.1 Test Pin

One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test.

AT91SAM7SE512/256/32 Preliminary

12.5.2 EmbeddedICE

12.5.3 Debug Unit

™

(Embedded In-circuit Emulator)

The ARM7TDMI EmbeddedICE is supported via the ICE/JTAG port.The internal state of the ARM7TDMI is examined through an ICE/JTAG port.

The ARM7TDMI processor contains hardware extensions for advanced debugging features:

• In halt mode, a store-multiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM7TDMI registers. This data can be serially shifted out without affecting the rest of the system.

• In monitor mode, the JTAG interface is used to transfer data between the debugger and a simple monitor program running on the ARM7TDMI processor.

There are three scan chains inside the ARM7TDMI processor that support testing, debugging, and programming of the Embedded ICE. The scan chains are controlled by the ICE/JTAG port.

Embedded ICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed.

For further details on the Embedded ICE, see the ARM7TDMI (Rev4) Technical Reference Manual (DDI0210B).

The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum.

6222B–ATARM–26-Mar-07

The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel.The Debug Unit allows blockage of access to the system through the ICE interface.

A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration.

Table 12-2. AT91SAM7SExx Chip IDs

Chip Name Chip ID

AT91SAM7SE32 0x27280340

AT91SAM7SE256 0x272A0940

AT91SAM7SE512 0x272A0A40

For further details on the Debug Unit, see the Debug Unit section.

12.5.4 IEEE 1149.1 JTAG Boundary Scan

IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology.

IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed.

A Boundary-scan Descriptor Language (BSDL) file is provided to set up test.

12.5.4.1 JTAG Boundary-scan Register

The Boundary-scan Register (BSR) contains 353 bits that correspond to active pins and associated control signals.

Each AT91SAM7SExx input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad.

For more information, please refer to BDSL files which are available for SAM7SE Series.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

12.5.5 ID Code Register

Access: Read-only

31 30 29 28 27 26 25 24

VERSION PART NUMBER

23 22 21 20 19 18 17 16

PART NUMBER

15 14 13 12 11 10 9 8

PART NUMBER MANUFACTURER IDENTITY

76543210

MANUFACTURER IDENTITY 1

• VERSION[31:28]: Product Version Number

Set to 0x0.

• PART NUMBER[27:12]: Product Part Number

Chip Name Chip ID

AT91SAM7SE32 0x5B1D

AT91SAM7SE256 0x5B15

AT91SAM7SE512 0x5B14

• MANUFACTURER IDENTITY[11:1]

Set to 0x01F.

• Bit[0] Required by IEEE Std. 1149.1.

Set to 0x1.

Chip Name JTAG ID Code

AT91SAM7SE32 05B1_D03F

AT91SAM7SE256 05B1_503F

AT91SAM7SE512 05B1_403F

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

13. Reset Controller (RSTC)

The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last.

The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets.

A brownout detection is also available to prevent the processor from falling into an unpredictable state.

13.1 Block Diagram

Figure 13-1. Reset Controller Block Diagram

AT91SAM7SE512/256/32 Preliminary

Reset Controller

bod_rst_en

brown_out

Main Supply

POR

NRST

WDRPROC

wd_fault

nrst_out

Brownout

Manager

Startup

Counter

NRST

Manager

bod_reset

user_reset

exter_nreset

Reset

State

Manager

SLCK

rstc_irq

proc_nreset

periph_nreset

6222B–ATARM–26-Mar-07

13.2 Functional Description

13.2.1 Reset Controller Overview

The Reset Controller is made up of an NRST Manager, a Brownout Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:

• proc_nreset: Processor reset line. It also resets the Watchdog Timer.

• periph_nreset: Affects the whole set of embedded peripherals.

• nrst_out: Drives the NRST pin.

These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required.

The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.

The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation.

13.2.2 NRST Manager

The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 13-2 shows the block diagram of the NRST Manager.

Figure 13-2. NRST Manager

13.2.2.1 NRST Signal or Interrupt

The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager.

However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger.

NRST

RSTC_SR

URSTS

NRSTL

nrst_out

RSTC_MR

URSTEN

RSTC_MR

ERSTL

External Reset Timer

URSTIEN

rstc_irq

Other

interrupt

sources

user_reset

exter_nreset

The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1.

13.2.2.2 NRST External Reset Control

The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts

(ERSTL+1)

Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs

and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse.

This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset.

13.2.3 Brownout Manager

Brownout detection prevents the processor from falling into an unpredictable state if the power supply drops below a certain level. When VDDCORE drops below the brownout threshold, the brownout manager requests a brownout reset by asserting the bod_reset signal.

AT91SAM7SE512/256/32 Preliminary

13.2.4 Reset States

The programmer can disable the brownout reset by setting low the bod_rst_en input signal, i.e.; by locking the corresponding general-purpose NVM bit in the Flash. When the brownout reset is disabled, no reset is performed. Instead, the brownout detection is reported in the bit BODSTS of RSTC_SR. BODSTS is set and clears only when RSTC_SR is read.

The bit BODSTS can trigger an interrupt if the bit BODIEN is set in the RSTC_MR.

At factory, the brownout reset is disabled.

Figure 13-3. Brownout Manager

bod_rst_en

brown_out

RSTC_SR

BODSTS

RSTC_MR

BODIEN

Other

interrupt

sources

bod_reset

rstc_irq

6222B–ATARM–26-Mar-07

The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released.

13.2.4.1 Power-up Reset

When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow Clock oscillator is stable before starting up the device.

The startup time, as shown in Figure 13-4, is hardcoded to comply with the Slow Clock Oscillator startup time. After the startup time, the reset signals are released and the field RSTTYP in RSTC_SR reports a Power-up Reset.

When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted immediately.

Figure 13-4. Power-up Reset

SLCK

MCK

Main Supply

POR output

proc_nreset

periph_nreset

NRST

(nrst_out)

13.2.4.2 User Reset

Any

Freq.

Startup Time

Processor Startup

= 3 cycles

EXTERNAL RESET LENGTH

= 2 cycles

The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system.

The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted.

The User Reset is left when NRST rises, after a two-cycle resynchronization time and a threecycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high.

When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset.

The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

Figure 13-5. User Reset State

SLCK

AT91SAM7SE512/256/32 Preliminary

MCK

NRST

proc_nreset

RSTTYP

periph_nreset

NRST

(nrst_out)

13.2.4.3 Brownout Reset

When the brown_out/bod_reset signal is asserted, the Reset State Manager immediately enters the Brownout Reset. In this state, the processor, the peripheral and the external reset lines are asserted.

Any

Freq.

Resynch.

2 cycles

Any XXX

>= EXTERNAL RESET LENGTH

Resynch.

2 cycles

Processor Startup

= 3 cycles

0x4 = User Reset

The Brownout Reset is left 3 Slow Clock cycles after the rising edge of brown_out/bod_reset after a two-cycle resynchronization. An external reset is also triggered.

When the processor reset is released, the field RSTTYP in RSTC_SR is loaded with the value 0x5, thus indicating that the last reset is a Brownout Reset.

6222B–ATARM–26-Mar-07

Figure 13-6. Brownout Reset State

SLCK

MCK

brown_out

or bod_reset

proc_nreset

RSTTYP

periph_nreset

NRST

(nrst_out)

13.2.4.4 Software Reset

The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:

Any

Freq.

Any

Resynch.

2 cycles

XXX

Processor Startup

= 3 cycles

0x5 = Brownout Reset

EXTERNAL RESET LENGTH

8 cycles (ERSTL=2)

• PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.

• PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.

• EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR).

The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts 3 Slow Clock cycles.

The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e.; synchronously to SLCK.

If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset.

If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect.

Figure 13-7. Software Reset

SLCK

13.2.4.5 Watchdog Reset

The Watchdog Reset is entered when a watchdog fault occurs. This state lasts 3 Slow Clock cycles.

When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:

• If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST

• If WDRPROC = 1, only the processor reset is asserted.

MCK

Write RSTC_CR

proc_nreset

if PROCRST=1

RSTTYP

periph_nreset

if PERRST=1

NRST

(nrst_out)

if EXTRST=1

SRCMP in RSTC_SR

Any

Freq.

Any

Resynch.

1 cycle

Processor Startup

= 3 cycles

XXX

EXTERNAL RESET LENGTH

0x3 = Software Reset

8 cycles (ERSTL=2)

line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.

6222B–ATARM–26-Mar-07

The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum.

When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller.

Figure 13-8. Watchdog Reset

SLCK

Only if

WDRPROC = 0

13.2.5 Reset State Priorities

The Reset State Manager manages the following priorities between the different reset sources, given in descending order:

• Power-up Reset

•Brownout Reset

• Watchdog Reset

• Software Reset

• User Reset

MCK

wd_fault

proc_nreset

RSTTYP

periph_nreset

NRST

(nrst_out)

Any

Freq.

Any

Processor Startup

= 3 cycles

XXX

EXTERNAL RESET LENGTH

0x2 = Watchdog Reset

8 cycles (ERSTL=2)

Particular cases are listed below:

• When in User Reset:

– A watchdog event is impossible because the Watchdog Timer is being reset by the

proc_nreset signal.

– A software reset is impossible, since the processor reset is being activated.

• When in Software Reset:

– A watchdog event has priority over the current state. – The NRST has no effect.

• When in Watchdog Reset:

– The processor reset is active and so a Software Reset cannot be programmed. – A User Reset cannot be entered.

13.2.6 Reset Controller Status Register

The Reset Controller status register (RSTC_SR) provides several status fields:

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

• RSTTYP field: This field gives the type of the last reset, as explained in previous sections.

• SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.

• NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.

• URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR register. This transition is also detected on the Master Clock (MCK) rising edge (see Figure

13-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the

URSTIEN bit in the RSTC_MR register, the URSTS bit triggers an interrupt. Reading the RSTC_SR status register resets the URSTS bit and clears the interrupt.

• BODSTS bit: This bit indicates a brownout detection when the brownout reset is disabled (bod_rst_en = 0). It triggers an interrupt if the bit BODIEN in the RSTC_MR register enables the interrupt. Reading the RSTC_SR register resets the BODSTS bit and clears the interrupt.

Figure 13-9. Reset Controller Status and Interrupt

MCK

AT91SAM7SE512/256/32 Preliminary

Peripheral Access

NRST

NRSTL

URSTS

rstc_irq

if (URSTEN = 0) and

(URSTIEN = 1)

2 cycle

resynchronization

2 cycle

resynchronization

read

RSTC_SR

13.3 Reset Controller (RSTC) User Interface

Table 13-1. Reset Controller (RSTC) Register Mapping

Offset Register Name Access Reset Value

0x00 Control Register RSTC_CR Write-only -

0x04 Status Register RSTC_SR Read-only 0x0000_0000

0x08 Mode Register RSTC_MR Read/Write 0x0000_0000

6222B–ATARM–26-Mar-07

13.3.1 Reset Controller Control Register Register Name: RSTC_CR Access Type: Write-only

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

–––––– –

76543210 ––––EXTRSTPERRST–PROCRST

• PROCRST: Processor Reset

0 = No effect. 1 = If KEY is correct, resets the processor.

• PERRST: Peripheral Reset

0 = No effect. 1 = If KEY is correct, resets the peripherals.

• EXTRST: External Reset

0 = No effect. 1 = If KEY is correct, asserts the NRST pin.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

13.3.2 Reset Controller Status Register Register Name: RSTC_SR Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––SRCMPNRSTL

15 14 13 12 11 10 9 8

––––– RSTTYP

76543210 ––––––BODSTSURSTS

• URSTS: User Reset Status

0 = No high-to-low edge on NRST happened since the last read of RSTC_SR. 1 = At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR.

• BODSTS: Brownout Detection Status

0 = No brownout high-to-low transition happened since the last read of RSTC_SR. 1 = A brownout high-to-low transition has been detected since the last read of RSTC_SR.

• RSTTYP: Reset Type

Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field.

RSTTYP Reset Type Comments

0 0 0 Power-up Reset VDDCORE rising

0 1 0 Watchdog Reset Watchdog fault occurred

0 1 1 Software Reset Processor reset required by the software

1 0 0 User Reset NRST pin detected low

1 0 1 Brownout Reset Brownout reset occurred

• NRSTL: NRST Pin Level

Registers the NRST Pin Level at Master Clock (MCK).

• SRCMP: Software Reset Command in Progress

0 = No software command is being performed by the reset controller. The reset controller is ready for a software command. 1 = A software reset command is being performed by the reset controller. The reset controller is busy.

13.3.3 Reset Controller Mode Register Register Name: RSTC_MR

6222B–ATARM–26-Mar-07

Access Type: Read/Write

31 30 29 28 27 26 25 24

KEY

23 22 21 20 19 18 17 16

–––––––BODIEN

15 14 13 12 11 10 9 8

–––– ERSTL

76543210 – – URSTIEN – – – URSTEN

• URSTEN: User Reset Enable

0 = The detection of a low level on the pin NRST does not generate a User Reset. 1 = The detection of a low level on the pin NRST triggers a User Reset.

• URSTIEN: User Reset Interrupt Enable

0 = USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0.

• BODIEN: Brownout Detection Interrupt Enable

0 = BODSTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1 = BODSTS bit in RSTC_SR at 1 asserts rstc_irq.

• ERSTL: External Reset Length

This field defines the external reset length. The external reset is asserted during a time of 2

(ERSTL+1)

allows assertion duration to be programmed between 60 µs and 2 seconds.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

Slow Clock cycles. This

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

14. Real-time Timer (RTT)

14.1 Overview

The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt or/and triggers an alarm on a programmed value.

14.2 Block Diagram

Figure 14-1. Real-time Timer

AT91SAM7SE512/256/32 Preliminary

SLCK

RTT_MR

RTTRST

reload

16-bit

Divider

RTT_MR RTPRES

RTT_MR

RTTRST

RTT_VR

RTT_AR

32-bit

Counter

CRTV

ALMV

RTT_SR

read

set

RTTINC

reset

set

RTT_MR

RTTINCIEN

rtt_int

RTT_MR

ALMIEN

ALMS

rtt_alarm

14.3 Functional Description

The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR).

Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 Hz). The 32-bit counter can count up to 2 sponding to more than 136 years, then roll over to 0.

The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear.

6222B–ATARM–26-Mar-07

seconds, corre-

The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value.

The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset.

The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 Hz.

Reading the RTT_SR status register resets the RTTINC and ALMS fields.

Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK):

1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR register.

2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register).

Figure 14-2. RTT Counting

MCK

RTPRES - 1

Prescaler

RTT

RTTINC (RTT_SR)

ALMS (RTT_SR)

APB Interface

APB cycle

...

ALMVALMV-10 ALMV+1

read RTT_SR

ALMV+2 ALMV+3

APB cycle

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

14.4 Real-time Timer (RTT) User Interface

Table 14-1. Real-time Timer (RTT) Register Mapping

Offset Register Name Access Reset Value

0x00 Mode Register RTT_MR Read/Write 0x0000_8000

0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF

0x08 Value Register RTT_VR Read-only 0x0000_0000

0x0C Status Register RTT_SR Read-only 0x0000_0000

6222B–ATARM–26-Mar-07

14.4.1 Real-time Timer Mode Register Register Name: RTT_MR

Access Type: Read/Write

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–––––RTTRSTRTTINCIENALMIEN

15 14 13 12 11 10 9 8

RTPRES

76543210

RTPRES

• RTPRES: Real-time Timer Prescaler Value

Defines the number of SLCK periods required to increment the real-time timer. RTPRES is defined as follows:

RTPRES = 0: The Prescaler Period is equal to 2

RTPRES ≠ 0: The Prescaler Period is equal to RTPRES.

• ALMIEN: Alarm Interrupt Enable

0 = The bit ALMS in RTT_SR has no effect on interrupt.

1 = The bit ALMS in RTT_SR asserts interrupt.

• RTTINCIEN: Real-time Timer Increment Interrupt Enable

0 = The bit RTTINC in RTT_SR has no effect on interrupt.

1 = The bit RTTINC in RTT_SR asserts interrupt.

• RTTRST: Real-time Timer Restart

1 = Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

14.4.2 Real-time Timer Alarm Register Register Name: RTT_AR

Access Type: Read/Write

31 30 29 28 27 26 25 24

ALMV

23 22 21 20 19 18 17 16

ALMV

15 14 13 12 11 10 9 8

ALMV

76543210

ALMV

• ALMV: Alarm Value

Defines the alarm value (ALMV+1) compared with the Real-time Timer.

14.4.3 Real-time Timer Value Register Register Name: RTT_VR

Access Type: Read-only

31 30 29 28 27 26 25 24

CRTV

23 22 21 20 19 18 17 16

CRTV

15 14 13 12 11 10 9 8

CRTV

76543210

CRTV

• CRTV: Current Real-time Value

Returns the current value of the Real-time Timer.

6222B–ATARM–26-Mar-07

14.4.4 Real-time Timer Status Register Register Name: RTT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––––RTTINCALMS

• ALMS: Real-time Alarm Status

0 = The Real-time Alarm has not occurred since the last read of RTT_SR.

1 = The Real-time Alarm occurred since the last read of RTT_SR.

• RTTINC: Real-time Timer Increment

0 = The Real-time Timer has not been incremented since the last read of the RTT_SR.

1 = The Real-time Timer has been incremented since the last read of the RTT_SR.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

15. Periodic Interval Timer (PIT)

15.1 Overview

The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time.

15.2 Block Diagram

Figure 15-1. Periodic Interval Timer

AT91SAM7SE512/256/32 Preliminary

PIT_MR

PIV

MCK

Prescaler

MCK/16

= ?

20-bit

Counter

CPIV

CPIV PICNT

PIT_PIVR

PIT_PIIR

12-bit Adder

PICNT

PIT_MR

PITIEN

set

PIT_SR

PITS

reset

read PIT_PIVR

pit_irq

6222B–ATARM–26-Mar-07

15.3 Functional Description

The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems.

The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16.

The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR).

Writing a new PIV value in PIT_MR does not reset/restart the counters.

When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR.

When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR.

The PIT may be enabled/disabled using the PITEN bit in the PIT_MR register (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 15-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN= 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again.

The PIT is stopped when the core enters debug state.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

Figure 15-2. Enabling/Disabling PIT with PITEN

AT91SAM7SE512/256/32 Preliminary

APB cycle

MCK

APB cycle

restarts MCK Prescaler

MCK Prescaler

PITEN

CPIV

PICNT

PITS (PIT_SR)

APB Interface

PIVPIV - 10

read PIT_PIVR

6222B–ATARM–26-Mar-07

15.4 Periodic Interval Timer (PIT) User Interface

Table 15-1. Periodic Interval Timer (PIT) Register Mapping

Offset Register Name Access Reset Value

0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF

0x04 Status Register PIT_SR Read-only 0x0000_0000

0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000

0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

15.4.1 Periodic Interval Timer Mode Register Register Name:PIT_MR

Access Type: Read/Write

31 30 29 28 27 26 25 24

––––––PITIENPITEN

23 22 21 20 19 18 17 16

–––– PIV

15 14 13 12 11 10 9 8

PIV

76543210

PIV

• PIV: Periodic Interval Value

Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1).

• PITEN: Period Interval Timer Enabled

0 = The Periodic Interval Timer is disabled when the PIV value is reached.

1 = The Periodic Interval Timer is enabled.

• PITIEN: Periodic Interval Timer Interrupt Enable

0 = The bit PITS in PIT_SR has no effect on interrupt.

1 = The bit PITS in PIT_SR asserts interrupt.

15.4.2 Periodic Interval Timer Status Register Register Name: PIT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––PITS

• PITS: Periodic Interval Timer Status

0 = The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR.

1 = The Periodic Interval timer has reached PIV since the last read of PIT_PIVR.

6222B–ATARM–26-Mar-07

15.4.3 Periodic Interval Timer Value Register Register Name: PIT_PIVR

Access Type: Read-only

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

Reading this register clears PITS in PIT_SR.

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

15.4.4 Periodic Interval Timer Image Register Register Name: PIT_PIIR

Access Type: Read-only

31 30 29 28 27 26 25 24

PICNT

23 22 21 20 19 18 17 16

PICNT CPIV

15 14 13 12 11 10 9 8

CPIV

76543210

CPIV

• CPIV: Current Periodic Interval Value

Returns the current value of the periodic interval timer.

• PICNT: Periodic Interval Counter

Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

16. Watchdog Timer (WDT)

16.1 Overview

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode.

16.2 Block Diagram

Figure 16-1. Watchdog Timer Block Diagram

AT91SAM7SE512/256/32 Preliminary

WDT_CR WDRSTT

read WDT_SR or reset

write WDT_MR

WDT_MR

WDD

<= WDD

WDERR

set

reset

reload

WDT_MR

WDV

12-bit Down

Counter

Current

Value

WDUNF

reset

set

reload

1/128

SLCK

WDT_MR

WDRSTEN

wdt_fault

(to Reset Controller)

wdt_int

WDFIEN

WDT_MR

6222B–ATARM–26-Mar-07

16.3 Functional Description

The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It is supplied with VDDCORE. It restarts with initial values on processor reset.

The Watchdog is built around a 12-bit down counter, which is loaded with the value defined in the field WDV of the Mode Register (WDT_MR). The Watchdog Timer uses the Slow Clock divided by 128 to establish the maximum Watchdog period to be 16 seconds (with a typical Slow Clock of 32.768 kHz).

After a Processor Reset, the value of WDV is 0xFFF, corresponding to the maximum value of the counter with the external reset generation enabled (field WDRSTEN at 1 after a Backup Reset). This means that a default Watchdog is running at reset, i.e., at power-up. The user must either disable it (by setting the WDDIS bit in WDT_MR) if he does not expect to use it or must reprogram it to meet the maximum Watchdog period the application requires.

The Watchdog Mode Register (WDT_MR) can be written only once. Only a processor reset resets it. Writing the WDT_MR register reloads the timer with the newly programmed mode parameters.

In normal operation, the user reloads the Watchdog at regular intervals before the timer underflow occurs, by writing the Control Register (WDT_CR) with the bit WDRSTT to 1. The Watchdog counter is then immediately reloaded from WDT_MR and restarted, and the Slow Clock 128 divider is reset and restarted. The WDT_CR register is write-protected. As a result, writing WDT_CR without the correct hard-coded key has no effect. If an underflow does occur, the “wdt_fault” signal to the Reset Controller is asserted if the bit WDRSTEN is set in the Mode Register (WDT_MR). Moreover, the bit WDUNF is set in the Watchdog Status Register (WDT_SR).

To prevent a software deadlock that continuously triggers the Watchdog, the reload of the Watchdog must occur while the Watchdog counter is within a window between 0 and WDD, WDD is defined in the WatchDog Mode Register WDT_MR.

Any attempt to restart the Watchdog while the Watchdog counter is between WDV and WDD results in a Watchdog error, even if the Watchdog is disabled. The bit WDERR is updated in the WDT_SR and the “wdt_fault” signal to the Reset Controller is asserted.

Note that this feature can be disabled by programming a WDD value greater than or equal to the WDV value. In such a configuration, restarting the Watchdog Timer is permitted in the whole range [0; WDV] and does not generate an error. This is the default configuration on reset (the WDD and WDV values are equal).

The status bits WDUNF (Watchdog Underflow) and WDERR (Watchdog Error) trigger an interrupt, provided the bit WDFIEN is set in the mode register. The signal “wdt_fault” to the reset controller causes a Watchdog reset if the WDRSTEN bit is set as already explained in the reset controller programmer Datasheet. In that case, the processor and the Watchdog Timer are reset, and the WDERR and WDUNF flags are reset.

If a reset is generated or if WDT_SR is read, the status bits are reset, the interrupt is cleared, and the “wdt_fault” signal to the reset controller is deasserted.

Writing the WDT_MR reloads and restarts the down counter.

While the processor is in debug state or in idle mode, the counter may be stopped depending on the value programmed for the bits WDIDLEHLT and WDDBGHLT in the WDT_MR.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

Figure 16-2. Watchdog Behavior

AT91SAM7SE512/256/32 Preliminary

Watchdog Error

Watchdog Underflow

FFF

WDV

Forbidden

Window

WDD

Permitted

Window

Watchdog

Fault

Normal behavior

if WDRSTEN is 1

if WDRSTEN is 0

WDT_CR = WDRSTT

6222B–ATARM–26-Mar-07

16.4 Watchdog Timer (WDT) User Interface

Table 16-1. Watchdog Timer (WDT) Register Mapping

Offset Register Name Access Reset Value

0x00 Control Register WDT_CR Write-only -

0x04 Mode Register WDT_MR Read/Write Once 0x3FFF_2FFF

0x08 Status Register WDT_SR Read-only 0x0000_0000

16.4.1 Watchdog Timer Control Register Register Name:WDT_CR

Access Type: Write-only

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––WDRSTT

KEY

• WDRSTT: Watchdog Restart

0: No effect.

1: Restarts the Watchdog.

•KEY: Password

Should be written at value 0xA5. Writing any other value in this field aborts the write operation.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

16.4.2 Watchdog Timer Mode Register Register Name:WDT_MR

Access Type: Read/Write Once

31 30 29 28 27 26 25 24

– – WDIDLEHLT WDDBGHLT WDD

23 22 21 20 19 18 17 16

WDD

15 14 13 12 11 10 9 8

WDDIS

76543210

• WDV: Watchdog Counter Value

Defines the value loaded in the 12-bit Watchdog Counter.

• WDFIEN: Watchdog Fault Interrupt Enable

0: A Watchdog fault (underflow or error) has no effect on interrupt.

WDRPROC WDRSTEN WDFIEN WDV

WDV

1: A Watchdog fault (underflow or error) asserts interrupt.

• WDRSTEN: Watchdog Reset Enable

0: A Watchdog fault (underflow or error) has no effect on the resets.

1: A Watchdog fault (underflow or error) triggers a Watchdog reset.

• WDRPROC: Watchdog Reset Processor

0: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates all resets.

1: If WDRSTEN is 1, a Watchdog fault (underflow or error) activates the processor reset.

• WDD: Watchdog Delta Value

Defines the permitted range for reloading the Watchdog Timer.

If the Watchdog Timer value is less than or equal to WDD, writing WDT_CR with WDRSTT = 1 restarts the timer.

If the Watchdog Timer value is greater than WDD, writing WDT_CR with WDRSTT = 1 causes a Watchdog error.

• WDDBGHLT: Watchdog Debug Halt

0: The Watchdog runs when the processor is in debug state.

1: The Watchdog stops when the processor is in debug state.

• WDIDLEHLT: Watchdog Idle Halt

0: The Watchdog runs when the system is in idle mode.

1: The Watchdog stops when the system is in idle state.

6222B–ATARM–26-Mar-07

• WDDIS: Watchdog Disable

0: Enables the Watchdog Timer.

1: Disables the Watchdog Timer.

16.4.3 Watchdog Timer Status Register Register Name:WDT_SR

Access Type: Read-only

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 ––––––WDERRWDUNF

• WDUNF: Watchdog Underflow

0: No Watchdog underflow occurred since the last read of WDT_SR.

1: At least one Watchdog underflow occurred since the last read of WDT_SR.

• WDERR: Watchdog Error

0: No Watchdog error occurred since the last read of WDT_SR.

1: At least one Watchdog error occurred since the last read of WDT_SR.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

17. Voltage Regulator Mode Controller (VREG)

17.1 Overview

The Voltage Regulator Mode Controller contains one Read/Write register, the Voltage Regulator Mode Register. Its offset is 0x60 with respect to the System Controller offset.

This register controls the Voltage Regulator Mode. Setting PSTDBY (bit 0) puts the Voltage Regulator in Standby Mode or Low-power Mode. On reset, the PSTDBY is reset, so as to wake up the Voltage Regulator in Normal Mode.

6222B–ATARM–26-Mar-07

17.2 Voltage Regulator Power Controller (VREG) User Interface

Table 17-1. Voltage Regulator Power Controller Register Mapping

Offset Register Name Access Reset Value

0x60 Voltage Regulator Mode Register VREG_MR Read/Write 0x0

17.2.1 Voltage Regulator Mode Register Register Name:VREG_MR

Access Type:Read/Write

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––PSTDBY

• PSTDBY: Periodic Interval Value

0 = Voltage regulator in normal mode.

1 = Voltage regulator in standby mode (low-power mode).

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

18. Memory Controller (MC)

18.1 Overview

The Memory Controller (MC) manages the ASB bus and controls accesses requested by the masters, typically the ARM7TDMI processor and the Peripheral DMA Controller. It features a simple bus arbiter, an address decoder, an abort status, a misalignment detector and an Embedded Flash Controller. In addition, the MC contains a Memory Protection Unit (MPU) consisting of 16 areas that can be protected against write and/or user accesses. Access to peripherals can be protected in the same way.

18.2 Block Diagram

Figure 18-1. Memory Controller Block Diagram

Memory Controller

AT91SAM7SE512/256/32 Preliminary

ASB

ARM7TDMI

Processor

Peripheral

DMA

Controller

Abort

Bus

Arbiter

Abort

Status

Misalignment

Detector

Memory

Protection

Unit

User

Interface

Decoder

APB

Bridge

Embedded

Flash

Controller

Address

Internal

Flash

Internal

RAM

External

Bus

Interface

6222B–ATARM–26-Mar-07

Peripheral 0

Peripheral 1

Peripheral N

APB

From Master

to Slave

18.3 Functional Description

The Memory Controller handles the internal ASB bus and arbitrates the accesses of both masters.

It is made up of:

• A bus arbiter

• An address decoder

• An abort status

• A misalignment detector

• A memory protection unit

• An Embedded Flash Controller

The MC handles only little-endian mode accesses. The masters work in little-endian mode only.

18.3.1 Bus Arbiter

The Memory Controller has a simple, hard-wired priority bus arbiter that gives the control of the bus to one of the two masters. The Peripheral Data Controller has the highest priority; the ARM processor has the lowest one.

18.3.2 Address Decoder

The Memory Controller features an Address Decoder that first decodes the four highest bits of the 32-bit address bus and defines 11 separate areas:

• One 256-Mbyte address space for the internal memories

• Eight 256-Mbyte address spaces, each assigned to one of the eight chip select lines of the External Bus Interface

• One 256-Mbyte address space reserved for the embedded peripherals

• An undefined address space of 1536M bytes that returns an Abort if accessed

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

18.4 External Memory Areas

Figure 18-2 shows the assignment of the 256-Mbyte memory areas.

Figure 18-2. External Memory Areas

AT91SAM7SE512/256/32 Preliminary

256M Bytes

6 x 256M Bytes

1,536 bytes

256M Bytes

0x0000 0000

0x0FFF FFFF

0x1000 0000

0x1FFF FFFF

0x2000 0000

0x2FFF FFFF

0x3000 0000

0x3FFF FFFF

0x4000 0000

0x4FFF FFFF

0x5000 0000

0x5FFF FFFF

0x6000 0000

0x6FFF FFFF

0x7000 0000

0x7FFF FFFF

0x8000 0000

0x8FFF FFFF

0x9000 0000

0xEFFF FFFF

0xF000 0000

0xFFFF FFFF

Internal Memories

Chip Select 0

Chip Select 1

Chip Select 2

Chip Select 3

Chip Select 4

Chip Select 5

Chip Select 6

Chip Select 7

Undefined

(Abort)

Peripherals

EBI

External

Bus

Interface

18.4.1 Internal Memory Mapping

Within the Internal Memory address space, the Address Decoder of the Memory Controller decodes eight more address bits to allocate 1-Mbyte address spaces for the embedded memories.

The allocated memories are accessed all along the 1-Mbyte address space and so are repeated n times within this address space, n equaling 1M bytes divided by the size of the memory.

When the address of the access is undefined within the internal memory area, the Address Decoder returns an Abort to the master.

6222B–ATARM–26-Mar-07

Figure 18-3. Internal Memory Mapping

18.4.2 Internal Memory Area 0

The first 32 bytes of Internal Memory Area 0 contain the ARM processor exception vectors, in particular, the Reset Vector at address 0x0.

Before execution of the remap command, the internal ROM or the on-chip Flash is mapped into Internal Memory Area 0, so that the ARM7TDMI reaches an executable instruction contained in Flash. A general purpose bit (GPNVM Bit 2) is used to boot either on the ROM (default) or from the Flash.

256M Bytes

0x0000 0000

0x000F FFFF

0x0010 0000

0x001F FFFF

0x0020 0000

0x002F FFFF

0x0030 0000

0x003F FFFF

0x0040 0000

0x0FFF FFFF

Internal Memory Area 0

Internal Memory Area 1

Internal Flash

Internal Memory Area 2

Internal SRAM

Internal Memory Area 3

Internal ROM

Undefined Areas

(Abort)

1 M Bytes

252 M Bytes

Setting the GPNVM Bit 2 selects the boot from the Flash, clearing it selects the boot from the ROM. Asserting ERASE clears the GPNVM Bit 2 and thus selects the boot from the ROM by default.

After the remap command, the internal SRAM at address 0x0020 0000 is mapped into Internal Memory Area 0. The memory mapped into Internal Memory Area 0 is accessible in both its original location and at address 0x0.

18.4.3 Remap Command

After execution, the Remap Command causes the Internal SRAM to be accessed through the Internal Memory Area 0.

As the ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, and Fast Interrupt) are mapped from address 0x0 to address 0x20, the Remap Command allows the user to redefine dynamically these vectors under software control.

The Remap Command is accessible through the Memory Controller User Interface by writing the MC_RCR (Remap Control Register) RCB field to one.

The Remap Command can be cancelled by writing the MC_RCR RCB field to one, which acts as a toggling command. This allows easy debug of the user-defined boot sequence by offering a simple way to put the chip in the same configuration as after a reset.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

18.4.4 Abort Status

AT91SAM7SE512/256/32 Preliminary

There are three reasons for an abort to occur:

• access to an undefined address

• access to a protected area without the permitted state

• an access to a misaligned address.

When an abort occurs, a signal is sent back to all the masters, regardless of which one has generated the access. However, only the ARM7TDMI can take an abort signal into account, and only under the condition that it was generating an access. The Peripheral Data Controller does not handle the abort input signal. Note that the connection is not represented in Figure 18-1.

To facilitate debug or for fault analysis by an operating system, the Memory Controller integrates an Abort Status register set.

The full 32-bit wide abort address is saved in MC_AASR. Parameters of the access are saved in MC_ASR and include:

• the size of the request (field ABTSZ)

• the type of the access, whether it is a data read or write, or a code fetch (field ABTTYP)

• whether the access is due to accessing an undefined address (bit UNDADD), a misaligned address (bit MISADD) or a protection violation (bit MPU)

• the source of the access leading to the last abort (bits MST0 and MST1)

• whether or not an abort occurred for each master since the last read of the register (bit SVMST0 and SVMST1) unless this information is loaded in MST bits

In the case of a Data Abort from the processor, the address of the data access is stored. This is useful, as searching for which address generated the abort would require disassembling the instructions and full knowledge of the processor context.

In the case of a Prefetch Abort, the address may have changed, as the prefetch abort is pipelined in the ARM processor. The ARM processor takes the prefetch abort into account only if the read instruction is executed and it is probable that several aborts have occurred during this time. Thus, in this case, it is preferable to use the content of the Abort Link register of the ARM processor.

18.4.5 Memory Protection Unit

The Memory Protection Unit allows definition of up to 16 memory spaces within the internal memories. Note that the external memories can not be protected.

After reset, the Memory Protection Unit is disabled. Enabling it requires writing the Protection Unit Enable Register (MC_PUER) with the PUEB at 1.

Programming of the 16 memory spaces is done in the registers MC_PUIA0 to MC_PUIA15.

The size of each of the memory spaces is programmable by a power of 2 between 1K bytes and 4M bytes. The base address is also programmable on a number of bits according to the size.

The Memory Protection Unit also allows the protection of the peripherals by programming the Protection Unit Peripheral Register (MC_PUP) with the field PROT at the appropriate value.

The peripheral address space and each internal memory area can be protected against write and non-privileged access of one of the masters. When one of the masters performs a forbidden access, an Abort is generated and the Abort Status traces what has happened.

6222B–ATARM–26-Mar-07

There is no priority in the protection of the memory spaces. In case of overlap between several memory spaces, the strongest protection is taken into account. If an access is performed to an address which is not contained in any of the 16 memory spaces, the Memory Protection Unit generates an abort.

The reset value of MC_PUIAx registers is 0, which blocks all access to the first 1K of memory starting at address 0, which prevents the core from reading exception vectors. Therefore, all

regions must be programmed to allow read/write access on the first 4M Bytes of the memory range during MPU initialization.

18.4.6 Embedded Flash Controller

The Embedded Flash Controller is added to the Memory Controller and ensures the interface of the flash block with the 32-bit internal bus. It allows an increase of performance in Thumb Mode for Code Fetch with its system of 32-bit buffers. It also manages with the programming, erasing, locking and unlocking sequences thanks to a full set of commands.

18.4.7 Misalignment Detector

The Memory Controller features a Misalignment Detector that checks the consistency of the accesses.

For each access, regardless of the master, the size of the access and the bits 0 and 1 of the address bus are checked. If the type of access is a word (32-bit) and the bits 0 and 1 are not 0, or if the type of the access is a half-word (16-bit) and the bit 0 is not 0, an abort is returned to the master and the access is cancelled. Note that the accesses of the ARM processor when it is fetching instructions are not checked.

The misalignments are generally due to software bugs leading to wrong pointer handling. These bugs are particularly difficult to detect in the debug phase.

As the requested address is saved in the Abort Status Register and the address of the instruction generating the misalignment is saved in the Abort Link Register of the processor, detection and fix of this kind of software bugs is simplified.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

18.5 Memory Controller (MC) User Interface

Base Address: 0xFFFFFF00

Table 18-1. Memory Controller (MC) Memory Mapping

Offset Register Name Access Reset State

0x00 MC Remap Control Register MC_RCR Write-only

0x04 MC Abort Status Register MC_ASR Read-only 0x0

0x08 MC Abort Address Status Register MC_AASR Read-only 0x0

0x0C Reserved

0x10 MC Protection Unit Area 0 MC_PUIA0 Read/Write 0x0

0x14 MC Protection Unit Area 1 MC_PUIA1 Read/Write 0x0

0x18 MC Protection Unit Area 2 MC_PUIA2 Read/Write 0x0

0x1C MC Protection Unit Area 3 MC_PUIA3 Read/Write 0x0

0x20 MC Protection Unit Area 4 MC_PUIA4 Read/Write 0x0

0x24 MC Protection Unit Area 5 MC_PUIA5 Read/Write 0x0

0x28 MC Protection Unit Area 6 MC_PUIA6 Read/Write 0x0

0x2C MC Protection Unit Area 7 MC_PUIA7 Read/Write 0x0

0x30 MC Protection Unit Area 8 MC_PUIA8 Read/Write 0x0

0x34 MC Protection Unit Area 9 MC_PUIA9 Read/Write 0x0

0x38 MC Protection Unit Area 10 MC_PUIA10 Read/Write 0x0

0x3C MC Protection Unit Area 11 MC_PUIA11 Read/Write 0x0

0x40 MC Protection Unit Area 12 MC_PUIA12 Read/Write 0x0

0x44 MC Protection Unit Area 13 MC_PUIA13 Read/Write 0x0

0x48 MC Protection Unit Area 14 MC_PUIA14 Read/Write 0x0

0x4C MC Protection Unit Area 15 MC_PUIA15 Read/Write 0x0

0x50 MC Protection Unit Peripherals MC_PUP Read/Write 0x0

0x54 MC Protection Unit Enable Register MC_PUER Read/Write 0x0

0x60 EFC0 Configuration Registers See EFC0 User Interface

0x70 EFC1 Configuration Registers See EFC1 User Interface

0x80 External bus Interface Registers See EBI User Interface

0x90 SMC Configuration Registers See SMC User Interface

0xB0 SDRAMC Configuration Registers See SDRAMC User Interface

0xDC ECC Configuration Registers See ECC User Interface

6222B–ATARM–26-Mar-07

18.5.1 MC Remap Control Register Register Name: MC_RCR

Access Type:Write-only Absolute Address: 0xFFFF FF00

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

––––––––

15 14 13 12 11 10 9 8

––––––––

76543210 –––––––RCB

• RCB: Remap Command Bit

0: No effect.

1: This Command Bit acts on a toggle basis: writing a 1 alternatively cancels and restores the remapping of the page zero memory devices.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

AT91SAM7SE512/256/32 Preliminary

18.5.2 MC Abort Status Register Register Name: MC_ASR

Access Type: Read-only Reset Value:0x0 Absolute Address: 0xFFFF FF04

31 30 29 28 27 26 25 24

––––––SVMST1SVMST0

23 22 21 20 19 18 17 16

––––––MST1MST0

15 14 13 12 11 10 9 8

– – – – ABTTYP ABTSZ

76543210 –––––MPUMISADDUNDADD

• UNDADD: Undefined Address Abort Status

0: The last abort was not due to the access of an undefined address in the address space.

1: The last abort was due to the access of an undefined address in the address space.

• MISADD: Misaligned Address Abort Status

0: The last aborted access was not due to an address misalignment.

1: The last aborted access was due to an address misalignment.

• MPU: Memory Protection Unit Abort Status

0: The last aborted access was not due to the Memory Protection Unit.

1: The last aborted access was due to the Memory Protection Unit.

• ABTSZ: Abort Size Status

ABTSZ Abort Size

00 Byte

0 1 Half-word

10 Word

11 Reserved

• ABTTYP: Abort Type Status

ABTTYP Abort Type

0 0 Data Read

0 1 Data Write

1 0 Code Fetch

11 Reserved

6222B–ATARM–26-Mar-07

• MST0: ARM7TDMI Abort Source

0: The last aborted access was not due to the ARM7TDMI.

1: The last aborted access was due to the ARM7TDMI.

• MST1: PDC Abort Source

0: The last aborted access was not due to the PDC.

1: The last aborted access was due to the PDC.

• SVMST0: Saved ARM7TDMI Abort Source

0: No abort due to the ARM7TDMI occurred since the last read of MC_ASR or it is notified in the bit MST0.

1: At least one abort due to the ARM7TDMI occurred since the last read of MC_ASR.

• SVMST1: Saved PDC Abort Source

0: No abort due to the PDC occurred since the last read of MC_ASR or it is notified in the bit MST1.

1: At least one abort due to the PDC occurred since the last read of MC_ASR.

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

18.5.3 MC Abort Address Status Register Register Name: MC_AASR

Access Type: Read-only Reset Value:0x0

AT91SAM7SE512/256/32 Preliminary

Absolute Address: 0xFFFF FF08

31 30 29 28 27 26 25 24

23 22 21 20 19 18 17 16

15 14 13 12 11 10 9 8

76543210

• ABTADD: Abort Address

This field contains the address of the last aborted access.

ABTADD

6222B–ATARM–26-Mar-07

18.5.4 MC Protection Unit Area 0 to 15 Registers Register Name: MC_PUIA0 - MC_PUIA15

Access Type: Read/Write Reset Value:0x0 Absolute Address: 0xFFFFFF10 - 0xFFFFFF4C

31 30 29 28 27 26 25 24

––––––––

23 22 21 20 19 18 17 16

–– BA

15 14 13 12 11 10 9 8

BA – –

76543210

SIZE – – PROT

•PROT: Protection

Processor Mode

PROT

0 0 No access No access

0 1 Read/Write No access

1 0 Read/Write Read-only

1 1 Read/Write Read/Write

Privilege User

• SIZE: Internal Area Size

SIZE Area Size LSB of BA

00001 KB 10

00012 KB 11

00104 KB 12

00118 KB 13

010016 KB 14

010132 KB 15

011064 KB 16

0111128 KB 17

1000256 KB 18

1001512 KB 19

10101 MB 20

10112 MB 21

11014 MB 22

• BA: Internal Area Base Address

These bits define the Base Address of the area. Note that only the most significant bits of BA are significant. The number of significant bits are in respect with the size of the area.

100

AT91SAM7SE512/256/32 Preliminary

6222B–ATARM–26-Mar-07

Datasheet AT91SAM7SE512, AT91SAM7SE256, AT91SAM7SE32 Datasheet (ATMEL)

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Description

1.1 Configuration Summary of the AT91SAM7SE512, AT91SAM7SE256 and AT91SAM7SE32

2. Block Diagram

3. Signal Description

4. Package

4.1 128-lead LQFP Package Outline

4.2 128-lead LQFP Pinout

4.3 144-ball LFBGA Package Outline

4.4 144-ball LFBGA Pinout

5. Power Considerations

5.1 Power Supplies

5.2 Power Consumption

5.3 Voltage Regulator

5.4 Typical Powering Schematics

6. I/O Lines Considerations

6.1 JTAG Port Pins

6.2 Test Pin

6.3 Reset Pin

6.4 ERASE Pin

6.5 SDCK Pin

6.6 PIO Controller lines

6.7 I/O Lines Current Drawing

7. Processor and Architecture

7.1 ARM7TDMI Processor

7.2 Debug and Test Features

7.3 Memory Controller

7.4 External Bus Interface

7.5 Static Memory Controller

7.6 SDRAM Controller

7.7 Error Corrected Code Controller

7.8 Peripheral DMA Controller

8. Memories

8.1 Embedded Memories

8.1.1 Internal Memories

8.1.1.1 Internal SRAM

8.1.1.2 Internal ROM

8.1.1.3 Internal Flash

8.1.2 Embedded Flash

8.1.2.1 Flash Overview

8.1.2.2 Embedded Flash Controller

8.1.2.3 Lock Regions

8.1.2.4 Security Bit Feature

8.1.2.5 Non-volatile Brownout Detector Control

8.1.2.6 Calibration Bits

8.1.3 Fast Flash Programming Interface

8.1.4 SAM-BA™ Boot

8.2 External Memories

9. System Controller

9.1 Reset Controller

9.1.1 Brownout Detector and Power On Reset

9.2 Clock Generator

9.3 Power Management Controller

9.4 Advanced Interrupt Controller

9.5 Debug Unit

9.6 Periodic Interval Timer

9.7 Watchdog Timer

9.8 Real-time Timer

9.9 PIO Controllers

9.10 Voltage Regulator Controller

10. Peripherals

10.1 User Interface

10.2 Peripheral Identifiers

10.3 Peripheral Multiplexing on PIO Lines

10.4 PIO Controller A Multiplexing

10.5 PIO Controller B Multiplexing

10.6 PIO Controller C Multiplexing

10.7 Serial Peripheral Interface

10.8 Two Wire Interface

10.9 USART

10.10 Serial Synchronous Controller

10.11 Timer Counter

10.12 PWM Controller

10.13 USB Device Port

10.14 Analog-to-Digital Converter

11. ARM7TDMI Processor Overview