Atmel AT91M55800A User Manual

Features

• Utilizes the ARM7TDMI

– High-performance 32-bit RISC Architecture – High-density 16-bit Instruction Set – Leader in MIPS/Watt – Embedded ICE (In-Circuit Emulation)

• 8K Bytes Internal SRAM

• Fully-programmable External Bus Interface (EBI)

– Maximum External Address Space of 128M Bytes – Eight Chip Selects – Software Programmable 8/16-bit External Databus

• 8-level Priority, Individually Maskable, Vectored Interrupt Controller

– Seven External Interrupts, Including a High-priority, Low-latency Interrupt Request

• Fifty-eight Programmable I/O Lines

• 6-channel 16-bit Timer/Counter

– Six External Clock Inputs and Two Multi-purpose I/O Pins per Channel

• Three USARTs

• Master/Slave SPI Interface

– 8-bit to 16-bit Programmable Data Length – Four External Slave Chip Selects

• Programmable Watchdog Timer

• 8-channel 10-bit ADC

• 2-channel 10-bit DAC

• Clock Generator with On-chip Main Oscillator and PLL for Multiplication

– 3 to 20 MHz Frequency Range Main Oscillator

• Real-time Clock with On-chip 32 kHz Oscillator

– Battery Backup Operation and External Alarm

• 8-channel Peripheral Data Controller for USARTs and SPIs

• Advanced Power Management Controller (APMC)

– Normal, Wait, Slow, Standby and Power-down modes

• IEEE 1149.1 JTAG Boundary-scan on all Digital Pins

• Fully Static Operation: 0 Hz to 33 MHz

• 2.7V to 3.6V Core Operating Range

• 2.7V to 5.5V I/O Operating Range

• 2.7V to 3.6V Analog Operating Range

• 1.8V to 3.6V Backup Battery Operating Range

• 2.7V to 3.6V Oscillator and PLL Operating Range

• -40°C to +85°C Temperature Range

• Available in a 176-lead LQFP or 176-ball BGA Package

ARM® Thumb® Processor Core

AT91 ARM

Thumb®

Microcontrollers

AT91M55800A

1. Description

The AT91M55800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications.

The fully programmable External Bus Interface provides a direct connection to off-chip memory in as fast as one clock cycle for a read or write operation. An eight-level prior-

Rev. 1745D–ATARM–04-Nov-05

ity vectored interrupt controller in conjunction with the peripheral data controller significantly improve the real-time performance of the device.

The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with an on-chip SRAM, a wide range of peripheral functions, analog interfaces and low-power oscillators on a monolithic chip, the Atmel AT91M55800A is a powerful microcontroller that provides a highly-flexible and cost-effective solution to many ultra low-power applications.

AT91M55800A

1745D–ATARM–04-Nov-05

AT91M55800A

2. Pin Configurations

Table 2-1. Pin Configuration for 176-lead LQFP Package

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

1 GND 45 GND 89 GND 133 GND 2 GND 46 GND 90 GND 134 GND 3 NCS0 47 D8 91 PA19/RXD1 135 NCS4 4 NCS1 48 D9 92 PA20/SCK2 136 NCS5 5 NCS2 49 D10 93 PA21/TXD2 137 NCS6 6 NCS3 50 D11 94 PA22/RXD2 138 NCS7 7 NLB/A0 51 D12 95 PA23/SPCK 139 PB0 8 A1 52 D13 96 PA24/MISO 140 PB1

9 A2 53 D14 97 PA25/MOSI 141 PB2 10 A3 54 D15 98 PA26/NPCS0/NSS 142 PB3/IRQ4 11 A4 55 PB19/TCLK0 99 PA27/NPCS1 143 PB4/IRQ5 12 A5 56 PB20/TIOA0 100 PA28/NPCS2 144 PB5 13 A6 57 PB21/TIOB0 101 PA29/NPCS3 145 PB6/AD0TRIG 14 A7 58 PB22/TCLK1 102 VDDIO 146 PB7/AD1TRIG 15 VDDIO 59 VDDIO 103 GND 147 VDDIO 16 GND 60 GND 104 VDDPLL 148 GND 17 A8 61 PB23/TIOA1 105 XIN 149 PB8 18 A9 62 PB24/TIOB1 106 XOUT 150 PB9 19 A10 63 PB25/TCLK2 107 GNDPLL 151 PB10 20 A11 64 PB26/TIOA2 108 PLLRC 152 PB11 21 A12 65 PB27/TIOB2 109 VDDBU 22 A13 66 PA0/TCLK3 110 XIN32 23 A14 67 PA1/TIOA3 111 XOUT32 24 A15 68 PA2/TIOB3 112 NRSTBU 25 A16 69 PA3/TCLK4 113 GNDBU 26 A17 70 PA4/TIOA4 114 WAKEUP 27 A18 71 PA5/TIOB4 115 SHDN 28 A19 72 PA6/TCLK5 116 GNDBU 29 VDDIO 73 VDDIO 117 VDDA 30 GND 74 GND 118 AD0 31 A20 75 PA7/TIOA5 119 AD1 32 A21 76 PA8/TIOB5 120 AD2 33 A22 77 PA9/IRQ0 121 AD3 34 A23 78 PA10/IRQ1 122 AD4 35 D0 79 PA11/IRQ2 123 AD5 36 D1 80 PA12/IRQ3 124 AD6 37 D2 81 PA13/FIQ 125 AD7 38 D3 82 PA14/SCK0 126 ADVREF 39 D4 83 PA15/TXD0 127 DAVREF 40 D5 84 PA16/RXD0 128 DA0 41 D6 85 PA17/SCK1 129 DA1 42 D7 86 PA18/TXD1/NTRI 130 GNDA 43 VDDCORE 87 VDDCORE 131 VDDCORE 175 VDDCORE 44 VDDIO 88 VDDIO 132 VDDIO 176 VDDIO

Notes: 1. Analog pins

2. Battery backup pins

(2)

(1)

153 PB12 154 PB13 155 PB14 156 PB15 157 PB16 158 PB17 159 NWDOVF 160 MCKO 161 VDDIO 162 GND 163 PB18/BMS 164 JTAGSEL 165 TMS 166 TDI 167 TDO 168 TCK 169 NTRST 170 NRST 171 NWAIT 172 NOE/NRD 173 NWE/NWR0 174 NUB/NWR1

1745D–ATARM–04-Nov-05

Table 2-2. Pin Configuration for 176-ball BGA Package

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

A1 NCS1 C1 A0/NLB E1 A4 G1 A12

A2 NWAIT C2 NCS0 E2 A3 G2 A9

A3 NRST C3 VDDIO E3 A5 G3 A8

A4 NTRST C4 VDDCORE E4 GND G4 GND

A5 PB18/BMS C5 TMS E5 – G5 –

A6 NWDOVF C6 VDDIO E6 – G6 –

A7 PB16 C7 MCK0 E7 – G7 –

A8 PB12 C8 PB13 E8 – G8 –

A9 PB10 C9 PB6/AD0TRIG E9 – G9 –

A10 PB9 C10 VDDIO E10 – G10 –

A11 PB8 C11 PB4/IRQ5 E11 – G11 –

A12 NCS7 C12 PB0 E12 AD6 G12 AD3

A13 NCS6 C13 VDDIO E13 AD5 G13 AD2

A14 GND C14 DA0 E14 NRSTBU G14 GND

A15 DAVREF C15 ADVREF E15 GNDBU G15 XIN32

B1 NCS2 D1 A2 F1 A10 H1 A15

B2 NUB/NWR1 D2 A1 F2 A7 H2 A14

B3 NWE/NWR0 D3 NCS3 F3 VDDIO H3 A13

B4 NOE/NRD D4 GND F4 A6 H4 A11

B5 TD0 D5 TCK F5 – H5 –

B6 TDI D6 JTAGSEL F6 – H6 –

B7 PB17 D7 GND F7 – H7 –

B8 PB11 D8 PB15 F8 – H8 –

B9 PB7/AD1TRIG D9 PB14 F9 – H9 –

B10 PB3/IRQ4 D10 PB5 F10 – H10 –

B11 PB2 D11 PB1 F11 – H11 –

B12 NCS5 D12 GND F12 GND H12 AD1

B13 NCS4 D13 VDDCORE F13 AD4 H13 AD0

B14 DA1 D14 AD7 F14 VDDBU H14 WAKEUP

B15 GNDA D15 VDDA F15 XOUT32 H15 GND

AT91M55800A

1745D–ATARM–04-Nov-05

AT91M55800A

Table 2-2. Pin Configuration for 176-ball BGA Package (Continued)

Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A Pin AT91M55800A

J1 A17 L1 A20 N1 D4 R1 D10

J2 A18 L2 A23 N2 D6 R2 D11

J3 VDDIO L3 D0 N3 VDDIO R3 D12

J4 A16 L4 D1 N4 D14 R4 D13

J5 – L5 – N5 PB19/TCLK0 R5 PB20/TIOA0

J6 – L6 – N6 VDDIO R6 PB23/TIOA1

J7 – L7 – N7 PB25/TCLK2 R7 PB24/TIOB1

J8 – L8 – N8 PA1/TIOA3 R8 PA3/TCLK4

J9 – L9 – N9 VDDIO R9 PA4/TIOA4

J10 – L10 – N10 PA8/TIOB5 R10 PA5/TIOB4

J11 – L11 – N11 PA9/IRQ0 R11 PA6/TCLK5

J12 PA29/NPCS3 L12 PA25/MOSI N12 VDDCORE R12 PA12/IRQ3

J13 SHDN L13 PA22RXD2 N13 VDDIO R13 PA14/SCK0

J14 VDDPLL L14 PA26/NPCS0/NSS N14 PA19/RXD1 R14 PA15/TXD0

J15 PLLRC L15 XOUT N15 GND R15 PA16/RXD0

K1 A19 M1 D2 P1 D5

K2 A22 M2 D3 P2 D7

K3 A21 M3 VDDCORE P3 D8

K4 GND M4 GND P4 D9

K5 – M5 GND P5 D15

K6 – M6 PB21/TIOB0 P6 PB22/TCLK1

K7 – M7 GND P7 PB26/TIOA2

K8 – M8 PB27/TIOB2 P8 PA2/TIOB3

K9 – M9 PA0/TCLK3 P9 PA7/TIOA5

K10 – M10 GND P10 PA10/IRQ1

K11 – M11 PA23/SPCK P11 PA11/IRQ2

K12 PA28/NPCS2 M12 GND P12 PA13/FIQ

K13 VDDIO M13 PA21/TXD2 P13 PA17SCK1

K14 PA27/NPCS1 M14 PA24/MISO P14 PA18/TXD1/NTRI

K15 GNDPLL M15 XIN P15 PA20/SCK2

1745D–ATARM–04-Nov-05

Figure 2-1. 176-lead LQFP Pinout

132 89

133

176

Figure 2-2. 176-ball BGA Pinout

123456789101112

144

13 14 15

AT91M55800A

1745D–ATARM–04-Nov-05

3. Pin Description

Table 3-1. Pin Description

Module Name Function Type

A0 - A23 Address bus Output –

D0 - D15 Data bus I/O –

NCS0 - NCS7 Chip select Output Low

NWR0 Lower byte 0 write signal Output Low Used in Byte-write option

NWR1 Lower byte 1 write signal Output Low Used in Byte-write option

EBI

AIC

Timer

NRD Read signal Output Low Used in Byte-write option

NWE Write enable Output Low Used in Byte-select option

NOE Output enable Output Low Used in Byte-select option

NUB Upper byte-select Output Low Used in Byte-select option

NLB Lower byte-select Output Low Used in Byte-select option

NWAIT Wait input Input Low

BMS Boot mode select Input – Sampled during reset

IRQ0 - IRQ5 External interrupt request Input – PIO-controlled after reset

FIQ Fast external interrupt request Input – PIO-controlled after reset

TCLK0 - TCLK5 Timer external clock Input – PIO-controlled after reset

TIOA0 - TIOA5 Multipurpose timer I/O pin A I/O – PIO-controlled after reset

AT91M55800A

Active

Level Comments

TIOB0 - TIOB5 Multipurpose timer I/O pin B I/O – PIO-controlled after reset

SCK0 - SCK2 External serial clock I/O – PIO-controlled after reset

USART

SPI

PIO

WD NWDOVF Watchdog timer overflow Output Low Open drain

ADC

TXD0 - TXD2 Transmit data output Output – PIO-controlled after reset

RXD0 - RXD2 Receive data input Input – PIO-controlled after reset

SPCK SPI clock I/O – PIO-controlled after reset

MISO Master in slave out I/O – PIO-controlled after reset

MOSI Master out slave in I/O – PIO-controlled after reset

NSS Slave select Input Low PIO-controlled after reset

NPCS0 - NPCS3 Peripheral chip select Output Low PIO-controlled after reset

PA0 - PA29 Parallel I/O port A I/O – Input after reset

PB0 - PB27 Parallel I/O port B I/O – Input after reset

AD0-AD7 Analog input channels 0 - 7 Analog in –

AD0TRIG ADC0 external trigger Input – PIO-controlled after reset

AD1TRIG ADC1 external trigger Input – PIO-controlled after reset

ADVREF Analog reference Analog ref –

1745D–ATARM–04-Nov-05

Table 3-1. Pin Description (Continued)

Module Name Function Type

DAC

Clock

APMC

Reset

JTAG/ICE

DA0 - DA1 Analog output channels 0 - 1 Analog out –

DAVREF Analog reference Analog ref –

XIN Main oscillator input Input –

XOUT Main oscillator output Output –

PLLRC RC filter for PLL Input –

XIN32 32 kHz oscillator input Input –

XOUT32 32 kHz oscillator output Output –

MCKO System clock Output –

WAKEUP Wakeup request Input –

SHDN Shutdown request Output – Tri-state after backup reset

NRST Hardware reset input Input Low Schmidt trigger

NRSTBU

NTRI Tri-state mode select Input Low Sampled during reset

JTAGSEL

TMS Test mode select Input – Schmidt trigger, internal pull-up

TDI Test data input Input – Schmidt trigger, internal pull-up

TDO Test data output Output –

TCK Test clock Input – Schmidt trigger, internal pull-up

NTRST Test reset input Input Low Schmidt trigger, internal pull-up

Hardware reset input for battery part

Selects between ICE and JTAG mode

Input Low Schmidt trigger

Input –

Active

Level Comments

Power

VDDA Analog power Analog pwr –

GNDA Analog ground Analog gnd –

VDDBU Power backup Power –

GNDBU Ground backup Ground –

VDDCORE Digital core power Power –

VDDIO Digital I/O power Power –

VDDPLL Main oscillator and PLL power Power –

GND Digital ground Ground –

GNDPLL PLL ground Ground –

AT91M55800A

1745D–ATARM–04-Nov-05

4. Block Diagram

AT91M55800A

JTAGSEL

NTRST

TMS TDO

PB10 PB11 PB12 PB13 PB14 PB15 PB16

PB17 PB3/IRQ4 PB4/IRQ5 PA9/IRQ0

PA10/IRQ1 PA11/IRQ2 PA12/IRQ3

PA13/FIQ

PA14/SCK0 PA15/TXD0 PA16/RXD0

PA17/SCK1

PA18/TXD1/NTRI

PA19/RXD1

PA20/SCK2 PA21/TXD2 PA22/RXD2

PA23/SPCK

PA24/MISO PA25/MOSI

PA26/NPCS0/NSS

PA27/NPCS1 PA28/NPCS2 PA29/NPCS3

NWDOVF

VDDA

DA0

DAVREF

DA1

PB6/AD0TRIG

AD0 AD1 AD2 AD3

ADVREF

AD4 AD5 AD6 AD7

PB7/AD1TRIG

GNDA

TDI

TCK

PB0 PB1 PB2 PB5 PB8 PB9

XIN

16 MHz

XOUT

XIN32

32.768 kHz

XOUT32

NRST

VDDIO, VDDCORE

GND

D0 - D15 A1 - A23

A0/NLB NRD/NOE NWR0/NWE NWR1/NUB NWAIT NCS0 - NCS7

PB18/BMS

PB19/TCLK0 PB22/TCLK1 PB25/TCLK2

PB20/TIOA0 PB21/TIOB0

PB23/TIOA1 PB24/TIOB1

PB26/TIOA2 PB27/TIOB2

PA0/TCLK3 PA3/TCLK4 PA6/TCLK5

PA1/TIOA3 PA2/TIOB3

PA4/TIOA4 PA5/TIOB4

PA7/TIOA5 PA8/TIOB5

VDDPLL

MCKO

PLLRC

GNDPLL

VDDBU

SHDN WAKEUP

NRSTBU

GNDBU

Embedded

ICE

Reset

JTAGSEL

ARM7TDMI Core

JTAG

2 PDC

Channels

2 PDC

Channels

2 PDC

Channels

2 PDC

Channels

Chip ID

Internal RAM

8K Bytes

ASB

Controller

I O B

AIC:

Advanced

Interrupt

Controller

USART0

I O A

USART1

USART2

SPI: Serial Peripheral

Interface

PIOA Controller

WD: Watchdog Timer

DAC0

DAC1

4-Channel

ADC0

4-Channel

ADC1

Analog

ASB

AMBA Bridge

APB

EBI: External

Bus Interface

EBI User Interface

PIOB

Controller

TC: Timer

Counter

Block 0

TC0

TC1

TC2

TC: Timer

Counter

Block 1

TC3

TC4

TC5

Clock

Generator

PLL

APMC:

Advanced

Power

Management

Controller

RTC:

Real Time

Clock

Battery Backup

O B

O A

1745D–ATARM–04-Nov-05

5. Architectural Overview

The AT91M55800A microcontroller integrates an ARM7TDMI with its embedded ICE interface, memories and peripherals. Its architecture consists of two main buses, the Advanced System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and optimized for low power consumption.

The AT91M55800A microcontroller implements the ICE port of the ARM7TDMI processor on dedicated pins, offering a complete, low cost and easy-to-use debug solution for target debugging.

5.1 Memory

The AT91M55800A microcontroller embeds 8K bytes of internal SRAM. The internal memory is directly connected to the 32-bit data bus and is single-cycle accessible.

The AT91M55800A microcontroller features an External Bus Interface (EBI), which enables connection of external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling faster memory accesses than standard memory interfaces.

™

Bridge.

5.2 Peripherals

The AT91M55800A microcontroller integrates several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed with a minimum number of instructions. The peripheral register set is composed of control, mode, data, status and enable/disable/status registers.

An on-chip, 8-channel Peripheral Data Controller (PDC) transfers data between the on-chip USARTs/SPI and the on and off-chip memories without processor intervention. One PDC channel is connected to the receiving channel and one to the transmitting channel of each USART and of the SPI.

Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces the number of clock cycles required for a data transfer. It can transfer up to 64K contiguous bytes. As a result, the performance of the microcontroller is increased and the power consumption reduced.

5.2.1 System Peripherals

The External Bus Interface (EBI) controls the external memory and peripheral devices via an 8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own programming register.

The Advanced Power Management Controller (APMC) optimizes power consumption of the product by controlling the clocking elements such as the oscillators and the PLL, system and user peripheral clocks, and the power supplies.

The Advanced Interrupt Controller (AIC) controls the internal interrupt sources from the internal peripherals and the eight external interrupt lines (including the FIQ), to provide an interrupt and/or fast interrupt request to the ARM7TDMI. It integrates an 8-level priority controller and, using the Auto-vectoring feature, reduces the interrupt latency time.

AT91M55800A

1745D–ATARM–04-Nov-05

5.2.2 User Peripherals

AT91M55800A

The Real-time Clock (RTC) peripheral is designed for very low power consumption, and combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt.

The Parallel Input/Output Controllers (PIOA and PIOB) control the 58 I/O lines. They enable the user to select specific pins for on-chip peripheral input/output functions, and general-purpose input/output signal pins. The PIO controllers can be programmed to detect an interrupt on a signal change from each line.

The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a deadlock.

The Special Function (SF) module integrates the Chip ID and Reset Status registers.

Three USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 8 data bits. Each USART also features a Timeout and a Time Guard Register, facilitating the use of the two dedicated Peripheral Data Controller (PDC) channels.

The six 16-bit Timer/Counters (TC) are highly programmable and support capture or waveform modes. Each TC channel can be programmed to measure or generate different kinds of waves, and can detect and control two input/output signals. Each TC also has three external clock signals.

The SPI provides communication with external devices in master or slave mode. It has four external chip selects which can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bits.

The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Successive Approximation Register (SAR) approach.

1745D–ATARM–04-Nov-05

6. Associated Documentation

Table 6-1. Associated Documentation

Product Information Document Title

Internal architecture of processor

AT91M55800A

ARM/Thumb instruction sets Embedded in-circuit-emulator

External memory interface mapping Peripheral operations Peripheral user interfaces Ordering information Packaging information Soldering profile Errata

DC Characteristics Power consumption Thermal and reliability coniderations AC characteristics

Product overview Ordering information Packaging information Soldering profile

ARM7TDMI (Thumb) Datasheet 0673

AT91M55800A Datasheet (This document) 1745

AT91M55800A Electrical Characteristics 1727

AT91M55800A Summary Datasheet 1745S

Literature

Number

AT91M55800A

1745D–ATARM–04-Nov-05

7. Product Overview

7.1 Power Supplies

The AT91M55800A has 5 kinds of power supply pins:

• VDDCORE pins, which power the chip core

• VDDIO pins, which power the I/O Lines

• VDDPLL pins, which power the oscillator and PLL cells

• VDDA pins, which power the analog peripherals ADC and DAC

• VDDBU pins, which power the RTC, the 32768 Hz oscillator and the Shut-down Logic of

VDDIO and VDDCORE are separated to permit the I/O lines to be powered with 5V, thus resulting in full TTL compliance.

The following ground pins are provided:

• GND for both VDDCORE and VDDIO

• GNDPLL for VDDPLL

•GNDA for VDDA

• GNDBU for VDDBU

All of these ground pins must be connected to the same voltage (generally the board electric ground) with wires as short as possible. GNDPLL, GNDA and GNDBU are provided separately in order to allow the user to add a decoupling capacitor directly between the power and ground pads. In the same way, the PLL filter resistor and capacitors must be connected to the device and to GNDBU with wires as short as possible. Also, the main oscillator crystal and the 32768 Hz crystal external load capacitances must be connected respectively to GNDPLL and to GNDBU with wires as short as possible.

AT91M55800A

the APMC

The main constraints applying to the different voltages of the device are:

• VDDBU must be lower than or equal to VDDCORE

• VDDA must be higher than or equal to VDDCORE

• VDDCORE must be lower than or equal to VDDIO

The nominal power combinations supported by the AT91M55800A are described in the following table:

Table 7-1. Nominal Power Combinations

VDDIO VDDCORE VDDA VDDPLL VDDBU

3V 3V 3V 3V 3V 33 MHz

3.3V 3.3V 3.3V 3.3V 3.3V 33 MHz

5V 3.3V 3.3V 3.3V 3.3V 33 MHz

7.2 Input/Output Considerations

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the AT91M55800A microcontroller be held at valid logic levels to minimize the power consumption.

Maximum Operating

Frequency

1745D–ATARM–04-Nov-05

7.3 Master Clock

7.4 Reset

7.4.1 NRST Pin

Master Clock is generated in one of the following ways, depending on programming in the APMC registers:

• From the 32768 Hz low-power oscillator that clocks the RTC

• The on-chip main oscillator together with a PLL generate a software-programmable main clock in the 500 Hz to 33 MHz range. The main oscillator can be bypassed to allow the user to enter an external clock signal.

The Master Clock (MCK) is also provided as an output of the device on the pin MCKO, whose state is controlled by the APMC module.

Reset restores the default states of the user interface registers (defined in the user interface of each peripheral), and forces the ARM7TDMI to perform the next instruction fetch from address zero. Aside from the program counter, the ARM7TDMI registers do not have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. At reset, the source of MCK is the Slow Clock (32768 Hz crystal), and the signal presented on MCK must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation.

7.4.2 NTRST Pin

Test Access Port (TAP) reset functionality is provided through the NTRST signal.

The NTRST control pin initializes the selected TAP controller. The TAP controller involved in this reset is determined according to the initial logical state applied on the JTAGSEL pin after the last valid NRST.

In either Boundary Scan or ICE Mode a reset can be performed from the same or different circuitry, as shown in Figure 7-1 below. But in all cases, the NTRST like the NRST signal, must be asserted after each power-up. (See the AT91M55800A electrical datasheet, Atmel lit° 1727, for the necessary minimum pulse assertion time.)

Figure 7-1. Separate or Common Reset Management

Reset

Controller

Reset

Controller

NTRST

NRST

AT91M55800A

(1) (2)

Reset

Controller

NTRST

NRST

AT91M55800A

Notes: 1. NRST and NTRST handling in Debug Mode during development.

2. NRST and NTRST handling during production.

AT91M55800A

1745D–ATARM–04-Nov-05

In order to benefit the most regarding the separation of NRST and NTRST during the Debug phase of development, the user must independently manage both signals as shown in example (1) of Figure 7-1 above. However, once Debug is completed, both signals are easily managed together during production as shown in example (2) of Figure 7-1 above.

7.4.3 Watchdog Reset

The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot Mode and Tri-state Mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority.

7.5 Emulation Functions

7.5.1 Tri-state Mode

The AT91M55800A provides a Tri-state Mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In Tri-state Mode, all the output pin drivers of the AT91M55800A microcontroller are disabled.

To enter Tri-state Mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation the pin NTRI must be held high during reset, by a resistor of up to 400K Ohm.

AT91M55800A

NTRI is multiplexed with I/O line PA18 and USART 1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on NTRI while NRST is asserted.

7.5.2 JTAG/ICE Debug Mode

ARM Standard Embedded In-Circuit Emulation is supported via the JTAG/ICE port. It is connected to a host computer via an external ICE Interface. The JTAG/ICE debug mode is enabled when JTAGSEL is low.

In ICE Debug Mode the ARM Core responds with a non-JTAG chip ID which identifies the core to the ICE system. This is not JTAG compliant.

7.5.3 IEEE 1149.1 JTAG Boundary-scan

JTAG Boundary-scan is enabled when JTAGSEL is high. The functions SAMPLE, EXTEST and BYPASS are implemented. There is no JTAG chip ID. The Special Function module provides a chip ID which is independent of JTAG.

It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after JTAGSEL is changed.

7.6 Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces:

1745D–ATARM–04-Nov-05

• Internal memories in the four lowest megabytes

• Middle space reserved for the external devices (memory or peripherals) controlled by the EBI

7.6.1 Internal Memories

7.6.2 Boot Mode Select

• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

The AT91M55800A microcontroller integrates an 8-Kbyte SRAM bank. This memory bank is mapped at address 0x0 (after the remap command), allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for stack allocation (to speed up context saving and restoring), or as data and program storage for critical algorithms. All internal memory is 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones.

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory (see Table 7-2).

The pin BMS is multiplexed with the I/O line PB18 that can be programmed after reset like any standard PIO line.

7.6.3 Remap Command

7.6.4 Abort Control

Table 7-2. Boot Mode Select

BMS Boot Mode

1 External 8-bit memory on NCS0

0 External 16-bit memory on NCS0

The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91M55800A microcontroller uses a remap command that enables switching between the boot memory and the internal RAM bank addresses. The remap command is accessible through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if access to the other external devices (connected to chip selects 1 to 7) is required. The remap operation can only be changed back by an internal reset or an NRST assertion.

The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is asserted when accessing an undefined address in the EBI address space.

No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not.

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7.7 External Bus Interface

The External Bus Interface handles the accesses between addresses 0x0040 0000 and 0xFFC0 0000. It generates the signals that control access to the external devices, and can configure up to eight 16-Mbyte banks. In all cases it supports byte, half-word and word aligned accesses.

For each of these banks, the user can program:

• Number of wait states

• Number of data float times (wait time after the access is finished to prevent any bus contention in case the device is too long in releasing the bus)

• Data bus width (8-bit or 16-bit)

• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device (Byte Access Select Mode) or two 8-bit devices in parallel that emulate a 16-bit memory (Byte-write Access mode).

The External Bus Interface features also the Early Read Protocol, configurable for all the devices, that significantly reduces access time requirements on an external device.

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8. Peripherals

The AT91M55800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus. Peripheral registers are only word accessible – byte and half-word accesses are not supported. If a byte or a half-word access is attempted, the memory controller automatically masks the lowest address bits and generates a word access.

Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address space).

8.1 Peripheral Registers

The following registers are common to all peripherals:

• Control Register – Write-only register that triggers a command when a one is written to the corresponding position at the appropriate address. Writing a zero has no effect.

• Mode Register – read/write register that defines the configuration of the peripheral. Usually has a value of 0x0 after a reset.

• Data Register – read and/or write register that enables the exchange of data between the processor and the peripheral.

• Status Register – Read-only register that returns the status of the peripheral.

• Enable/Disable/Status Registers – shadow command registers. Writing a one in the Enable Register sets the corresponding bit in the Status Register. Writing a one in the Disable Register resets the corresponding bit and the result can be read in the Status Register. Writing a bit to zero has no effect. This register access method maximizes the efficiency of bit manipulation, and enables modification of a register with a single non-interruptible instruction, replacing the costly read-modify-write operation.

Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward compatibility. These bits read 0.

8.2 Peripheral Interrupt Control

The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt Controller.

The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask) makes it possible to enable or disable peripheral interrupt sources with a non-interruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in realtime and multi-tasking systems.

8.3 Peripheral Data Controller

The user interface of a PDC channel is integrated in the memory space of each peripheral. It contains a 32-bit address pointer register and a 16-bit count register. When the programmed data is transferred, an end of transfer interrupt is generated by the corresponding peripheral.

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8.4 System Peripherals

8.4.1 APMC: Advanced Power Management Controller

The AT91M55800A Advanced Power Management Controller allows optimization of power consumption. The APMC enables/disables the clock inputs of most of the peripherals and the ARM Core. Moreover, the main oscillator, the PLL and the analog peripherals can be put in standby mode allowing minimum power consumption to be obtained. The APMC provides the following operating modes:

• Normal: clock generator provides clock to the entire chip except the RTC.

• Wait mode: ARM Core clock deactivated

• Slow Clock mode: clock generator deactivated, master clock 32 kHz

• Standby mode: RTC active, all other clocks disabled

• Power down: RTC active, supply on the rest of the circuit deactivated

AT91M55800A

8.4.2 RTC: Real-time Clock

The AT91M55800A features a Real-time Clock (RTC) peripheral that is designed for very low power consumption. It combines a complete time-of-day clock with alarm and a two-hundred year Gregorian calendar, complemented by a programmable periodic interrupt.

The time and calendar values are coded in Binary-Coded Decimal (BCD) format. The time format can be 24-hour mode or 12-hour mode with an AM/PM indicator.

Updating time and calendar fields and configuring the alarm fields is performed by a parallel capture on the 32-bit data bus. An entry control is performed to avoid loading registers with incompatible BCD format data or with an incompatible date according to the current month/ year/century.

8.4.3 AIC: Advanced Interrupt Controller

The AIC has an 8-level priority, individually maskable, vectored interrupt controller, and drives the NIRQ and NFIQ pins of the ARM7TDMI from:

• The external fast interrupt line (FIQ)

• The six external interrupt request lines (IRQ0 - IRQ5)

• The interrupt signals from the on-chip peripherals.

The AIC is largely programmable offering maximum flexibility, and its vectoring features reduce the real-time overhead in handling interrupts.

The AIC also features a spurious vector, which reduces Spurious Interrupt handling to a minimum, and a protect mode that facilitates the debug capabilities.

8.4.4 PIO: Parallel I/O Controller

The AT91M55800A has 58 programmable I/O lines. 13 pins are dedicated as general-purpose I/O pins. The other I/O lines are multiplexed with an external signal of a peripheral to optimize the use of available package pins. The PIO lines are controlled by two separate and identical

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PIO Controllers called PIOA and PIOB. The PIO controller enables the generation of an interrupt on input change and insertion of a simple input glitch filter on any of the PIO pins.

8.4.5 WD: Watchdog

The Watchdog is built around a 16-bit counter, and is used to prevent system lock-up if the software becomes trapped in a deadlock. It can generate an internal reset or interrupt, or assert an active level on the dedicated pin NWDOVF. All programming registers are password-protected to prevent unintentional programming.

8.4.6 SF: Special Function

The AT91M55800A provides registers which implement the following special functions.

• Chip identification

• RESET status

8.5 User Peripherals

8.5.1 USART: Universal Synchronous/

Asynchronous Receiver Transmitter

The AT91M55800A provides three identical, full-duplex, universal synchronous/asynchronous receiver/transmitters.

Each USART has its own baud rate generator, and two dedicated Peripheral Data Controller channels. The data format includes a start bit, up to 8 data bits, an optional programmable parity bit and up to 2 stop bits.

The USART also features a Receiver Timeout register, facilitating variable-length frame support when it is working with the PDC, and a Time-guard register, used when interfacing with slow remote equipment.

8.5.2 TC: Timer Counter

The AT91M55800A features two Timer Counter blocks that include three identical 16-bit timer counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse-width modulation.

The Timer Counters can be used in Capture or Waveform mode, and all three counter channels can be started simultaneously and chained together.

8.5.3 SPI: Serial Peripheral Interface

The SPI provides communication with external devices in master or slave mode. It has four external chip selects that can be connected to up to 15 devices. The data length is programmable, from 8- to 16-bit.

8.5.4 ADC: Analog-to-digital Converter

The two identical 4-channel 10-bit analog-to-digital converters (ADC) are based on a Successive Approximation Register (SAR) approach.

Each ADC has 4 analog input pins, AD0 to AD3 and AD4 to AD7, digital trigger input pins AD0TRIG and AD1TRIG, and provides an interrupt signal to the AIC. Both ADCs share the analog power supply pins VDDA and GNDA, and the input reference voltage pin ADVREF.

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Each channel can be enabled or disabled independently, and has its own data register. The ADC can be configured to automatically enter Sleep mode after a conversion sequence, and can be triggered by the software, the Timer Counter, or an external signal.

8.5.5 DAC: Digital-to-analog Converter

Each DAC has an analog output pin, DA0 and DA1, and provides an interrupt signal to the AIC DA0IRQ and DA1IRQ. Both DACs share the analog power supply pins VDDA and GNDA, and the input reference DAVREF.

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9. Memory Map

Figure 9-1. AT91M55800A Memory Map Before and after Remap Command

Before Remap After Remap

Address Function Size Abort Control

0xFFFFFFFF

0xFFC00000

0xFFBFFFFF

0x00400000

0x003FFFFF

On-chip

Peripherals

Reserved

On-chip RAM

4M Bytes

1M Byte

Address Function Size Abort Control

0xFFFFFFFF

0xFFC00000

0xFFBFFFFF

0x00400000

0x003FFFFF

On-chip

Peripherals

External Devices (up to 8)

Reserved

4M Bytes

Up to 8 Devices

Programmable Page Size

1, 4, 16, 64M Bytes

1M Byte No

Ye s

0x00300000

0x002FFFFF

0x00200000

0x001FFFFF

0x00100000

0x000FFFFF

0x00000000

Reserved

On-chip

Device

Reserved

On-chip

Device

External

Devices Selected

by NCS0

1M Byte

0x00300000

0x002FFFFF

0x00200000

0x001FFFFF

0x00100000

0x000FFFFF

0x00000000

Reserved

On-chip

Device

Reserved

On-chip

Device

On-chip RAM

1M Byte

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10. Peripheral Memory Map

Figure 1. AT91M55800A Peripheral Memory Map

AT91M55800A

Address Peripheral Peripheral Name Size

0xFFFFFFFF

0xFFFFF000

0xFFFFBFFF

0xFFFF8000

0xFFFF7FFF

0xFFFF4000

0xFFFF3FFF

0xFFFF0000

0xFFFEFFFF

0xFFFEC000

0xFFFD7FFF

0xFFFD4000

0xFFFD3FFF

0xFFFD0000

0xFFFCBFFF

0xFFFC8000

0xFFFC7FFF

0xFFFC4000

0xFFFC3FFF

0xFFFC0000

0xFFFBFFFF

0xFFFBC000

0xFFFBBFFF

0xFFFB8000

0xFFFB7FFF

0xFFFB4000

0xFFFB3FFF

0xFFFB0000

0xFFFAFFFF

0xFFFAC000

0xFFFABFFF

0xFFFA8000

0xFFF03FFF

0xFFF00000

0xFFE03FFF

0xFFE00000

0xFFC00000

AIC

APMC

PIO B

PIO A

TC 3,4,5

TC 0,1,2

USART2

USART1

USART0

SPI

RTC

ADC1

ADC0

DAC1

DAC0

EBI

Advanced Interrupt Controller

Reserved

WatchdogTimer

Advanced Power Management Controller

Parallel I/O Controller B

Parallel I/O Controller A

Reserved

Timer Counter Channels 3,4,5

Timer Counter Channels 0,1,2

Reserved

Universal Synchronous/ Asynchronous Receiver/Transmitter 2

Universal Synchronous/ Asynchronous Receiver/Transmitter 1

Universal Synchronous/ Asynchronous Receiver/Transmitter 0

Serial Peripheral Interface

Real-time Clock

Analog-to-digital Converter 1

Analog-to-digital Converter 0

Digital-to-analog Converter 1

Digital-to-analog Converter 0

Reserved

Special Function

Reserved

External Bus Interface

Reserved

4K Bytes

16K Bytes

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11. EBI: External Bus Interface

The EBI generates the signals that control the access to the external memory or peripheral devices. The EBI is fully-programmable and can address up to 128M bytes. It has eight chip selects and a 24-bit address bus.

The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate read and write control signals allow for direct memory and peripheral interfacing.

The EBI supports different access protocols allowing single-clock cycle memory accesses.

The main features are:

• External memory mapping

• 8 active-low chip select lines

• 8- or 16-bit data bus

• Byte-write or byte-select lines

• Remap of boot memory

• Two different read protocols

• Programmable wait state generation

• External wait request

• Programmable data float time

The EBI User Interface is described on page 48.

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11.1 External Memory Mapping

The memory map associates the internal 32-bit address space with the external 24-bit address bus.

The memory map is defined by programming the base address and page size of the external memories (see EBI User Interface registers EBI_CSR0 to EBI_CSR7). Note that A0 - A23 is only significant for 8-bit memory; A1 - A23 is used for 16-bit memory.

If the physical memory device is smaller than the programmed page size, it wraps around and appears to be repeated within the page. The EBI correctly handles any valid access to the memory device within the page. (See Figure 11-1.)

In the event of an access request to an address outside any programmed page, an Abort signal is generated. Two types of Abort are possible: instruction prefetch abort and data abort. The corresponding exception vector addresses are respectively 0x0000 000C and 0x0000

0010. It is up to the system programmer to program the error handling routine to use in case of an Abort (see the ARM7TDMI datasheet for further information).

Figure 11-1. External Memory Smaller than Page Size

Memory

Map

1-Mbyte Device

Low

AT91M55800A

Base + 4M Byte

Base + 3M Byte

Base + 2M Byte

Base + 1M Byte

Base

Repeat 3

Repeat 2

Repeat 1

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11.2 EBI Pin Description

Name Description Type

A0 - A23 Address bus (output) Output

D0 - D15 Data bus (input/output) I/O

NCS0 - NCS7 Active low chip selects (output) Output

NRD Read Enable (output) Output

NWR0 - NWR1 Lower and upper write enable (output) Output

NOE Output enable (output) Output

NWE Write enable (output) Output

NUB, NLB Upper and lower byte-select (output) Output

NWAIT Wait request (input) Input

The following table shows how certain EBI signals are multiplexed:

Multiplexed Signals Functions

A0 NLB 8- or 16-bit data bus

NRD NOE Byte-write or byte-select access

NWR0 NWE Byte-write or byte-select access

NWR1 NUB Byte-write or byte-select access

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11.3 Data Bus Width

AT91M55800A

A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled by the DBW field in the EBI_CSR (Chip-select Register) for the corresponding chip select.

Figure 11-2 shows how to connect a 512K x 8-bit memory on NCS2.

Figure 11-2. Memory Connection for an 8-bit Data Bus

EBI

D0 - D7

D8 - D15

A1 - A18

A0 NWR1 NWR0

NRD

NCS2

D0 - D7

A1 - A18 A0

Write Enable Output Enable

Memory Enable

Figure 11-3 shows how to connect a 512K x 16-bit memory on NCS2.

Figure 11-3. Memory Connection for a 16-bit Data Bus

EBI

D0 - D7

D8 - D15

A1 - A19

NLB

NUB High Byte Enable

NWE

NOE

NCS2

D0 - D7 D8 - D15 A0 - A18 Low Byte Enable

Write Enable Output Enable

Memory Enable

11.4 Byte-write or Byte-select Access

Each chip select with a 16-bit data bus can operate with one of two different types of write access:

• Byte-write Access supports two Byte-write and a single read signal.

• Byte-select Access selects upper and/or lower byte with two byte-select lines, and separate read and write signals.

This option is controlled by the BAT field in the EBI_CSR (Chip-select Register) for the corresponding chip select.

Byte-write Access is used to connect 2 x 8-bit devices as a 16-bit memory page.

• The signal A0/NLB is not used.

• The signal NWR1/NUB is used as NWR1 and enables upper byte writes.

• The signal NWR0/NWE is used as NWR0 and enables lower byte writes.

• The signal NRD/NOE is used as NRD and enables half-word and byte reads.

Figure 11-4 shows how to connect two 512K x 8-bit devices in parallel on NCS2.

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Figure 11-4. Memory Connection for 2 x 8-bit Data Busses

EBI

D0 - D7

D8 - D15

A1 - A19

A0 NWR1 NWR0

NRD

NCS2

D0 - D7

A0 - A18

Write Enable Read Enable

Memory Enable

D8 - D15 A0 - A18

Write Enable

Read Enable Memory Enable

Byte-select Access is used to connect 16-bit devices in a memory page.

• The signal A0/NLB is used as NLB and enables the lower byte for both read and write operations.

• The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write operations.

• The signal NWR0/NWE is used as NWE and enables writing for byte or half word.

• The signal NRD/NOE is used as NOE and enables reading for byte or half word.

Figure 11-5 shows how to connect a 16-bit device with byte and half-word access (e.g. 16-bit

SRAM) on NCS2.

Figure 11-5. Connection for a 16-bit Data Bus with Byte and Half-word Access

EBI

D0 - D7 D8 - D15 A1 - A19

NLB

NUB High Byte Enable

NWE

NOE

NCS2

D0 - D7 D8 - D15 A0 - A18 Low Byte Enable

Write Enable Output Enable

Memory Enable

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AT91M55800A

Figure 11-6 shows how to connect a 16-bit device without byte access (e.g. Flash) on NCS2.

Figure 11-6. Connection for a 16-bit Data Bus Without Byte-write Capability.

11.5 Boot on NCS0

EBI

D0 - D7

D8 - D15

A1 - A19

NLB

NUB

NWE

NOE

NCS2

D0 - D7 D8 - D15 A0 - A18

Write Enable Output Enable

Memory Enable

Depending on the device and the BMS pin level during the reset, the user can select either an 8-bit or 16-bit external memory device connected on NCS0 as the Boot Memory. In this case, EBI_CSR0 (Chip-select Register 0) is reset at the following configuration for chip select 0:

• 8 wait states (WSE = 1, NWS = 7)

• 8-bit or 16-bit data bus width, depending on BMS

Byte access type and number of data float time are respectively set to Byte-write Access and

0. With a nonvolatile memory interface, any value can be programmed for these parameters.

Before the remap command, the user can modify the chip select 0 configuration, programming the EBI_CSR0 with exact boot memory characteristics. The base address becomes effective after the remap command, but the new number of wait states can be changed immediately. This is useful if a boot sequence needs to be faster.

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11.6 Read Protocols

The EBI provides two alternative protocols for external memory read access: standard and early read. The difference between the two protocols lies in the timing of the NRD (read cycle) waveform.

The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid for all memory devices. Standard read protocol is the default protocol after reset.

Note: In the following waveforms and descriptions, NRD represents NRD and NOE since the two sig-

11.6.1 Standard Read Protocol

Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are active during the second half of the clock cycle. The first half of the clock cycle allows time to ensure completion of the previous access as well as the output of address and NCS before the read cycle begins.

During a standard read protocol, external memory access, NCS is set low and ADDR is valid at the beginning of the access while NRD goes low only in the second half of the master clock cycle to avoid bus conflict (see Figure 11-7). NWE is the same in both protocols. NWE always goes low in the second half of the master clock cycle (see Figure 11-8).

Figure 11-7. Standard Read Protocol

nals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless NWR0 and NWR1 are otherwise represented. ADDR represents A0 - A23 and/or A1 - A23.

11.6.2 Early Read Protocol

Early read protocol provides more time for a read access from the memory by asserting NRD at the beginning of the clock cycle. In the case of successive read cycles in the same memory, NRD remains active continuously. Since a read cycle normally limits the speed of operation of the external memory system, early read protocol can allow a faster clock frequency to be used. However, an extra wait state is required in some cases to avoid contentions on the external bus.

MCK

ADDR

NCS

NRD

NWE

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