ATMEL AT91M43300 User Manual
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Features
• Utilizes the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-Circuit Emulation)
• 3K Bytes Internal RAM
• Fully-programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software-programmable 8/16-bit External Data Bus
• 8-channel Peripheral Data Controller
• 8-level Priority, Individually-maskable, Vectored Interrupt Controller
– 5 External Interrupts, including a High-priority, Low-latency Interrupt Request
• 58 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
– 6 External Clock Inputs
– 2 Multi-purpose I/O Pins per Channel
• 3 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for up to 9-bit Data Transfers
• Master/Slave SPI Interface
– 2 Dedicated Peripheral Data Controller (PDC) Channels
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects
• Programmable Watchdog Timer
• Power Management Controller (PMC)
– CPU and Peripherals can be Deactivated Individually
• IEEE 1149.1 JTAG Boundary Scan on all Active Pins
• Fully Static Operation: 0 Hz to 25 MHz (12 MHz @ 1.8V)
• 1.8V to 3.6V Core Operating Voltage Range
• 2.7V to 5.5V I/O Operating Voltage Range
• -40° to +85°C Operating Temperature Range
• Available in a 144-ball PBGA Package
™
ARM® Thumb® Processor Core
AT91
ARM
®
Thumb®
Microcontrollers
AT91M43300
Description
The AT91M43300 is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core.
This processor has a high-performance 32-bit RISC architecture with a high-density
16-bit instruction set and features very low power consumption. In addition, a large
number of internally banked registers result in very fast exception handling, making
the device ideal for real-time control applications. The AT91 ARM-based MCU family
also features Atmel’s high-density, in-system programmable, nonvolatile memory
technology.
The AT91M43300 has a direct connection to off-chip memory, including Flash,
through the fully-programmable External Bus Interface.
The AT91M43300 is manufactured using Atmel’s high-density CMOS technology. By
combining the ARM7TDMI microcontroller core with an on-chip SRAM, and a wide
range of peripheral functions on a monolithic chip, the AT91M43300 provides a highlyflexible and cost-effective solution to many compute-intensive multi-processor applications.
The compact BGA package reduces required board space to an absolute minimum.
Rev. 1322A–10/99
1
Pin Description
Table 1. AT91M43300 Pin Description
Module Name Function Type
A0 - A23 Address Bus Output – All valid after reset
D0 - D15 Data Bus I/O –
CS4 - CS7 Chip Select Output High A23 - A20 after reset
NCS0 - NCS3 Chip Select Output Low
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Lower Byte 1 Write Signal Output Low Used in Byte Write option
EBI
AIC
Timer
USART
SPI
PIO
WD NWDOVF Watchdog Timer Overflow Output Low Open drain
Clock
Reset NRST Hardware Reset Input Input Low Schmitt trigger, internal pull-up
JTAG/ICE
Power
Emulation NTRI Tristate Mode Enable Input Low Sampled during reset
NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NLB Lower Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input – Sampled during reset
IRQ0 - IRQ3 External Interrupt Request Input – PIO-controlled after reset
FIQ Fast External Interrupt Request Input – PIO-controlled after reset
TCLK0 - TCLK5 Timer External Clock Input – PIO-controlled after reset
TIOA0 - TIOA5 Multi-purpose Timer I/O Pin A I/O – PIO-controlled after reset
TIOB0 - TIOB5 Multi-purpose Timer I/O Pin B I/O – PIO-controlled after reset
SCK0 - SCK2 External Serial Clock I/O – PIO-controlled after reset
TXD0 - TXD2 Transmit Data Output Output – PIO-controlled after reset
RXD0 - RXD2 Receive Data Input Input – PIO-controlled after reset
SPCK SPI Clock I/O – PIO-controlled after reset
MISO Master In Slave Out I/O – PIO-controlled after reset
MOSI Master Out Slave In I/O – PIO-controlled after reset
NSS Slave Select Input Low PIO-controlled after reset
NPCS0 - NPCS3 Peripheral Chip Select Output Low PIO-controlled after reset
PA0 - PA29 Programmable I/O Port A I/O – Input after reset
PB0 - PB27 Programmable I/O Port B I/O – Input after reset
MCKI Master Clock Input Input – Schmitt trigger
MCKO Master Clock Output Output –
JTAGSEL Selects between JTAG and ICE mode Input –
TMS Test Mode Select Input – Schmitt trigger, internal pull-up
TDI Test Data In Input – Schmitt trigger, internal pull-up
TDO Test Data Out Output –
TCK Test Clock Input – Schmitt trigger, internal pull-up
NTRST Test Reset Input Input Low Schmitt trigger, internal pull-up
VDDIO I/O Power Power – 3V or 5V nominal supply
VDDCORE Core Power Power – 2.0V or 3V nominal supply
GND Ground Ground –
Active
Level
Comments
High enables IEEE 1149.1 JTAG
boundary scan
2
AT91M43300
Pin Configuration
Figure 1. AT91M43300 in 144-ball BGA Package (top view)
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AT91M43300
A
B
C
D
E
F
G
H
J
K
L
M
NUB
NOE
NWR1
NCS0 NWE
NCS2 NCS1 VDDCORE NCS3 GND NRST PB10 PB14 PB9 VDDCORE
A3 A2 GND PB13 PB16 PB12
VDDIO GND A10 PA7
A9 A14 A8 PB23
A15 VDDIO A21
A18 D0 GND PB20
A20
CS7
D4 VDDIO VDDCORE PA5
D5 D7 GND VDDIO PA10
D6 D8 D9 GND PA9
TCK TDI VDDIO PB17
NRD
VDDIO TDO NTRST MCKI PB15 PB8 PB6 GND
NWR0
NWAIT A5 PB18
A4 A1 A6
A12 A7 A0
A13 A17 A11
CS6
D2 A22
CS5
A19 D3 PA2
D1 D11 D12
D10 D14 PB24
D15 VDDIO PA0
PB22
GND PA1
TCLK1
GND VDDIO PB7 PB5
MCKO
TMS
BMS
A23
CS4
TIOB1
TCLK3
TIOA3
JTAGSEL
PB19
TCLK0
A16
D13
PB21
TIOB0
PB26
TIOA2
PA4
TIOA4
PA6
TCLK5
TIOA5
TIOA1
PB27
TIOB2
TIOA0
TIOB3
TIOB4
NWDOVF VDDIO
PA8
PA19
TIOB5
RXD1
PB25
PA25
TCLK2
MOSI
PA12
PA11
IRQ3
IRQ2
PA3
PA20
TCLK4
SCK2
PA16
PA17
RXD0
SCK1
VDDIO
IRQ1
PA13
IRQ0
FIQ
PB4 PB3
PB2 PB1
PB11 PB0
GND GND
PA22
RXD2
GND GND
PA23
SPCK
PA27
NPCS1
PA24
MISO
GND PA21
VDDCORE
PA14
SCK0
GND
PA29
NPCS3
PA28
NPCS2
PA26
NPCS0 /NSS
TXD2
PA18 / TXD1
NTRI
PA15
TXD0
3
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