ATMEL AT91M42800A User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Utilizes the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 8K Bytes Internal SRAM
• Fully Programmable External Bus Interface (EBI)
– Maximum External Address Space of 64M Bytes
– Up to 8 Chip Selects
– Software Programmable 8/16-bit External Data Bus
• 8-channel Peripheral Data Controller
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 5 External Interrupts, Including a High-priority, Low-latency Interrupt Request
• 54 Programmable I/O Lines
• 6-channel 16-bit Timer/Counter
– 6 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
– Support for up to 9-bit Data Transfers
• 2 Master/Slave SPI Interfaces
– 2 Dedicated Peripheral Data Controller (PDC) Channels per SPI
– 8- to 16-bit Programmable Data Length
– 4 External Slave Chip Selects per SPI
• 3 System Timers
– Period Interval Timer (PIT); Real-time Timer (RTT); Watchdog Timer (WDT)
• Power Management Controller (PMC)
– CPU and Peripherals Can be Deactivated Individually
• Clock Generator with 32.768 kHz Low-power Oscillator and PLL
– Support for 38.4 kHz Crystals
– Software Programmable System Clock (up to 33 MHz)
®
• IEEE
• Fully Static Operation: 0 Hz to 33 MHz, Internal Frequency Range at V
• 2.7V to 3.6V Core and PLL Operating Voltage Range; 2.7V to 5.5V I/O Operating Voltage
• -40°C to +85°C Temperature Range
• Available in a 144-lead LQFP Package (Green) and a 144-ball BGA Package (RoHS
1149.1 JTAG Boundary Scan on All Active Pins
85°C
Range
compliant)
®
ARM® Thumb® Processor Core
DDCORE
= 3.0V,
AT91 ARM
Thumb
Microcontrollers
AT91M42800A
Rev. 1779D–ATARM–14-Apr-06
1. Description
The AT91M42800A is a member of the Atmel AT91 16/32-bit microcontroller family, which is
based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC
architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling,
making the device ideal for real-time control applications. The AT91 ARM-based MCU family
also features Atmel’s high-density, in-system programmable, nonvolatile memory technology.
The AT91M42800A has a direct connection to off-chip memory, including Flash, through the
External Bus Interface.
The Power Management Controller allows the user to adjust device activity according to system requirements, and, with the 32.768 kHz low-power oscillator, enables the AT91M42800A
to reduce power requirements to an absolute minimum. The AT91M42800A is manufactured
using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core
with on-chip SRAM and a wide range of peripheral functions including timers, serial communication controllers and a versatile clock generator on a monolithic chip, the AT91M42800A
provides a highly flexible and cost-effective solution to many compute-intensive applications.
2
AT91M42800A
1779D–ATARM–14-Apr-06
2. Pin Configuration
Figure 2-1. Pin Configuration in TQFP144 Package (Top View)
108 73
AT91M42800A
109
AT91M42800 33AI
144
136
Figure 2-2. Pin Configuration in BGA144 Package (Top View)
123456789101112
A
B
C
D
E
72
37
1779D–ATARM–14-Apr-06
F
G
H
J
K
L
M
3
Table 1. AT91M42800A Pinout in TQFP 144 Package
Pin# Name Pin# Name Pin# Name Pin# Name
1 GND 37 GND 73 GND 109 GND
2 GND 38 GND 74 GND 110 GND
3 NLB/A0 39 D4 75 PB22/TIOA5 111 PA26
4 A1 40 D5 76 PB23/TIOB5 112 MODE0
5 A2 41 D6 77 PA0/IRQ0 113 XIN
6 A3 42 D7 78 PA1/IRQ1 114 XOUT
7 A4 43 D8 79 PA2/IRQ2 115 GND
8 A5 44 D9 80 PA3/IRQ3 116 PLLRCA
9 A6 45 D10 81 PA4/FIQ 117 VDDPLL
10 A7 46 D11 82 PA5/SCK0 118 PLLRCB
11 A8 47 D12 83 PA6/TXD0 119 VDDPLL
12 VDDIO 48 VDDIO 84 VDDIO 120 VDDIO
13 GND 49 GND 85 GND 121 GND
14 A9 50 D13 86 PA7/RXD0 122 NWDOVF
15 A10 51 D14 87 PA8/SCK1 123 PA27/BMS
16 A11 52 D15 88 PA9/TXD1/NTRI 124 MODE1
17 A12 53 PB6/TCLK0 89 PA10/RXD1 125 TMS
18 A13 54 PB7/TIOA0 90 PA11/SPCKA 126 TDI
19 A14 55 PB8/TIOB0 91 PA12/MISOA 127 TDO
20 A15 56 PB9/TCLK1 92 PA13/MOSIA 128 TCK
21 A16 57 PB10/TIOA1 93 PA14/NPCSA0/NSSA 129 NTRST
22 A17 58 PB11/TIOB1 94 PA15/NPCSA1 130 NRST
23 A18 59 PB12/TCLK2 95 PA16/NPCSA2 131 PA28
24 VDDIO 60 VDDIO 96 VDDIO 132 VDDIO
25 GND 61 GND 97 GND 133 GND
26 A19 62 PB13/TIOA2 98 PA17/NPCSA3 134 PA29/PME
27 PB2/A20/CS7 63 PB14/TIOB2 99 PA18/SPCKB 135 NWAIT
28 PB3/A21/CS6 64 PB15/TCLK3 100 PA19/MISOB 136 NOE/NRD
29 PB4/A22/CS5 65 PB16/TIOA3 101 PA20/MOSIB 137 NWE/NWR0
30 PB5/A23/CS4 66 PB17/TIOB3 102 PA21/NPCSB0/NSSB 138 NUB/NWR1
31 D0 67 PB18/TCLK4 103 PA22/NPCSB1 139 NCS0
32 D1 68 PB19/TIOA4 104 PA23/NPCSB2 140 NCS1
33 D2 69 PB20/TIOB4 105 PA24/NPCSB3 141 PB0/NCS2
34 D3 70 PB21/TCLK5 106 PA25/MCKO 142 PB1/NCS3
35 VDDCORE 71 VDDCORE 107 VDDCORE 143 VDDCORE
36 VDDIO 72 VDDIO 108 VDDIO 144 VDDIO
4
AT91M42800A
1779D–ATARM–14-Apr-06
AT91M42800A
Table 2. AT91M42800A Pinout in BGA 144 Package
Pin# Name Pin# Name Pin# Name Pin# Name
A1 PB1/NCS3 D1 A2 G1 A17 K1 D1
A2 NCS0 D2 A3 G2 A16 K2 VDDCORE
A3 NCS1 D3 A4 G3 A11 K3 VDDIO
A4 GND D4 NWAIT G4 A13 K4 D9
A5 PLLRCB D5 PA29/PME G5 GND K5 D10
A6 GND D6 PA28 G6 GND K6 D14
A7 PLLRCA D7 TCK G7 GND K7 PB9/TCLK1
A8 GND D8 TMS G8 GND K8 PB13/TIOA2
A9 XOUT D9 MODE1 G9 PA9/TXD1/NTRI K9 PB11/TIOB1
A10 XIN D10 PA25/MCKO G10 PA10/RXD1 K10 VDDIO
A11 MODE0 D11 PA21/NPCSB0 G11 PA8/SCK1 K11 PB16/TIOA3
A12 PA22/NPCSB1 D12 PA18/SPCKB G12 PA7/RXD0 K12 PB23/TIOB5
B1 NUB/NWR1 E1 A7 H1 A18 L1 D3
B2 PB0/NCS2 E2 VDDIO H2 VDDIO L2 D2
B3 VDDCORE E3 A6 H3 A15 L3 D5
B4 NWE/NWR0 E4 A5 H4 A14 L4 D8
B5 VDDPLL E5 GND H5 A19 L5 VDDIO
B6 TDO E6 GND H6 GND L6 D13
B7 VDDPLL E7 GND H7 GND L7 PB8/TIOB0
B8 NWDOVF E8 NTRST H8 GND L8 VDDIO
B9 PA26 E9 PA13/MOSIA H9 PA6/TXD0 L9 PB17/TIOB3
B10 PA19/MISOB E10 PA16/NPCSA2 H10 PA4/FIQ L10 VDDCORE
B11 PA24/NPCSB3 E11 VDDIO H11 VDDIO L11 PB20/TIOB4
B12 PA23/NPCSB2 E12 PA17/NPCSA3 H12 PA5/SCK0 L12 PB22/TIOA5
C1 NLB/A0 F1 A8 J1 PB5/A23/CS4 M1 D4
C2 A1 F2 A12 J2 D0 M2 D6
C3 VDDIO F3 A9 J3 PB4/A22/CS5 M3 D7
C4 NOE/NRD F4 A10 J4 PB3/A21/CS6 M4 D11
C5 VDDIO F5 GND J5 PB2/A20/CS7 M5 D12
C6 NRST F6 GND J6 D15 M6 PB7/TIOA0
C7 TDI F7 GND J7 PB6/TCLK0 M7 PB12/TCLK2
C8 VDDIO F8 GND J8 PB10/TIOA1 M8 PB15/TCLK3
C9 PA27/BMS F9 PA12/MISOA J9 PA3/IRQ3 M9 PB14/TIOB2
C10 VDDIO F10 PA15/NPCSA1 J10 PA2/IRQ2 M10 PB18/TCLK4
C11 VDDCORE F11 PA11/SPCKA J11 PA0/IRQ0 M11 PB19/TIOA4
C12 PA20/MOSIB F12 PA14/NPCSA0 J12 PA1/IRQ1 M12 PB21/TCLK5
1779D–ATARM–14-Apr-06
5
3. Pin Description
Table 3. AT91M42800A Pin Description
Module Name Function Type
A0 - A23 Address Bus Output – All valid after reset
D0 - D15 Data Bus I/O –
CS4 - CS7 Chip Select Output High A23 - A20 after reset
NCS0 - NCS3 Chip Select Output Low
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Lower Byte 1 Write Signal Output Low Used in Byte Write option
NRD Read Signal Output Low Used in Byte Write option
EBI
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NLB Lower Byte Select (16-bit SRAM) Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input – Sampled during reset
PME Protect Mode Enable Input High PIO-controlled after reset
Active
Level Comments
AIC
TC
USART
SPIA
SPIB
PIO
ST NWDOVF Watchdog Timer Overflow Output Low Open drain
IRQ0 - IRQ3 External Interrupt Request Input – PIO-controlled after reset
FIQ Fast External Interrupt Request Input – PIO-controlled after reset
TCLK0 - TCLK5 Timer External Clock Input – PIO-controlled after reset
TIOA0 - TIOA5 Multi-purpose Timer I/O Pin A I/O – PIO-controlled after reset
TIOB0 - TIOB5 Multi-purpose Timer I/O Pin B I/O – PIO-controlled after reset
SCK0 - SCK1 External Serial Clock I/O – PIO-controlled after reset
TXD0 - TXD1 Transmit Data Output Output – PIO-controlled after reset
RXD0 - RXD1 Receive Data Input Input – PIO-controlled after reset
SPCKA/SPCKB Clock I/O – PIO-controlled after reset
MISOA/MISOB Master In Slave Out I/O – PIO-controlled after reset
MOSIA/MOSIB Master Out Slave In I/O – PIO-controlled after reset
NSSA/NSSB Slave Select Input Low PIO-controlled after reset
NPCSA0 - NPCSA3
NPCSB0 - NPCSB3
PA0 - PA29 Programmable I/O Port A I/O – Input after reset
PB0 - PB23 Programmable I/O Port B I/O – Input after reset
Peripheral Chip Selects Output Low PIO-controlled after reset
6
AT91M42800A
1779D–ATARM–14-Apr-06
Table 3. AT91M42800A Pin Description (Continued)
Module Name Function Type
XIN Oscillator Input or External Clock Input –
XOUT Oscillator Output Output –
CLOCK
Test and
Reset
PLLRCA RC Filter for PLL A Input –
PLLRCB RC Filter for PLL B Input –
MCKO Clock Output Output –
NRST Hardware Reset Input Input Low Schmitt trigger
MODE0 - MODE1 Mode Selection Input
TMS Test Mode Select Input – Schmitt trigger, internal pull-up
TDI Test Data In Input – Schmitt trigger, internal pull-up
AT91M42800A
Active
Level Comments
JTAG/ICE
Emulation NTRI Tri-state Mode Enable Input Low Sampled during reset
Power
TDO Test Data Out Output –
TCK Test Clock Input – Schmitt trigger, internal pull-up
NTRST Test Reset Input Input Low Schmitt trigger, internal pull-up
VDDIO I/O Power Power – 3V or 5V nominal supply
VDDCORE Core Power Power – 3V nominal supply
VDDPLL PLL Power Power – 3V nominal supply
GND Ground Ground –
1779D–ATARM–14-Apr-06
7
4. Block Diagram
Figure 4-1. AT91M42800A
NTRST
TMS
TDO
TDI
TCK
JTAG
Selection
Embedded
ICE
Reset
NRST
MODE0
MODE1
XIN
XOUT
PLLRCA
PLLRCB
PA25/MCKO
PA26
PA28
PA0/IRQ0
PA1/IRQ1
PA2/IRQ2
PA3/IRQ3
PA4/FIQ
PA5/SCK0
PA6/TXD0
PA7/RXD0
PA8/SCK1
PA9/TXD1/NTRI
PA10/RXD1
PA11/SPCKA
PA12/MISOA
PA13/MOSIA
PA14/NPCSA0/NSSA
PA15/NPCSA1
PA16/NPCSA2
PA17/NPCSA3
PA18/SPCKB
PA19/MISOB
PA20/MOSIB
PA21/NPCSB0/NSSB
PA22/NPCSB1
PA23/NPCSB2
PA24/NPCSB3
ARM7TDMI
JTAG
Clock
Generator
AIC: Advanced
Interrupt Controller
USART0
P
I
O
USART1
SPIA: Serial
Peripheral
Interface
SPIB: Serial
Peripheral
Interface
PMC: Power Management
Controller
Core
Internal RAM
8K Bytes
ASB
Controller
2 PDC
Channels
2 PDC
Channels
2 PDC
Channels
2 PDC
Channels
ASB
AMBA™ Bridge
APB
EBI: External
Bus Interface
EBI User
Interface
TC: Timer/
Counter
Block 0
TC0
TC1
TC2
TC: Timer/
Counter
Block 1
TC3
TC4
TC5
System
Timers
Watchdog
Real-time
P
I
O
D0-D15
A0/NLB
A1-A19
NRD/NOE
NWR0/NWE
NWR1/NUB
NWAIT
NCS0
NCS1
PA27/BMS
PA29/PME
PB0/NCS2
PB1/NCS3
PB2/A20/CS7
PB3/A21/CS6
PB4/A22/CS5
PB5/A23/CS4
PB6/TCLK0
PB9/TCLK1
PB12/TCLK2
PB7/TIOA0
PB8/TIOB0
PB10/TIOA1
PB11/TIOB1
PB13/TIOA2
PB14/TIOB2
PB15/TCLK3
PB18/TCLK4
PB21/TCLK5
PB16/TIOA3
PB17/TIOB3
PB19/TIOA4
PB20/TIOB4
PB22/TIOA5
PB23/TIOB5
NWDOVF
Chip ID
PIO: Parallel I/O Controller
8
AT91M42800A
Period
Interval
1779D–ATARM–14-Apr-06
5. Architectural Overview
The AT91M42800A microcontroller integrates an ARM7TDMI with its embedded ICE interface, memories and peripherals. Its architecture consists of two main buses, the Advanced
System Bus (ASB) and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled by the memory controller, the ASB interfaces the ARM7TDMI processor
with the on-chip 32-bit memories, the External Bus Interface (EBI) and the AMBA
The AMBA Bridge drives the APB, which is designed for accesses to on-chip peripherals and
optimized for low power consumption.
The AT91M42800A microcontroller implements the ICE port of the ARM7TDMI processor on
dedicated pins, offering a complete, low-cost and easy-to-use debug solution for target
debugging.
5.1 Memories
The AT91M42800A microcontroller embeds up to 8K bytes of internal SRAM. The internal
memory is directly connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 30 MIPS at 33 MHz by using the ARM instruction set of the
processor. The on-chip memory significantly reduces the system power consumption and
improves its performance over external memory solutions.
The AT91M42800A microcontroller features an External Bus Interface (EBI), which enables
connection of external memories and application-specific peripherals. The EBI supports 8- or
16-bit devices and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early read protocol, enabling single clock cycle memory accesses two times faster
than standard memory interfaces.
AT91M42800A
™
Bridge.
5.2 Peripherals
The AT91M42800A microcontroller integrates several peripherals, which are classified as system or user peripherals. All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and
can be programmed with a minimum number of instructions. The peripheral register set is
composed of control, mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip
USARTs/SPIs and the on- and off-chip memories without processor intervention. Most importantly, the PDC removes the processor interrupt handling overhead and significantly reduces
the number of clock cycles required for a data transfer. It can transfer up to 64K continuous
bytes without reprogramming the start address. As a result, the performance of the microcontroller is increased and the power consumption reduced.
5.2.1 System Peripherals
The External Bus Interface (EBI) controls the external memory and peripheral devices via an
8- or 16-bit data bus and is programmed through the APB. Each chip select line has its own
programming register.
The Power Management Controller (PMC) optimizes power consumption of the product by
controlling the clocking elements such as the oscillator and the PLLs, system and user peripheral clocks.
The Advanced Interrupt Controller (AIC) controls the internal sources from the internal peripherals and the five external interrupt lines (including the FIQ) to provide an interrupt and/or fast
1779D–ATARM–14-Apr-06
9
5.2.2 User Peripherals
interrupt request to the ARM7TDMI. It integrates an 8-level priority controller, and, using the
Auto-vectoring feature, reduces the interrupt latency time.
The Parallel Input/Output Controllers (PIOA, PIOB) controls up to 54 I/O lines. It enables the
user to select specific pins for on-chip peripheral input/output functions, and general-purpose
input/output signal pins. The PIO controllers can be programmed to detect an interrupt on a
signal change from each line.
There are three embedded system timers. The Real-time Timer (RTT) counts elapsed seconds and can generate periodic or programmed interrupts. The Period Interval Timer (PIT)
can be used as a user-programmable time-base, and can generate periodic ticks. The Watchdog (WD) can be used to prevent system lock-up if the software becomes trapped in a
deadlock.
The Special Function (SF) module integrates the Chip ID and the Reset Status registers.
Two USARTs, independently configurable, enable communication at a high baud rate in synchronous or asynchronous mode. The format includes start, stop and parity bits and up to 9
data bits. Each USART also features a Time-out and a Time-guard register, facilitating the use
of the two dedicated Peripheral Data Controller (PDC) channels.
The two 3-channel, 16-bit Timer/Counters (TC) are highly-programmable and support capture
or waveform modes. Each TC channel can be programmed to measure or generate different
kinds of waves, and can detect and control two input/output signals. Each TC also has three
external clock signals.
Two independently configurable SPIs provide communication with external devices in master
or slave mode. Each has four external chip selects which can be connected to up to 15
devices. The data length is programmable, from 8- to 16-bit.
10
AT91M42800A
1779D–ATARM–14-Apr-06
6. Associated Documentation
Table 6-1. Associated Documentation
Information Document Title
Internal architecture of processor
ARM/Thumb instruction sets
Embedded in-circuit-emulator
External memory interface mapping
Peripheral operations
Peripheral user interfaces
DC characteristics
Power consumption
Thermal and reliability chonsiderations
AC characteristics
Product overview
Ordering information
Packaging information
Soldering profile
ARM7TDMI (Thumb) Datasheet
AT91M42800A Datasheet (this document)
AT91M42800A Electrical Characteristics Datasheet
AT91M42800A Summary Datasheet
AT91M42800A
7. Product Overview
7.1 Power Supply
The AT91M42800A has three kinds of power supply pins:
• VDDCORE pins that power the chip core
• VDDIO pins that power the I/O lines
• VDDPLL pins that power the oscillator and PLL cells
VDDCORE and VDDIO pins allow core power consumption to be reduced by supplying it with
a lower voltage than the I/O lines. The VDDCORE pins must never be powered at a voltage
greater than the supply voltage applied to the VDDIO.
The VDDPLL pin is used to supply the oscillator and both PLLs. The voltage applied on these
pins is typically 3.3V, and it must not be lower than VDDCORE.
Typical supported voltage combinations are shown in the following table:
Table 1.
Pins Nominal Supply Voltages
VDDCORE 3.3V 3.0V or 3.3V
VDDIO 5.0V 3.0V or 3.3V
VDDPLL 3.3V 3.0V or 3.3V
7.2 Input/Output Considerations
After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum
flexibility. It is recommended that in any application phase, the inputs to the AT91M42800A
microcontroller be held at valid logic levels to minimize the power consumption.
1779D–ATARM–14-Apr-06
11
7.3 Operating Modes
The AT91M42800A has two pins dedicated to defining MODE0 and MODE1 operating modes.
These pins allow the user to enter the device in Boundary Scan mode. They also allow the
user to run the processor from the on-chip oscillator output and from an external clock by
bypassing the on-chip oscillator. The last mode is reserved for test purposes. A chip reset
must be performed (NRST and NTRST) after MODE0 and/or MODE1 have been changed.
Table 7-1.
Warning: The user must take the external oscillator frequency into account so that it is consis-
tent with the minimum access time requested by the memory device used at the boot. Both the
default EBI setting (zero wait state) on Chip Select 0 (See ”Boot on NCS0” on page 29) and
the minimum access time of the boot memory are two parameters that determine this maximum frequency of the external oscillator.
7.4 Clock Generator
The AT91M42800A microcontroller embeds a 32.768 kHz oscillator that generates the Slow
Clock (SLCK). This on-chip oscillator can be bypassed by setting the correct logical level on
the MODE0 and MODE1 pins, as shown above. In this case, SLCK equals XIN.
MODE0 MODE1 Operating Mode
0 0 Normal operating mode by using the on-chip oscillator
0 1 Boundary Scan Mode
1 0 Normal operating mode by using an external clock on XIN
1 1 Reserved for test
7.5 Reset
7.5.1 NRST Pin
The AT91M42800A microcontroller has a fully static design and works either on the Master
Clock (MCK), generated from the Slow Clock by means of the two integrated PLLs, or on the
Slow Clock (SLCK).
These clocks are also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, and after the reset, the MCKO is
valid and outputs an image of the SLCK signal. The PIO Controller must be programmed to
use this pin as standard I/O line.
Reset initializes the user interface registers to their default states as defined in the peripheral
sections of this datasheet and forces the ARM7TDMI to perform the next instruction fetch from
address zero. Except for the program counter, the ARM core registers do not have defined
reset states. When reset is active, the inputs of the AT91M42800A must be held at valid logic
levels. The EBI address lines drive low during reset. All the peripheral clocks are disabled during reset to save power.
NRST is the active low reset input. It is asserted asynchronously, but exit from reset is synchronized internally to the slow clock (SLCK). At power-up, NRST must be active until the onchip oscillator is stable. During normal operation, NRST must be active for a minimum of 10
SLCK clock cycles to ensure correct initialization.
12
AT91M42800A
1779D–ATARM–14-Apr-06
7.5.2 NTRST Pin
AT91M42800A
The pins BMS and NTRI are sampled during the 10 SLCK clock cycles just prior to the rising
edge of NRST.
The NRST pin has no effect on the on-chip Embedded ICE logic.
The NTRST control pin initializes the selected TAP controller. The TAP controller involved in
this reset is determined according to the initial logical state applied on the JTAGSEL pin after
the last valid NRST.
In either Boundary Scan or ICE Mode, a reset can be performed from the same or different circuitry, as shown in Figure 7-1 below. But in all cases, the NTRST like the NRST signal, must
be asserted after each power-up. (See the AT91M42800A Electrical Datasheet, Atmel Lit. No.
1776, for the necessary minimum pulse assertion time.)
Figure 7-1. Separate or Common Reset Management
7.5.3 Watchdog Reset
Reset
Controller
Reset
Controller
Notes: 1. NRST and NTRST handling in Debug Mode during development.
2. NRST and NTRST handling during production.
NTRST
NRST
AT91M42800A
(1) (2)
Reset
Controller
NTRST
NRST
AT91M42800A
In order to benefit from the separation of NRST and NTRST during the debug phase of development, the user must independently manage both signals as shown in example (1) of Figure
7-1 above. However, once debug is completed, both signals are easily managed together dur-
ing production as shown in example (2) of Figure 7-1 above.
The internally generated watchdog reset has the same effect as the NRST pin, except that the
pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. The
NRST pin has priority if both types of reset coincide.
7.6 Emulation Functions
7.6.1 Tri-state Mode
The AT91M42800A provides a Tri-state mode, which is used for debug purposes in order to
connect an emulator probe to an application board. In Tri-state mode the AT91M42800A continues to function, but all the output pin drivers are tri-stated.
To enter Tri-state mode, the pin NTRI must be held low during the last 10 SLCK clock cycles
before the rising edge of NRST. For normal operation, the pin NTRI must be held high during
reset, by a resistor of up to 400 kΩ. NTRI must be driven to a valid logic value during reset.
NTRI is multiplexed with Parallel I/O PA9 and USART 1 serial data transmit line TXD1.
1779D–ATARM–14-Apr-06
13
Standard RS232 drivers generally contain internal 400 kΩ pull-up resistors. If TXD1 is con-
nected to one of these drivers, this pull-up will ensure normal operation, without the need for
an additional external resistor.
7.6.2 Embedded ICE
ARM standard embedded in-circuit emulation is supported via the JTAG/ICE port. It is connected to a host computer via an embedded ICE Interface.
Embedded ICE mode is selected when MODE1 is low.
It is not possible to switch directly between ICE and JTAG operations. A chip reset must be
performed (NRST and NTRST) after MODE0 and/or MODE1 have/has been changed. The
reset input to the embedded ICE (NTRST) is provided separately to facilitate debug of boot
programs.
7.6.3 IEEE 1149.1 JTAG Boundary Scan
IEEE 1149.1 JTAG Boundary Scan is enabled when MODE0 is low and MODE1 is high. The
functions SAMPLE, EXTEST and BYPASS are implemented. In ICE Debug mode, the ARM
core responds with a non-JTAG chip ID that identifies the core to the ICE system. This is not
IEEE 1149.1 JTAG compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed (NRST and NTRST) after MODE0 and/or MODE1
have/has been changed.
7.7 Memory Controller
The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the
internal 32-bit address bus and defines three address spaces:
7.7.1 Protection Mode
7.7.2 Internal Memories
• Internal Memories in the four lowest megabytes
• Middle Space reserved for the external devices (memory or peripherals) controlled by the
EBI
• Internal Peripherals in the four highest megabytes
In any of these address spaces, the ARM7TDMI operates in little-endian mode only.
The embedded peripherals can be protected against unwanted access. The PME (Protect
Mode Enable) pin must be tied high and validated in its peripheral operation (PIO Disable) to
enable the protection mode. When enabled, any peripheral access must be done while the
ARM7TDMI is running in Privileged mode (i.e., the accesses in user mode result in an abort).
Only the valid peripheral address space is protected and requests to the undefined addresses
will lead to a normal operation without abort.
The AT91M42800A microcontroller integrates an 8-Kbyte primary internal SRAM. All internal
memories are 32 bits wide and single-clock cycle accessible. Byte (8-bit), half-word (16-bit) or
word (32-bit) accesses are supported and are executed within one cycle. Fetching Thumb or
ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones.
The SRAM bank is mapped at address 0x0 (after the remap command), and ARM7TDMI
exception vectors between 0x0 and 0x20 that can be modified by the software. The rest of the
14
AT91M42800A
1779D–ATARM–14-Apr-06
7.7.3 Boot Mode Select
7.7.4 Remap Command
AT91M42800A
bank can be used for stack allocation (to speed up context saving and restoring), or as data
and program storage for critical algorithms.
The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in
non-volatile memory after the reset.
The input level on the BMS pin during the last 10 SLCK clock cycles before the rising edge of
the NRST selects the type of boot memory. The Boot mode depends on BMS (see Table 7-2).
The pin BMS is multiplexed with the I/O line PA27 that can be programmed after reset like any
standard PIO line.
Table 7-2. Boot Mode Select
BMS Boot Memory
1 External 8-bit memory NCS0
0 External 16-bit memory on NCS0
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt,
Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to allow these vectors
to be redefined dynamically by the software, the AT91M42800A microcontroller uses a remap
command that enables switching between the boot memory and the internal SRAM bank
addresses. The remap command is accessible through the EBI User Interface, by writing one
in RCB of EBI_RCR (Remap Control Register). Performing a remap command is mandatory if
access to the other external devices (connected to chip selects 1 to 7) is required. The remap
operation can only be changed back by an internal reset or an NRST assertion.
7.7.5 Abort Control
Notes: 1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level
sensitive.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI is
asserted in the following cases:
• When accessing an undefined address in the EBI address space
• When the ARM7TDMI performs a misaligned access
No abort is generated when reading the internal memory or by accessing the internal peripherals, whether the address is defined or not.
When the processor performs a forbidden write access in a mode-protected peripheral register, the write is cancelled but no abort is generated.
The processor can perform word or half-word data access with a misaligned address when a
register relative load/store instruction is executed and the register contains a misaligned
address. In this case, whether the access is in write or in read, an abort is generated but the
access is not cancelled.
The Abort Status Register traces the source that caused the last abort. The address and the
type of abort are stored in registers of the External Bus Interface.
1779D–ATARM–14-Apr-06
15
7.8 External Bus Interface
The External Bus Interface handles the accesses between addresses 0x0040 0000 and
0xFFC0 0000. It generates the signals that control access to the external devices, and can be
configured from eight 1-Mbyte banks up to four 16-Mbyte banks. In all cases it supports byte,
half-word and word aligned accesses.
For each of these banks, the user can program:
• Number of wait states
• Number of data float times (wait time after the access is finished to prevent any bus
contention in case the device takes too long in releasing the bus)
• Data bus width (8-bit or 16-bit)
• With a 16-bit wide data bus, the user can program the EBI to control one 16-bit device
(Byte Access Select mode) or two 8-bit devices in parallel that emulate a
16-bit memory (Byte Write Access mode).
The External Bus Interface features also the Early Read Protocol, configurable for all the
devices, that significantly reduces access time requirements on an external device.
8. Peripherals
The AT91M42800A peripherals are connected to the 32-bit wide Advanced Peripheral Bus.
Peripheral registers are only word accessible. Byte and half-word accesses are not supported.
If a byte or a half-word access is attempted, the memory controller automatically masks the
lowest address bits and generates a word access.
Each peripheral has a 16-Kbyte address space allocated (the AIC only has a 4-Kbyte address
space).
8.0.1 Peripheral Registers
The following registers are common to all peripherals:
• Control Register – Write-only register that triggers a command when a one is written to the
• Mode Register – read/write register that defines the configuration of the peripheral. Usually
• Data Registers – read and/or write register that enables the exchange of data between the
• Status Register – Read-only register that returns the status of the peripheral.
• Enable/Disable/Status Registers are shadow command registers. Writing a one in the
Unused bits in the peripheral registers are shown as “–” and must be written at 0 for upward
compatibility. These bits read 0.
corresponding position at the appropriate address. Writing a zero has no effect.
has a value of 0x0 after a reset.
processor and the peripheral.
Enable Register sets the corresponding bit in the Status Register. Writing a one in the
Disable Register resets the corresponding bit and the result can be read in the Status
Register. Writing a bit to zero has no effect. This register access method maximizes the
efficiency of bit manipulation, and enables modification of a register with a single noninterruptible instruction, replacing the costly read-modify-write operation.
8.0.2 Peripheral Interrupt Control
The Interrupt Control of each peripheral is controlled from the status register using the interrupt mask. The status register bits are ANDed to their corresponding interrupt mask bits and
16
AT91M42800A
1779D–ATARM–14-Apr-06
the result is then ORed to generate the Interrupt Source signal to the Advanced Interrupt
Controller.
The interrupt mask is read in the Interrupt Mask Register and is modified with the Interrupt
Enable Register and the Interrupt Disable Register. The enable/disable/status (or mask)
makes it possible to enable or disable peripheral interrupt sources with a non-interruptible single instruction. This eliminates the need for interrupt masking at the AIC or Core level in realtime and multi-tasking systems.
8.0.3 Peripheral Data Controller
The AT91M42800A has an 8-channel PDC dedicated to the two on-chip USARTs and to the
two on-chip SPIs. One PDC channel is connected to the receiving channel and one to the
transmitting channel of each peripheral.
The user interface of a PDC channel is integrated in the memory space of each USART channel and in the memory space of each SPI. It contains a 32-bit address pointer register and a
16-bit count register. When the programmed data is transferred, an end-of-transfer interrupt is
generated by the corresponding peripheral. See Section 17. ”USART: Universal Synchro-
nous/Asynchronous Receiver/Transmitter” on page 121 and Section 19. ”SPI: Serial
Peripheral Interface” on page 177 for more details on PDC operation and programming.
AT91M42800A
8.1 System Peripherals
8.1.1 PMC: Power Management Controller
The AT91M42800A’s Power Management Controller optimizes the power consumption of the
device. The PMC controls the clocking elements such as the oscillator and the PLLs, and the
System and the Peripheral Clocks. It also controls the MCKO pin and permits to the user to
select four different signals to be driven on this pin.
The AT91M42800A has the following clock elements:
• The oscillator providing a clock that depends on the crystal fundamental frequency
connected between the XIN and XOUT pins
• PLL A providing a low-to-middle frequency clock range
• PLL B providing a middle-to-high frequency range
• The Clock prescaler
• The ARM Processor Clock controller
• The Peripheral Clock controller
• The Master Clock Output controller
The on-chip low-power oscillator together with the PLL-based frequency multiplier and the
prescaler results in a programmable clock between 500 Hz and 66 MHz. It is the responsibility
of the user to make sure that the PMC programming does not result in a clock over the acceptable limits.
8.1.2 ST: System Timer
1779D–ATARM–14-Apr-06
The System Timer module integrates three different free-running timers:
• A Period Interval Timer setting the base time for an Operating System.
17
• A Watchdog Timer that is built around a 16-bit counter, and is used to prevent system lockup if the software becomes trapped in a deadlock. It can generate an internal reset or
interrupt, or assert an active level on the dedicated pin NWDOVF.
• A Real-time Timer counting elapsed seconds.
These timers count using the Slow Clock. Typically, this clock has a frequency of 32768 Hz.
8.1.3 AIC: Advanced Interrupt Controller
The AT91M42800A has an 8-level priority, individually maskable, vectored interrupt controller.
This feature substantially reduces the software and real-time overhead in handling internal
and external interrupts.
The interrupt controller is connected to the NFIQ (fast interrupt request) and the NIRQ (standard interrupt request) inputs of the ARM7TDMI processor. The processor’s NFIQ line can
only be asserted by the external fast interrupt request input: FIQ. The NIRQ line can be
asserted by the interrupts generated by the on-chip peripherals and the external interrupt
request lines: IRQ0 to IRQ3.
The 8-level priority encoder allows the customer to define the priority between the different
NIRQ interrupt sources.
Internal sources are programmed to be level sensitive or edge triggered. External sources can
be programmed to be positive or negative edge triggered or high- or low-level sensitive.
8.1.4 PIO: Parallel I/O Controller
The AT91M42800A has 54 programmable I/O lines. I/O lines are multiplexed with an external
signal of a peripheral to optimize the use of available package pins. These lines are controlled
by two separate and identical PIO Controllers called PIOA and PIOB. Each PIO controller also
provides an internal interrupt signal to the Advanced Interrupt Controller and insertion of a simple input glitch filter on any of the PIO pins.
8.1.5 SF: Special Function
The AT91M42800A provides registers that implement the following special functions.
• Chip Identification
• RESET Status
8.2 User Peripherals
8.2.1 USART: Universal Synchronous/ Asynchronous Receiver Transmitter
The AT91M42800A provides two identical, full-duplex, universal synchronous/asynchronous
receiver/transmitters that interface to the APB and are connected to the Peripheral Data
Controller.
The main features are:
• Programmable Baud Rate Generator with External or Internal Clock, as well as Slow Clock
• Parity, Framing and Overrun Error Detection
• Line Break Generation and Detection
• Automatic Echo, Local Loopback and Remote Loopback channel modes
• Multi-drop mode: Address Detection and Generation
18
AT91M42800A
1779D–ATARM–14-Apr-06
8.2.2 TC: Timer/Counter
The AT91M42800A features two Timer/Counter blocks, each containing three identical 16-bit
Timer/Counter channels. Each channel can be independently programmed to perform a wide
range of functions including frequency measurement, event counting, interval measurement,
pulse generation, delay timing and pulse-width modulation.
Each Timer/Counter (TC) channel has 3 external clock inputs, 5 internal clock inputs, and 2
multi-purpose input/output signals that can be configured by the user. Each channel drives an
internal interrupt signal that can be programmed to generate processor interrupts via the AIC
(Advanced Interrupt Controller).
The Timer/Counter block has two global registers that act upon all three TC channels. The
Block Control Register allows the three channels to be started simultaneously with the same
instruction. The Block Mode Register defines the external clock inputs for each Timer/Counter
channel, allowing them to be chained.
Each Timer/Counter block operates independently and has a complete set of block and channel registers.
AT91M42800A
• Interrupt Generation
• Two Dedicated Peripheral Data Controller channels
• 5-, 6-, 7-, 8- and 9-bit character length
8.2.3 SPI: Serial Peripheral Interface
The AT91M42800A includes two SPIs that provide communication with external devices in
Master or Slave mode. They are independent, and are referred to by the letters A and B. Each
SPI has four external chip selects that can be connected to up to 15 devices. The data length
is programmable from 8- to 16-bit.
1779D–ATARM–14-Apr-06
19
9. Memory Map
Figure 9-1. AT91M42800A Memory Map before Remap Command
Address Function Size Protection
0xFFFFFFFF
(1)
Abort Control
0xFFC00000
0xFFBFFFFF
0x00400000
0x003FFFFF
0x00300000
0x002FFFFF
On-chip
Peripherals
Reserved
On-chip SRAM
Reserved
On-chip
Device
4M Bytes
1M Byte
1M Byte
Privileged
No
No
Ye s
No
No
20
0x00200000
0x001FFFFF
0x00100000
0x000FFFFF
0x00000000
Note: 1. The ARM core modes are defined in the ARM7TDMI Datasheet. Privileged is a non-user
AT91M42800A
Reserved
On-chip
Device
External
Devices Selected
by NCS0
1M Byte
1M Byte
No
No
No
No
mode. The protection is active only if Protect mode is enabled.
1779D–ATARM–14-Apr-06
Figure 9-2. AT91M42800A Memory Map after Remap Command
Address Function Size Protection
0xFFFFFFFF
On-chip
Peripherals
0xFFC00000
0xFFBFFFFF
4M Bytes
Privileged
AT91M42800A
(1)
Abort Control
Ye s
0x00400000
0x003FFFFF
0x00300000
0x002FFFFF
0x00200000
0x001FFFFF
External
Devices
(up to 8)
Reserved
Reserved
On-chip
Device
Reserved
On-chip
Device
Up to 8 Devices
Programmable Page Size
1, 4, 16, 64M Bytes
1M Byte No No
1M Byte No No
1M Byte
No
No
Ye s
No
1779D–ATARM–14-Apr-06
0x00100000
0x000FFFFF
0x00000000
On-chip RAM
1M Byte
No
No
Note: 1. The ARM core modes are defined in the ARM7TDMI Datasheet. Privileged is a non-user
mode. The protection is active only if Protect mode is enabled.
21
10. Peripheral Memory Map
Figure 10-1. AT91M42800A Peripheral Memory Map
Address Peripheral Peripheral Name Size Protection
0xFFFFFFFF
0xFFFFF000
0xFFFFEFFF
0xFFFFC000
0xFFFFBFFF
0xFFFF8000
0xFFFF7FFF
0xFFFF4000
0xFFFF3FFF
0xFFFF0000
0xFFFEFFFF
0xFFFEC000
0xFFFEBFFF
0xFFFD8000
0xFFFD7FFF
0xFFFD4000
0xFFFD3FFF
0xFFFD0000
0xFFFCFFFF
0xFFFCC000
0xFFFCBFFF
0xFFFC8000
0xFFFC7FFF
0xFFFC4000
0xFFFC3FFF
0xFFFC0000
0xFFFBFFFF
0xFFF04000
0xFFF03FFF
0xFFF00000
0xFFEFFFFF
0xFFF04000
0xFFE03FFF
0xFFE00000
0xFFDFFFFF
0xFFD00000
Note: 1. The ARM core modes are defined in the ARM7TDMI Datasheet. Privileged is a non-user
AIC
ST
PMC
PIOB
PIOA
TC1
TC0
SPIB
SPIA
USART1
USART0
SF
EBI
Advanced Interrupt Controller
Reserved
System Timer
Power Management Controller
Parallel I/O Controller B
Parallel I/O Controller A
Reserved
Timer Counter 1
Channels 3, 4 and 5
Timer Counter 0
Channels 0,1 and 2
Serial Peripheral Interface B
Serial Peripheral Interface A
Universal Synchronous/
Asynchronous
Receiver/Transmitter 1
Universal Synchronous/
Asynchronous
Receiver/Transmitter 0
Reserved
Special Function
Reserved
External Bus Interface
Reserved
4K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
16K Bytes
mode. The protection is active only if Protect mode is enabled.
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
Privileged
22
AT91M42800A
1779D–ATARM–14-Apr-06
11. EBI: External Bus Interface
The EBI handles the access requests performed by the ARM core or the PDC. It generates the
signals that control the access to the external memory or peripheral devices. The EBI is fully
programmable and can address up to 64M bytes. It has eight chip selects and a 24-bit address
bus, the upper four bits of which are multiplexed with a chip select.
The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing.
The EBI supports different access protocols allowing single clock cycle memory accesses.
The main features are:
• External memory mapping
• Up to 8 chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
The EBI User Interface is described on page 48.
AT91M42800A
11.1 External Memory Mapping
The memory map associates the internal 32-bit address space with the external 24-bit
address bus.
The memory map is defined by programming the base address and page size of the external
memories (see registers EBI_CSR0 to EBI_CSR7 in Section 11.13 ”EBI User Interface” on
page 48). Note that A0 - A23 is only significant for 8-bit memory; A1 - A23 is used for 16-bit
memory.
If the physical memory device is smaller than the programmed page size, it wraps around and
appears to be repeated within the page. The EBI correctly handles any valid access to the
memory device within the page (see Figure 11-1 on page 24).
In the event of an access request to an address outside any programmed page, an abort signal is generated. Two types of abort are possible: instruction prefetch abort and data abort.
The corresponding exception vector addresses are 0x0000000C and 0x00000010, respectively. It is up to the system programmer to program the error handling routine to use in case of
an abort (see the ARM7TDMI datasheet for further information).
The chip selects can be defined to the same base address and an access to the overlapping
address space asserts both NCS lines. The Chip Select Register, having the smaller number,
defines the characteristics of the external access and the behaviour of the control signals.
1779D–ATARM–14-Apr-06
23
11.2 Abort Status
Figure 11-1. External Memory Smaller than Page Size
Base + 4M Bytes
1M Byte Device
1M Byte Device
Memory
Map
1M Byte Device
1M Byte Device
Low
Low
Low
Low
Hi
Base + 3M Bytes
Hi
Base + 2M Bytes
Hi
Base + 1M Byte
Hi
Base
Repeat 3
Repeat 2
Repeat 1
When an abort is generated, the EBI_AASR (Abort Address Status Register) and the
EBI_ASR (Abort Status Register) provide the details of the source causing the abort. Only the
last abort is saved and registers are left in the last abort status. After the reset, the registers
are initialized to 0.
The following are saved:
In EBI_AASR:
• The address at which the abort is generated
In EBI_ASR:
• Whether or not the processor has accessed an undefined address in the EBI address
space
• Whether or not the processor required an access at a misaligned address
• The size of the access (byte, word or half-word)
• The type of the access (read, write or code fetch)
11.3 EBI Behavior During Internal Accesses
When the ARM core performs accesses in the internal memories or the embedded peripherals, the EBI signals behave as follows:
• The address lines remain at the level of the last external access.
• The data bus is tri-stated.
• The control signals remain in an inactive state.
24
AT91M42800A
1779D–ATARM–14-Apr-06
AT91M42800A
11.4 Pin Description
Table 11-1. External Bus Interface Pin Description
Name Description Type
A0 - A23 Address bus Output
D0 - D15 Data bus I/O
NCS0 - NCS3 Active low chip selects Output
CS4 - CS7 Active high chip selects Output
NRD Read Enable Output
NWR0 - NWR1 Lower and upper write enable Output
NOE Output enable Output
NWE Write enable Output
NUB, NLB Upper and lower byte select Output
NWAIT Wait request Input
PME Protection Mode Enabled Input
Table 11-2. EBI Multiplexed Signals
Multiplexed Signals Functions
A23 - A20 CS4 - CS7 Allows from 4 to 8 chip select lines to be used
A0 NLB 8- or 16-bit data bus
NRD NOE Byte-write or byte select access
NWR0 NWE Byte-write or byte select access
NWR1 NUB Byte-write or byte select access
11.5 Chip Select Lines
The EBI provides up to eight chip select lines:
• Chip select lines NCS0 - NCS3 are dedicated to the EBI (not multiplexed).
• Chip select lines CS4 - CS7 are multiplexed with the top four address lines A23 - A20.
By exchanging address lines for chip select lines, the user can optimize the EBI to suit the
external memory requirements: more external devices or larger address range for each
device.
The selection is controlled by the ALE field in EBI_MCR (Memory Control Register). The following combinations are possible:
A20, A21, A22, A23 (configuration by default)
A20, A21, A22, CS4
A20, A21, CS5, CS4
A20, CS6, CS5, CS4
CS7, CS6, CS5, CS4
1779D–ATARM–14-Apr-06
25
Figure 11-2. Memory Connections for Four External Devices
(1)
NCS0 - NCS3
NRD
EBI
NWRx
A0 - A23
D0 - D15
Notes: 1. For four external devices, the maximum address space per device is 16M bytes.
Figure 11-3. Memory Connections for Eight External Devices
CS4 - CS7
NCS0 - NCS3
NRD
EBI
NWRx
A0 - A19
D0 - D15
(1)
NCS0
8 or 16
NCS2
NCS1
NCS0
8 or 16
NCS3
NCS2
NCS1
Memory Enable
Memory Enable
Output Enable
Write Enable
A0 - A19
D0 - D15 or D0 - D7
NCS3
Memory Enable
Output Enable
Write Enable
A0 - A23
D0 - D15 or D0 - D7
CS5
CS4
Memory Enable
Memory Enable
Memory Enable
Memory Enable
CS7
CS6
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Memory Enable
11.6 Data Bus Width
26
AT91M42800A
Notes: 1. For eight external devices, the maximum address space per device is 1M byte.
A data bus width of 8 or 16 bits can be selected for each chip select. This option is controlled
by the DBW field in the EBI_CSR (Chip Select Register) for the corresponding chip select.
Figure 11-4 shows how to connect a 512K x 8-bit memory on NCS2.
1779D–ATARM–14-Apr-06
Figure 11-4. Memory Connection for an 8-bit Data Bus
AT91M42800A
EBI
D0 - D7
D8 - D15
A1 - A18
A0
NWR1
NWR0
NRD
NCS2
D0 - D7
A1 - A18
A0
Write Enable
Output Enable
Memory Enable
Figure 11-5 shows how to connect a 512K x 16-bit memory on NCS2.
Figure 11-5. Memory Connection for a 16-bit Data Bus
EBI
D0 - D7
D8 - D15
A1 - A19
NLB
NUB High Byte Enable
NWE
NOE
NCS2
D0 - D7
D8 - D15
A0 - A18
Low Byte Enable
Write Enable
Output Enable
Memory Enable
11.7 Byte Write or Byte Select Access
Each chip select with a 16-bit data bus can operate with one of two different types of write
access:
• Byte Write Access supports two byte write and a single read signal.
• Byte Select Access selects upper and/or lower byte with two byte select lines, and separate
read and write signals.
This option is controlled by the BAT field in the EBI_CSR (Chip Select Register) for the corresponding chip select.
Byte Write Access is used to connect 2 x 8-bit devices as a 16-bit memory page.
• The signal A0/NLB is not used.
• The signal NWR1/NUB is used as NWR1 and enables upper byte writes.
• The signal NWR0/NWE is used as NWR0 and enables lower byte writes.
• The signal NRD/NOE is used as NRD and enables half-word and byte reads.
Figure 11-6 shows how to connect two 512K x 8-bit devices in parallel on NCS2.
1779D–ATARM–14-Apr-06
27
Figure 11-6. Memory Connection for 2 x 8-bit Data Buses
EBI
D0 - D7
D8 - D15
A1 - A19
A0
NWR1
NWR0
NRD
NCS2
D0 - D7
A0 - A18
Write Enable
Read Enable
Memory Enable
D8 - D15
A0 - A18
Write Enable
Read Enable
Memory Enable
Byte Select Access is used to connect 16-bit devices in a memory page.
• The signal A0/NLB is used as NLB and enables the lower byte for both read and write
operations.
• The signal NWR1/NUB is used as NUB and enables the upper byte for both read and write
operations.
• The signal NWR0/NWE is used as NWE and enables writing for byte or half-word.
• The signal NRD/NOE is used as NOE and enables reading for byte or half-word.
Figure 11-7 shows how to connect a 16-bit device with byte and half-word access (e.g., 16-bit
SRAM) on NCS2.
28
Figure 11-7. Connection for a 16-bit Data Bus with Byte and Half-word Access
Figure 11-8 shows how to connect a 16-bit device without byte access (e.g., Flash) on NCS2.
AT91M42800A
EBI
D0 - D7
D8 - D15
A1 - A19
NLB
NUB High Byte Enable
NWE
NOE
NCS2
D0 - D7
D8 - D15
A0 - A18
Low Byte Enable
Write Enable
Output Enable
Memory Enable
1779D–ATARM–14-Apr-06
AT91M42800A
Figure 11-8. Connection for a 16-bit Data Bus without Byte Write Capability
11.8 Boot on NCS0
EBI
D0 - D7
D8 - D15
A1 - A19
NLB
NUB
NWE
NOE
NCS2
D0 - D7
D8 - D15
A0 - A18
Write Enable
Output Enable
Memory Enable
Depending on the device and the BMS pin level during the reset, the user can select either an
8-bit or 16-bit external memory device connected on NCS0 as the Boot memory. In this case,
EBI_CSR0 (Chip Select Register 0) is reset at the following configuration for chip select 0:
• 8 wait states (WSE = 0 - wait states disabled)
• 8-bit or 16-bit data bus width, depending on BMS
Byte access type and number of data float time are set to Byte Write Access and 0,
respectively.
Before the remap command, the user can modify the chip select 0 configuration, programming
the EBI_CSR0 with the exact Boot memory characteristics. The base address becomes effective after the remap command.
11.9 Read Protocols
Warning: In the internal oscillator bypass mode described in ”Operating Modes” on page 12,
the user must take the external oscillator frequency into account according to the minimum
access time on the boot memory device.
As illustration, the following table gives examples of oscillator frequency limits according to the
time access without using NWAIT pin at the boot.
Chip Select Assertion to Output Data Valid
Maximum Delay in Read Cycle (t
110 7
90 9
70 11
55 14
25 24
Note: Values take only tCE into account.
in ns)
CE
External Oscillator
Frequency Limit (MHz)
The EBI provides two alternative protocols for external memory read access: standard and
early read. The difference between the two protocols lies in the timing of the NRD (read cycle)
waveform.
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The protocol is selected by the DRP field in EBI_MCR (Memory Control Register) and is valid
for all memory devices. Standard read protocol is the default protocol after reset.
Note: In the following waveforms and descriptions, NRD represents NRD and NOE since the two sig-
11.9.1 Standard Read Protocol
Standard read protocol implements a read cycle in which NRD and NWE are similar. Both are
active during the second half of the clock cycle. The first half of the clock cycle allows time to
ensure completion of the previous access as well as the output of address and NCS before the
read cycle begins.
During a standard read protocol, external memory access, NCS is set low and ADDR is valid
at the beginning of the access while NRD goes low only in the second half of the master clock
cycle to avoid bus conflict (see Figure 11-9).
Figure 11-9. Standard Read Protocol
nals have the same waveform. Likewise, NWE represents NWE, NWR0 and NWR1 unless
NWR0 and NWR1 are otherwise represented. ADDR represents A0 - A23 and/or
A1 - A23.
MCKI
ADDR
NWE is the same in both protocols. NWE always goes low in the second half of the master
clock cycle (see Figure 11-11 on page 31).
11.9.2 Early Read Protocol
Early read protocol provides more time for a read access from the memory by asserting NRD
at the beginning of the clock cycle. In the case of successive read cycles in the same memory,
NRD remains active continuously. Since a read cycle normally limits the speed of operation of
the external memory system, early read protocol can allow a faster clock frequency to be
used. However, an extra wait state is required in some cases to avoid contentions on the
external bus.
NCS
NRD
or
NWE
30
AT91M42800A
1779D–ATARM–14-Apr-06
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