ATMEL AT91FR40162S User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Incorporates the ARM7TDMI
– High-performance 32-bit RISC Architecture
– High-density 16-bit Instruction Set
– Leader in MIPS/Watt
– Embedded ICE (In-circuit Emulation)
• 256K Bytes of On-chip SRAM
– 32-bit Data Bus, Single-clock Cycle Access
• 1024K Words 16-bit Flash Memory (2M bytes)
– Single Voltage Read/Write,
– Sector Erase Architecture
– Erase Suspend Capability
– Low-power Operation
– Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection
– Reset Input for Device Initialization
– Sector Program Unlock Command
– 128-bit Protection Register
– Factory-programmed AT91 Flash Memory Uploader Software
• Fully Programmable External Bus Interface (EBI)
– Up to 8 Chip Selects, Maximum External Address Space of 64M Bytes
– Software Programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller
– 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
– 3 External Clock Inputs, 2 Multi-purpose I/O Pins per Channel
• 2 USARTs
– 2 Dedicated Peripheral Data Controller (PDC) Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features
– CPU and Peripherals Can be De-activated Individually
• Fully Static Operation:
– 0 Hz to 75 MHz Internal Frequency Range at VDDCORE = 1.8V, 85°C
• 2.7V to 3.6V I/O Operating Range, 1.65V to 1.95V Core Operating Range
• -40°C to 85° C Temperature Range
• Available in a 121-ball 10 x 10 x 1.2 mm BGA Package with 0.8 mm Ball Pitch
®
ARM® Thumb® Processor Core
AT91 ARM®
Thumb
®
Microcontrollers
AT91FR40162S
Summary
Preliminary
1. Description
The AT91FR40162S is a member of the Atmel AT91 16/32-bit Microcontroller family,
which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low
power consumption.
The AT91FR40162S ARM microcontroller features 2 Mbits of on-chip SRAM and 2
Mbytes of Flash memory in a single compact 121-ball BGA package. Its high level of
integration and very small footprint make the device ideal for space-constrained applications. The high-speed on-chip SRAM enables a performance of up to 74 MIPs in
typical conditions with significant power reduction and EMC improvement over an
external SRAM implementation.
The Flash memory may be programmed via the JTAG/ICE interface or the factoryprogrammed Flash Memory Uploader (FMU) using a single device supply, making the
AT91FR40162S suitable for in-system programmable applications.
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2. Pin Configuration
Figure 2-1. AT91FR40162S Pinout for 121-ball BGA Package (Top View)
A1 Corner
1110987654321
P21/TXD1
NTRI
P22
RXD1
VDDIO
P23
P24
BMS
GND
TDO
P26
NCS2
NWAIT
NCS1
GND
P19 P16 GND
P20
SCK1
GND
MCKI NRST
P25
MCK0
TMS GND TCK D8 NC NC
NWE
NWR0
VDDCORE VDDIO NC
GND
NLB
A0
A1 A4 A6 VDDIO A18
P15
RXD0
P18 P17
NUB
NWR1
NWDOVF A3 NC NC D3
A2 TDI D6 GND NC
P27
NCS3
GND A7 A17
P14
TXD0
P13
SCK0
A5 A19 VDDIO
P12
FIQ
NBUSY P9
VPP NRSTF A14 A15
A8 D11 D10 D13
NOE
NRD
NCS0 D2 D5 D4
NCSF NC D0 D1
NC VDDIO GND GND
VDDIO A10 A13 GND
VDDIO A9 A12 GND
P11
VDDCORE
IRQ2
P10
VDDIO
IRQ1
IRQ0P5TIOB1P3TCLK1
D9
A11 D7
P8
TIOB2P6TCLK2
P7
TIOA2P4TIOA1
GND
GND
A16
D12 D14 VDDIO
P31/A23
CS4
D15
NC NC
P29/A21
CS6
P30/A22
VDDCORE
P2
TIOB0
P1
TIOA0
P0
TCLK0
CS5
A20
A
B
C
D
E
F
G
H
J
K
L
2
AT91FR40162S
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3. Pin Description
Table 3-1. AT91FR40162S Pin Description
Module Name Function Type
AT91FR40162S
Active
Level Comments
EBI
AIC
Timer
A0 - A23 Address Bus Output –
D0 - D15 Data Bus I/O –
NCS0 - NCS3 External Chip Select Output Low Used to select external devices
CS4 - CS7 External Chip Select Output High A23 - A20 after reset
NWR0 Lower Byte 0 Write Signal Output Low Used in Byte Write option
NWR1 Upper Byte 1 Write Signal Output Low Used in Byte Write option
NRD Read Signal Output Low Used in Byte Write option
NWE Write Enable Output Low Used in Byte Select option
NOE Output Enable Output Low Used in Byte Select option
NUB Upper Byte Select Output Low Used in Byte Select option
NLB Lower Byte Select Output Low Used in Byte Select option
NWAIT Wait Input Input Low
BMS Boot Mode Select Input –
FIQ Fast Interrupt Request Input – PIO-controlled after reset
IRQ0 - IRQ2 External Interrupt Request Input – PIO-controlled after reset
TCLK0 - TCLK2 Timer External Clock Input – PIO-controlled after reset
TIOA0 - TIOA2 Multi-purpose Timer I/O Pin A I/O – PIO-controlled after reset
Valid after reset; do not reprogram A20 to
I/O, as it is MSB of Flash address
Sampled during reset; must be driven low
during reset for Flash to be used as boot
memory
TIOB0 - TIOB2 Multi-purpose Timer I/O Pin B I/O – PIO-controlled after reset
SCK0 - SCK1 External Serial Clock I/O – PIO-controlled after reset
USART
PIO P0 - P31 Parallel IO Line I/O –
WD NWDOVF Watchdog Overflow Output Low Open drain
Clock
Reset
ICE
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TXD0 - TXD1 Transmit Data Output Output – PIO-controlled after reset
RXD0 - RXD1 Receive Data Input Input – PIO-controlled after reset
MCKI Master Clock Input Input – Schmidt trigger
MCKO Master Clock Output Output –
NRST Hardware Reset Input Input Low Schmidt trigger
NTRI Tri-state Mode Select Input Low Sampled during reset
TMS Test Mode Select Input – Schmidt trigger, internal pull-up
TDI Test Data Input Input – Schmidt trigger, internal pull-up
TDO Test Data Output Output –
TCK Test Clock Input – Schmidt trigger, internal pull-up
3
Table 3-1. AT91FR40162S Pin Description (Continued)
Module Name Function Type
NCSF Flash Memory Select Input Low Enables
Flash
Memory
NBUSY Flash Memory Busy Output Output Low Flash RDY/BUSY
NRSTF Flash Memory Reset Input Input Low Resets Flash to standard operating mode
Active
Level Comments
Flash Memory when pulled low
signal; open-drain
Power
VDDIO Power Power –
VDDCORE Power Power –
GND Ground Ground –
VPP Write Protection Input Low
All V
DDIO, VDDCORE
MUST be connected to their respective
supplies by the shortest route
Provides data protection (Program/Erase)
when VPP input is below 0.4V
and all GND pins
4
AT91FR40162S
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4. Block Diagram
Figure 4-1. AT91FR40162S
D0-D15
A1- A19
A0/NLB
A20
NWR1/NUB
NWAIT
NCS0
NCS1
NRD/NOE
NWR0/NWE
P26/NCS2
P27/NCS3
P29/A21/CS6
P30/A22/CS5
P31/A23/CS4
GND
VPP
VDDIO
VDDIO
NRSTF
NCSF
NBUSY
P0/TCLK0
P3/TCLK1
P6/TCLK2
P1/TIOA0
AT91FR40162S
P2/TIOB0
P4/TIOA1
P5/TIOB1
P7/TIOA2
P8/TIOB2
D0 - D15
ASB
A0/NLB
A1 - A19
P28/A20/NCS7
VPP
VCC
GND
OE WE
A0 - A18
D0 - D15
A19
FLASH MEMORY
EBI: External Bus Interface
Interface
EBI User
AMBA Bridge
MCU
APB
CE
BYTE
RESET
RDY/BUSY
I
P
O
AT91R40008
TC0
Counter
TC: Timer
TC1
TC2
6174AS–ATARM–25-May-05
ARM7TDMI Core
ICE
Embedded
TDI
TCK
TMS
TDO
SRAM
256K Bytes
GND
VDDIO
VDDCORE
Reset
NRST
ASB
Controller
Clock
MCKI
P25/MCKO
AIC: Advanced
Interrupt Controller
P12/FIQ
P9/IRQ0
P10/IRQ1
P11/IRQ2
2 PDC
Channels
USART0
P14/TXD0
P13/SCK0
P15/RXD0
2 PDC
Channels
USART1
I
P
O
P16
P20/SCK1
P22/RXD1
P21/TXD1/NTRI
Chip ID
PS: Power Saving
P17
P18
P19
P23
P24/BMS
PIO: Parallel I/O Controller
WD: Watchdog Timer
NWDOVF
5
5. Architectural Overview
The AT91FR40162S integrates Atmel’s AT91R40008 ARM Thumb processor and a 2-Mbyte
(16-Mbit) Flash memory die in a single compact 121-ball BGA package. The address, data
and control signals, except the Flash memory enable, are internally interconnected.
The AT91R40008 architecture consists of two main buses, the Advanced System Bus (ASB)
and the Advanced Peripheral Bus (APB). Designed for maximum performance and controlled
by the memory controller, the ASB interfaces the ARM7TDMI processor with the on-chip 32-bit
SRAM memory, the External Bus Interface (EBI) connected to the encapsulated Flash and the
™
AMBA
peripherals and optimized for low power consumption.
The AT91FR40162S implements the ICE port of the ARM7TDMI processor on dedicated pins,
offering a complete, low-cost and easy-to-use debug solution for target debugging.
5.1 Memories
The AT91FR40162S embeds 256K bytes of internal SRAM. The internal memory is directly
connected to the 32-bit data bus and is single-cycle accessible. This provides maximum performance of 67 MIPS at 75 MHz by using the ARM instruction set of the processor, minimizing
system power consumption and improving on the performance of separate memory solutions.
The AT91FR40162S features an External Bus Interface (EBI), which enables connection of
external memories and application-specific peripherals. The EBI supports 8- or 16-bit devices
and can use two 8-bit devices to emulate a single 16-bit device. The EBI implements the early
read protocol, enabling faster memory accesses than standard memory interfaces.
Bridge. The AMBA Bridge drives the APB, which is designed for accesses to on-chip
5.2 Peripherals
The AT91FR40162S encapsulates a Flash memory organized as 1024K 16-bit words,
accessed via the EBI. A 16-bit Thumb instruction can be loaded from Flash memory in a single
access. Separate MCU and Flash memory reset inputs (NRST and NRSTF) are provided for
maximum flexibility. The user is thus free to tailor the reset operation to the application.
The AT91FR40162S integrates resident boot software called AT91 Flash Memory Uploader
software in the encapsulated Flash. The AT91 Flash Memory Uploader software is able to
upload program application software into its Flash memory.
The AT91FR40162S integrates several peripherals, which are classified as system or user
peripherals.
All on-chip peripherals are 32-bit accessible by the AMBA Bridge, and can be programmed
with a minimum number of instructions. The peripheral register set is composed of control,
mode, data, status and enable/disable/status registers.
An on-chip Peripheral Data Controller (PDC) transfers data between the on-chip USARTs and
on- and off-chip memory address space without processor intervention. Most importantly, the
PDC removes the processor interrupt handling overhead, making it possible to transfer up to
64K contiguous bytes without reprogramming the start address, thus increasing the performance of the microcontroller, and reducing the power consumption.
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AT91FR40162S
6174AS–ATARM–25-May-05
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