AT91EB42
Evaluation Board
.............................................................................
User Guide
Table of Contents
Section 1
Overview............................................................................................... 1-1
1.1 Scope........................................................................................................1-1
1.2 Deliverables ..............................................................................................1-1
1.3 The AT91EB42 Evaluation Board .............................................................1-1
Section 2
Setting Up the AT91EB42
Evaluation Board .................................................................................. 2-1
2.1 Electrostatic Warning ................................................................................2-1
2.2 Requirements............................................................................................2-1
2.3 Layout .......................................................................................................2-1
2.4 Jumper Settings ........................................................................................2-2
2.5 Powering Up the Board.............................................................................2-2
2.6 Measuring Current Consumption on the AT91M42800 ............................2-2
2.7 Testing the AT91EB42 Evaluation Board .................................................2-2
Section 3
The On-board Software ........................................................................3-1
3.1 AT91EB42 Evaluation Board ....................................................................3-1
3.2 Boot Software Program.............................................................................3-1
3.3 Programmed Default Memory Mapping ....................................................3-2
3.4 SRAM Downloader ...................................................................................3-2
3.5 Angel Monitor ............................................................................................3-2
3.6 Programmed Default Speed .....................................................................3-2
Section 4
Circuit Description.................................................................................4-1
4.1 AT91M42800 Processor ...........................................................................4-1
4.2 Expansion Connectors and JTAG Interface..............................................4-1
4.2.1 I/O Expansion Connector ...................................................................4-1
4.2.2 EBI Expansion Connector ..................................................................4-1
4.2.3 JTAG Interface ...................................................................................4-1
4.3 Memories ..................................................................................................4-2
4.4 Analog-to-digital Converter .......................................................................4-2
4.5 Power and Crystal Quartz.........................................................................4-2
4.6 Push Buttons, LEDs, Reset and Serial Interfaces ....................................4-2
4.7 Layout Drawing .........................................................................................4-3
i
Table of Contents
Section 5
Appendix A – Configuration Straps....................................................... 5-1
5.1 Configuration Straps (CB1 - 23, JP1 - 8) ..................................................5-1
5.2 Power Consumption Measurement Strap (JP5) .......................................5-4
5.3 Ground Links (JP6) ...................................................................................5-4
5.4 Increasing Memory Size ...........................................................................5-4
Section 6
Appendix B – Schematics..................................................................... 6-1
6.1 Schematics ...............................................................................................6-1
ii
Section 1
Overview
1.1 Scope The AT91EB42 Evaluation Board enables real-time code development and evaluation.
It supports the AT91M42800.
This guide focuses on the AT91EB42 Evaluation Board as an evaluation and demonstration platform:
Section 1 provides an overview.
Section 2 describes how to set up the evaluation board.
Section 3 details the on-board software.
Section 4 contains a description of the circuit board.
Section 5 and Section 6 are two appendices covering configuration straps and
schematics, including pin connectors.
1.2 Deliverables The evaluation board is delivered with a DB9 plug-to-DB9 socket straight-through serial
cable to connect the target evaluation board to a PC. A bare power lead with a 2.1 mm
jack on one end for connection to a bench power supply is also delivered.
The evaluation board is also delivered with a CD-ROM that contains an evaluation version of the software development toolkit and the documentation that outlines the AT91
microcontroller family.
The evaluation board is capable of supporting different kinds of debugging systems,
using an ICE interface or the on-board Angel Debug Monitor. Refer to the AT91EB42
Getting Started Tutorial documents for recommendations on using the evaluation board
in a full debug environment.
1.3 The AT91EB42 Evaluation Board
AT91EB42 Evaluation Board User Guide 1-1
The board consists of an AT91M42800 together with several peripherals:
Two serial ports
Reset push button
Four user-defined push buttons
Eight LEDs
a 256 KB 16-bit SRAM (upgradeable to 1M byte)
a 2 MB 16-bit Flash (of which 1M byte is available for user software)
a 4 MB Serial Data Flash
a 64 KB Serial EEPROM
a 32 KB SPI EEPROM
Overview
2 x 32-pin EBI expansion connectors
2 x 32-pin I/O expansion connectors
20-pin JTAG interface connector
If required, user-defined peripherals can also be added to the board. See Section 5 for
details.
Figure 1-1. AT91EB42 Evaluation Board Block Diagram
AT91M42800
Reset
Controller
JTAG
ICE
Connector
ARM7TDMI
Processor
8K Byte
RAM
ASB
EBI
SRAM
EBI
Expansion
Connector
Flash
2.1mm DC
Power
Socket
Fast-charge
Controller
32.768 KHz
Crystal
Push-buttons
Reset
Controller
Power Supply
Battery
Connector
Clock
Generator
Interrupt
Controller
System
Timer
Watchdog
Reset
PIO
APB
AMBA
Bridge
PIO
Timer
Counters
SPI
Serial
Ports
Serial
EEPROM
Serial
Data
Flash
RS232
Transceivers
LEDs
I/O
Expansion
Connector
Serial
EEPROM
DB9 Serial
Connectors
1-2 AT91EB42 Evaluation Board User Guide
Section 2
Setting Up the AT91EB42
Evaluation Board
2.1 Electrostatic Warning
2.2 Requirements Requirements in order to set up the AT91EB42 Evaluation Board are:
2.3 Layout Figure 2-1 shows the layout of the AT91EB42 Evaluation Board.
The AT91EB42 Evaluation Board is shipped in protective anti-static packaging. The
board must not be subjected to high electrostatic potentials. A grounding strap or similar
protective device should be worn when handling the board. Avoid touching the component pins or any other metallic element.
The AT91EB42 Evaluation Board itself
The DC power supply capable of supplying 7.5V to 9V at 1A (not supplied)
Figure 2-1. Layout of the AT91EB42 Evaluation Board
AT91EB42 Evaluation Board User Guide 2-1
Setting Up the AT91EB42 Evaluation Board
2.4 Jumper Settings JP1 is used to boot standard or user programs. For standard operations, set it in the
STD position.
JP8 is used to select the core power supply of the AT91M42800: 3.3V or 1.8V. For operation at 1.8V, MCK frequency shall be limited to 17 MHz.
For more information about jumpers and other straps, see Section 5.
2.5 Powering Up the Board
2.6 Measuring Current Consumption on the AT91M42800
DC power is supplied to the board via the 2.1 mm socket (J1) shown in Figure 2-2. The
polarity of the power supply is not critical. The minimum voltage required is 7V.
Figure 2-2. 2.1 mm Socket
positive (+)
or
negative (-)
2.1 mm connector
A battery power supply can be connected to the board via the J3 connector. A battery
fast-charge controller is provided on-board to charge this battery.
The board has a voltage regulator providing +3.3V. The regulator allows the input voltage to range from 7
V to 9V. When you switch the power on, the red LED marked
POWER lights up. If it does not, switch off and check the power supply connections.
The board is designed to generate the power for the AT91 product, and only the AT91
product, through the jumper JP5 (V
) and JP8 (V
DDIO
DDCORE
). This feature enables mea-
surements to be made of the current consumption of the AT91 product.
See Section 5 for further details.
2.7 Testing the AT91EB42 Evaluation Board
To test the AT91EB42 Evaluation Board, perform the following steps:
1. Hold down the SW1 button and power-up the board, or generate a reset and wait
for the light sequence on each LED to complete. All the LEDs light once and the
LED D1 remains lit.
2. Release the SW1 button. The LEDs D1 to D7 light up one after the other. If any
of the LEDs lights up twice, there is an error.
The LEDs represent the following components:
D1 for the internal RAM
D2 for the external RAM
D3 for the external Flash
D4 for the serial EEPROM
D5 for the SPI DataFlash
D6 for the EEPROM
D7 for the USART
D8 is reserved
®
If a test is not carried out, the corresponding LED remains unlit and the test sequence
restarts.
2-2 AT91EB42 Evaluation Board User Guide
Section 3
The On-board Software
3.1 AT91EB42 Evaluation Board
3.2 Boot Software Program
The AT91EB42 Evaluation Board embeds an AT49BV1604 Flash memory device programmed with default software. Only the lowest 8 x 8 KB sectors are used. The
remaining sectors are user definable, and can be programmed using one of the Flash
downloader solutions offered in the AT91 library.
When delivered, the Flash memory device contains:
the boot program
the functional test software
the SRAM downloader
the Angel Debug Monitor
a default user boot with a default application
The boot program, functional test software (FTS) and SRAM downloader are in sector 0
of the Flash. This sector is locked to prevent accidental erase, but it can be unlocked by
applying 12V to the RESET pin.
The boot software program configures the AT91M42800, and thus controls the memory
and other board components.
The boot software program is started at reset if JP1 is in the STD position. If JP1 is in
the USER position, the AT91M42800 boots from address 0x01010000 in the Flash,
which must have a user-defined boot.
The boot software program first initializes the EBI, then executes the REMAP procedure, and then checks the state of the buttons.
When the button SW1 is pressed:
All the LEDs light up together.
The D1 LED remains lit until SW1 is released.
The functional test software (FTS) is started.
When the button SW2 is pressed:
All the LEDs light up together.
The D2 LED remains lit until SW2 is released.
The SRAM downloader is activated.
When SW3 or SW4 are pressed or no buttons are pressed:
Branch at address 0x0100 2000.
The Angel Debug Monitor starts from this address by recopying itself in external
SRAM.
AT91EB42 Evaluation Board User Guide 3-1
The On-board Software
3.3 Programmed Default Memory Mapping
3.4 SRAM Downloader
Table 3-1 defines the mapping defined by the boot program.
Table 3-1. Memory Map
Part Name Start Address End Address Size Device
U1 0x01000000 0x011FFFFF 2M Bytes
U2-U3 0x02000000 0x02040000 256K Bytes SRAM
The boot software program, FTS and SRAM downloader are in sectors 1 and 2 of the
Flash device. Sectors 2 to 8 support the Angel Debug Monitor.
Sector 24 at address 0x0110 0000 must be programmed with a boot sequence to be
debugged. This sector can be mapped at address 0x0100 0000 (or 0x0 after a reset)
when the jumper JP1 is in the USER position.
The SRAM downloader allows an application to be loaded in the SRAM at the address
0x02000000, then activated. It is started by the boot if the SW2 button is pressed at
reset.
The procedure is as follows:
1. Connect the AT91EB42 Evaluation Board to the host PC serial “A” connection
using the straight serial cable provided.
2. Power-on or press “RESET”, holding down the SW2 button at the same time.
Wait for D2 to light up and then release SW2.
3. Start the BINCOM utility, available in the AT91 library, on the host computer:
Select the port for communications (COM1 or COM2, depending on where you connected the serial cable on the host PC) and the baud rate for communications
(115200 bds, 1 stop bit, no parity).
Open the file to be downloaded and send it. Wait for the end of the transfer.
4. Press any button to end the download. The control is switched to the address
0x02000000.
Flash
AT49BV1604
3.5 Angel Monitor The Angel monitor is located in the Flash from 0x01002000 up to 0x0100FFFF. The
boot program starts it if no button is pressed at reset.
When Angel starts, it recopies itself in SRAM in order to run faster. The SRAM used by
Angel is from 0x02020000 to 0x02040000, i.e., the highest half part of the SRAM.
The Angel on the AT91EB42 Evaluation Board can be upgraded regardless of the version programmed on it.
Note that if the debugger is started through ICE while the Angel monitor is on, the
Advanced Interrupt Controller (AIC) and the USART channel are enabled.
3.6 Programmed Default Speed
3-2 AT91EB42 Evaluation Board User Guide
As the speed of the AT91M42800 is programmable, the boot software program initializes the device to run as fast as possible, i.e., at 40 MHz. The boot software program
and the functional test software are run at this speed. The SRAM downloader, after initialization of the USARTs, enters the processor in idle mode and activates the
downloaded application at this speed. When Angel is started, it also runs at 40 MHz and
the user should not modify this frequency without reprogramming the speed of the
USARTs.
Section 4
Circuit Description
4.1 AT91M42800 Processor
4.2 Expansion Connectors and JTAG Interface
4.2.1 I/O Expansion Connector
Figure 6-1 on page 6-2 shows the AT91M42800. The footprint is for a 144-pin TQFP
package.
Strap CB20 enables the user to choose between the standard ICE debug mode and the
JTAG boundary scan mode of operation.
The operating mode is defined by the state of the JTAGSEL input detected at reset.
Jumper JP5 (see Figure 6-8 on page 6-9 in Section 6, “Appendix B – Schematics”) can
be removed by the user to allow measurement of the current demand by the whole
microcontroller (V
microcontroller consumption (V
The two expansion connectors, I/O expansion connector and EBI expansion connector,
and the JTAG interface are described below.
The I/O and EBI expansion connectors’ pinout and position are compatible with the
other evaluation boards (except the I/O expansion connector pinout and position of the
EB40) so that users can connect their prototype daughter boards to any of these evaluation boards.
The I/O expansion connector makes the general-purpose I/O (GPIO) lines, VCC3V3
and Ground, available to the user. Configuration straps CB2, CB3, CB4, CB11, CB13,
CB14, CB15, CB17, CB18 and CB19 are used to select between the I/O lines being
used by the evaluation board or by the user via the I/O expansion connector. The connector is not fitted at the factory; however, the user can fit any 32 x 2 connector on a 0.1"
(2.54 mm) pitch.
DDIO
and V
DDCORE
). Jumper JP8 can be removed to measure the core
DDCORE
).
4.2.2 EBI Expansion Connector
4.2.3 JTAG Interface An ARM
AT91EB42 Evaluation Board User Guide 4-1
The schematic (Figure 6-4 on page 6-5 in Section 6, “Appendix B – Schematics”) also
shows the bus expansion connector which, like the I/O expansion connector, is not fitted
at the factory. The user can fit any 32 x 2 connector on a 0.1" (2.54 mm) pitch to gain
access to the data, address, chip select, read/write, oscillator output and wait request
pins. VCC3V3 and ground are also available on this connector.
Configuration strap CB1, when open, allows the user to connect the EBI expansion connector to the MPI expansion connector of an AT91EB63 evaluation board without any
conflicts.
®
-standard 20-pin box header (P5) is provided to enable connection of an ICE
interface to the JTAG inputs on the AT91. This allows code to be developed on the
board without using system resources such as memory and serial ports.
Circuit Description
4.3 Memories The schematic (Figure 6-3 on page 6-4 in Section 6, “Appendix B – Schematics”) shows
one AT49BV1604 2 MB 16-bit Flash, one AT45DB321 4 MB serial DataFlash, one
AT24C512 64 KB EEPROM, one AT25256 32 KB EEPROM and two 128K/512K x 8
SRAM devices.
Note: The AT91EB42 is fitted with two 128K x 8 SRAM devices.
A footprint is provided for the user to fit a multi-chip device memory that embeds Flash
(1 MB) and SRAM (128 KB) in a single component in place of the Flash and SRAM
devices (U7: M36W108AB from ST).
Strap JP1 shown on the schematic is used to select the part of 1 MB of the Flash to be
accessed. This is to enable users to Flash download their application in the second part
of the Flash and to boot on it.
4.4 Analog-to-digital Converter
4.5 Power and Crystal Quartz
A footprint is provided for the user to fit a 4-channel 10-bit ADC device (AD7817ARU
from Analog Devices; see Figure 6-10 on page 6-11 in Section 6, “Appendix B – Schematics”). This device is interfaced to the AT91 microcontroller via the SPIA peripheral.
The voltage reference used is the 2.5V on-chip.
This device embeds a temperature sensor and is placed near the 32.768 KHz crystal
quartz. Thus the user is able to take into account the frequency drift due to temperature
evolution by a software program.
By default, two of the ADC channels are dedicated to supervise the board power supply
voltage levels (channel 1 for the battery power supply, channel 2 for the standard power
supply).
The AT91M42800 master clock is derived from a 32.768 KHz crystal quartz. The onchip low-power oscillator together with two PLL-based frequency multipliers and the
prescaler results in a programmable master clock between 500 Hz and 33 MHz.
Two sets of components for the PLL filters are fitted by default on the board (Figure 6-6
on page 6-7 in Section 6, "Appendix B - Schematics"). They are calculated to provide a
16.77 MHz (PLLA: multiplier factor of 512 and settling time of 600
(PLLB: multiplier factor of 1024 and settling time of 4 ms) master clock frequency.
The voltage regulator provides 3.3V to the board and will light the red POWER LED
(D11) when operating.
Power can be applied via the 2.1 mm connector to the regulator in either polarity
because of the diode-rectifying circuit. Another regulator allows the user to power the
AT91M42800 core with 3.3V or 1.8V by means of the JP8 jumper.
A battery power supply can be applied via the J3 connector. The type of battery and
connections to be used are shown in the schematics (Figure 6-9 on page 6-10 in Section 6, "Appendix B - Schematics"). This type of battery will ensure the power supply of
the board for approximately 30 minutes. A battery fast-charge controller is provided onboard to charge this battery. The number of series cells to be charged is set to 5, but
can be changed via the CB21, CB22 and CB32 configuration straps. The maximum time
allowed for fast-charging is set to 264 minutes.
=µs) or a 33.55 MHz
4.6 Push Buttons, LEDs, Reset and Serial Interfaces
4-2 AT91EB42 Evaluation Board User Guide
The IRQ0, TIOA0, PB6 and PB21 switches are debounced and buffered.
A supervisory circuit has been included in the design to detect and consequently reset
the board when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be
changed depending on the board production series. The supervisory circuit also provides a debounced reset signal. This device can also generate the reset signal in case
Circuit Description
of watchdog time-out as the pin NWDOVF of the AT91M42800 is connected to its input
.
MR
The assertion of this reset signal will light up the red RESET LED (D10). By pressing the
CLEAR RESET push button (S1), the LED can be turned off.
Another supervisory circuit initializes separately the microcontroller-embedded
JTAG/ICE interface when the 3.3V supply voltage drops below 3.0V. Note that this voltage can be changed, depending on the board production series. These separated reset
lines allow the user to reset the board without resetting the JTAG/ICE interface while
debugging.
The schematic (Figure 6-5 on page 6-6 in Section 6, "Appendix B - Schematics") also
shows eight general-purpose LEDs connected to port B PIO pins (PB8 to PB15).
Two 9-way D-type connectors (P3/4) are provided for serial port connection.
Serial port A (P3) is used primarily for host PC communication and is a DB9 female connector. TXD and RXD are swapped so that a straight-through cable can be used. CTS
and RTS are connected together, as are DCD, DSR and DTR.
Serial port B (P4) is a DB9 male connector with TXD and RXD obeying the standard
RS-232 pinout. Apart from TXD, RXD and ground, the other pins are not connected.
LEDs are connected to the TX and RX signals of both serial ports and show activity on
these serial links.
A MAX3223 device (U10) and associated bulk storage capacitors provide RS-232 level
conversion.
4.7 Layout Drawing The layout diagram (Figure 6-1 on page 6-2 in Section 6, “Appendix B – Schematics”)
shows an approximate floorplan for the board. This has been designed to give the lowest board area, while still providing access to all test points, jumpers and switches on
the board.
The board is provided with four mounting holes, one at each corner, into which feet are
attached. The board has two signal layers and two power planes.
AT91EB42 Evaluation Board User Guide 4-3
Circuit Description
4-4 AT91EB42 Evaluation Board User Guide
Section 5
Appendix A – Configuration Straps
5.1 Configuration Straps (CB1 - 23, JP1 - 8)
By adding the I/O and EBI expansion connectors, users can connect their own peripherals to the evaluation board. These peripherals may require more I/O lines than available
while the board is in its default state. Extra I/O lines can be made available by disabling
some of the on-board peripherals or features. This is done using the configuration straps
detailed below. Some of these straps present a default wire (notified by the default mention) that must be cut before soldering the strap.
CB1 On-board PB5/A23/CS4 Signal
(1)
Closed
Open AT91 PB5/A23/CS4 signal is not connected to the EBI expansion connector
CB2, CB3,
CB4 ADC Enabling
(1)
Closed
Open ADC (U20) control lines disabled. This authorizes users to connect the
AT91 PB5/A23/CS4 signal is connected to the EBI expansion connector
(P1-B21).
(P1-B21).
This authorizes users to connect the EBI expansion connector of this board
to the MPI expansion connector of an AT91EB63 Evaluation Board without
conflict problems.
ADC (U20) control lines enabled
corresponding PIO to their own resources via the I/O expansion connector.
CB5 Battery Power Supply Supervisory Enabling
(1)
Closed
Open Battery power supply is not connected to the ADC (U20) channel 1. This
Battery power supply is supervised by the ADC (U20) channel 1 via a
resistor bridge. The ratio is set to 0.3333 so that the battery voltage range
can be supervised (5.5V to 6.2V).
authorizes users to connect the corresponding ADC channel to their own
resources via the I/O expansion connector.
AT91EB42 Evaluation Board User Guide 5-1
Appendix A – Configuration Straps
CB7 Standard Power Supply Supervisory Enabling
(1)
Closed
Standard power supply is supervised by the ADC (U20) channel 2 via a
resistor bridge. The ratio is set to 0.1485 so that the standard power supply
can be supervised up to 15V.
Open Standard power supply is not connected to the ADC (U20) channel 2. This
authorizes users to connect the corresponding ADC channel to their own
resources via the I/O expansion connector.
CB6, CB8 ADC Channels 3 and 4 Enabling
Closed
(1)
ADC (U20) channels 3 and 4 are connected to ground.
Open ADC (U20) channels 3 and 4 are not connected to ground. This authorizes
users to connect the corresponding ADC channel to their own resources via
the I/O expansion connector.
CB9 On-board Boot Chip Select
Closed
(1)
AT91 NCS0 select signal is connected to the Flash memory.
Open AT91 NCS0 select signal is not connected to the Flash memory. This
authorizes users to connect the corresponding select signal to their own
resources via the EBI expansion connector.
CB10 Flash Reset
(1)
Closed
The on-board reset signal is connected to the Flash NRESET input.
Open The on-board reset signal is not connected to the Flash NRESET input.
CB11 PB22 Ready/Busy MCM Memory Signal
(1)
Closed
AT91 PB22 signal is connected to the multi-chip device memory (U7),
Ready/Busy output pin
Open AT91 PB22 signal is not connected to the multi-chip device memory (U7),
Ready/Busy output pin. This authorizes users to connect the corresponding
signal to their own resources via the I/O expansion connector
CB12 Boot Mode Strap Configuration
Open BMS AT91 input pin is set for the microcontroller to boot on an external 16-bit
memory at reset.
Closed
(1)
BMS AT91 input pin is set for the microcontroller to boot on an external 8-bit
memory at reset.
2
CB13, CB14 I
(1)
Closed
C EEPROM Enabling
EEPROM communication enabled
Open EEPROM communication disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
5-2 AT91EB42 Evaluation Board User Guide
Appendix A – Configuration Straps
CB15 Serial DataFlash Enabling
(1)
Closed
Open AT91 NPCSA0 select signal is not connected to the serial DataFlash
CB17 SPI EEPROM Enabling
(1)
Closed
Open EEPROM communication disabled. This authorizes users to connect the
CB18 PB20 ADC Write Access Signal
(1)
Closed
Open AT91 PB20 signal is not used to control the RD/WR ADC (U20) input pin.
AT91 NPCSA0 select signal is connected to the serial DataFlash memory.
memory. This authorizes users to connect the corresponding PIO to their
own resources via the I/O expansion connector.
EEPROM communication enabled
corresponding PIO to their own resources via the I/O expansion connector.
AT91 PB20 signal is used to control the RD/WR ADC (U20) input pin. Prior to
a write access, position this PIO line in a low state. Position it in a high state
prior to a read access.
This authorizes users to connect the corresponding signal to their own
resources via the I/O expansion connector.
CB19 PB18 End of Fast Charge Signal
(1)
Closed
AT91 PB18 signal is connected to the battery charger (U16), NFASTCHG
output pin.
Open AT91 PB18 signal is not connected to the battery charger (U16), NFASTCHG
output pin. This authorizes users to connect the corresponding signal to their
own resources via the I/O expansion connector.
CB20 JTAGSEL
(1)
1-2
AT91 standard ICE debug feature enabled
2-3 IEEE 1149.1 JTAG boundary scan feature enabled
CB21, CB22, CB23 Charger Device (U16): Programming the Battery Number of Cells
Number of Cells CB21 CB22 CB23
1 Open Closed Closed
2 Open Open Closed
4 Closed Open Closed
(1)
5
Open Closed Open
6 Open Open Open
8 Closed Open Open
AT91EB42 Evaluation Board User Guide 5-3
Appendix A – Configuration Straps
JP1 User or Standard Boot Selection
2-3 The first half part of the Flash memory is accessible at its base address.
1-2 The second half part of the Flash memory is accessible at its base address.
This authorizes users to download their own application software in this part
and to boot on it.
JP2 Push Button Enabling
Open SW1-4 inputs to the AT91 are valid.
Closed SW1-4 inputs to the AT91 are not valid. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
JP3 User or Standard Boot Selection
Open The RS-232 transceivers are enabled.
Closed The RS-232 transceivers are disabled. This authorizes users to connect the
corresponding PIO to their own resources via the I/O expansion connector.
JP8 Core Power Supply Selection
5.2 Power Consumption Measurement Strap (JP5)
5.3 Ground Links (JP6)
5.4 Increasing Memory Size
2-3 The AT91 core is powered by 3.3V power supply.
1-2 The AT91 core is powered by 1.8V power supply. In this case, the maximum
frequency that can be used is 17 MHz.
Note: 1. Hardwired default position: To cancel this default configuration, cut the wire on the
board.
The JP5 strap enables connection of an ammeter to measure the AT91M42800 global
consumption (V
DDCORE
and V
DDIO
) when V
DDCORE
power supply is derived from V
DDIO
(JP8 in 3V3 position). Core consumption can be measured by connecting another
ammeter between JP8 1-2 or 2-3, depending on the power supply used to power the
core.
The current measured on E11 is the total current required by the AT91M63200 on both
V
DDIO
and V
. It is also the current consumed by the switching regulator VR1 that
DDPLL
provides the 1.8V.
The JP6 strap allows the user to connect the electrical and mechanical grounds.
The AT91EB42 Evaluation Board is supplied with two 128K x 8 byte SRAM memories.
If, however, the user needs more than 256K bytes of memory, the devices can be
replaced with two 512K x 8 3.3V 10/15 ns SRAMs, giving in total 1024K bytes.
5-4 AT91EB42 Evaluation Board User Guide
Appendix B – Schematics
6.1 Schematics The following schematics are appended:
• Figure 6-1. PCB Layout
• Figure 6-2. AT91EB42 Blocks Overview
• Figure 6-3. EBI Memories
• Figure 6-4. I/O and EBI Expansion Connectors
• Figure 6-5. Push Buttons, LEDs and Serial Interface
• Figure 6-6. AT91M42800
• Figure 6-7. Reset and JTAG Interface
• Figure 6-8. Power Supply and Battery Charger
• Figure 6-9. Battery Type and Connection
2
• Figure 6-10. SPI Memories, I
The pin connectors are indicated on the schematics:
P1 = EBI Expansion Connector (Figure 6-4)
P2 = I/O Expansion Connector (Figure 6-4)
P3 = Serial A (Figure 6-5)
P4 = Serial B (Figure 6-5)
P5 = JTAG Interface (Figure 6-7)
C Memories and SPI ADC
Section 6
AT91EB42 Evaluation Board User Guide 6-1
Appendix B – Schematics
Figure 6-1. PCB Layout
6-2 AT91EB42 Evaluation Board User Guide
AT91EB42 Evaluation Board User Guide 6-3
Figure 6-2. AT91EB42 Blocks Overview
EBI MEMORIES
memo rie s con nect ed on E BI
MICROCO NTRO LLER
micro / Rst / Wchdog / JTAG co.
SUPPLY and RTC SAVE
EBI_[0..42]
IOB_[0..53]
EBI_[0..42]
PB22
PB18
EBI_[0..42]
IOB_32
A20
IOB_52
IOB_[0..53]
IOB_[0..57]
IOB_[0..57] IOB_[0..57]
EBI_[0..42]
EBI_[0..42]
IOB_[0..57]
IOB_16
IOB_15
IOB_14
IOB_13
IOB_12
IOB_11
IOB_3
IOB_49
IOB_50
IOB_46
IOB_47
EBI_41
IOB_[54..57]
IOB_51
IOB_[36..45]
IOB_[6..7]
IOB_[9..10]
IOB_0
NRST
VIN[1..4]
NPCS A2
NPCS A1
NPCS A0
MOSIA
MISOA
SPCKA
IRQ3
PB19
PB20
PB16
PB17
SERIAL MEMORIES
INPUT / OUTPUT ON BOARD
PB21
PB[6..15]
PA[6..7]
PA[9..10]
PA0
Serial Connectors / P.B. / LED
SERIAL MEMORIES
EXTENSIONS CONNECTORS
IOB_48
IOB_[0..57]
IOB_[0..57]
EBI_[0..42]
IOB_[0..57]
EBI_[0..42]
power s upply / batte ry
Extens ion Connec tors
Appendix B – Schematics
Appendix B – Schematics
Figure 6-3. EBI Memories
C4
100nF
A13
A12
24
A514A615A716A817A9
WE
13
A5
NWR1
A13
A12
24
A514A615A716A817A9
WE
13
A5
NWR0
A11
A6
A11
A6
A10
A10
A7
A9
19
NC
A1020A1121A1222A1323A14
18
A8
A19
A9
19
NC
A1020A1121A1222A1323A14
18
A8
A19
VCC3V3VCC3V3VCC3V3VCC3V3
512k512k
IDT71V424S10Y
U5
C3
100nF
C2
100nF
IDT71V424S10Y
U4
C1
100nF
44
NC1NC
44
NC1NC
42
NC43NC
2
A18
42
NC43NC
2
A18
NRD
D15
D13
A1532A16
A1532A16
31
OE
CS
6
NCS1
NRD
31
OE
CS
6
NCS1
30
D18D211D3
D0
7
D8
D9 D14
D6
D7
30
D18D211D3
D0
7
D1
D0
27
28
VCC
GND
GND
VCC
9
10
VCC3V3 VCC3V3
27
28
VCC
GND
GND
VCC
9
10
VCC3V3 VCC3V3
D10
D5
D2
D12
D425D526D629D7
12
D11
D4
D425D526D629D7
12
D3
A14
A16
A15
A17
33
35
36
NC
A1734A18
A01A12A23A34A4
U3
5
A1
A2
A3A7A4
A18
layout for SOJ 400mil.
A14
A15
A16
A17
33
35
36
1Mbytes ( two 512kX8 ) SRAM with two footprints or
256kbytes ( two 128kX8 ) SRAM with two footprints.
NC
A1734A18
128k 128k
512k 512k
A01A12A23A34A4
U2
5
A4
A2
A3
A1
A18
D[0..15]
D0
D2
D1
I/O029I/O131I/O233I/O335I/O438I/O540I/O642I/O744I/O830I/O9
D9
D6
D7
D8
D12
D10
D11
32
I/O1034I/O1136I/O1239I/O1341I/O14
D13
D14
43
45
I/O15
VCC3V3
37
47
VCCQ
VCC
D3
D5
D4
VCC3V3VCC3V3
NRD
D14
D15
D13
D12D4
36
OE
CS
D0
9
D8
D9
D7
D6
36
OE
CS
D0
9
D1
D0
GND27GND
33
34
VCC
GND
GND
VCC
D110D213D3
12
11
14
D11
D10
GND
VCC3V3VCC3V3
D5
33
34
VCC
GND
GND
VCC
D110D213D3
12
11
14
D3
D2
A13
30
D431D532D635D7
WE
15
NWR1
A13
30
D431D532D635D7
WE
15
NWR0
A12
A10
A516A617A718A819A9
A5
A6
A7
A11
A12
A10
A516A617A718A819A9
A7
A5
A6 A11
A17
A16
A15
39
41
37
NC
A1538A16
A1740A18
128k
A03A14A25A36A4
7
8
A4
A1
A3
A2
NCS1
NRD
layout for TSSOP 400mil.
A16
A14 A14
A17
A15
39
41
37
NC
A1538A16
A1740A18
128k
A03A14A25A36A4
8
7
A1
A4
A3
A2
NCS1
C5
100nF
46
A9
25
NC23NC24NC
A1026A1127A1228A1329A14
NC21NC
20
22
A8
A19
A9
25
NC23NC24NC
A1026A1127A1228A1329A14
NC21NC
20
22
A8
A19
CTL0 NWR0 NWE
IDT71424S10PH
A[0..19]
CTL[0..6]
EBI_[16..35]
EBI_[36..42]
EBI_[0..42]
IDT71424S10PH
VCC3V3
D0D1D2D3D4D5D6
DQ0D4DQ1C6DQ2C5DQ3E3DQ4C4DQ5B5DQ6G2DQ7
CTL2 NRD N OEA4CTL1 NWR1 NUB
D[0..15]
EBI_[0..15]
R72
100K
D7
B4
CTL5 NRST
CB11
NCS0CTL4
PB22
1 2
Ready/busy IOB_52
G5
RNB
NCS1CTL6
A20B
STD BOOT
2
3
JP1
jumper_3P
IOB_32
A20
H3
E1
NCC2NCD3NCE2NCF1NCF3NCG1NCH1NC
NC
USER BOOT
1
1
1
U6A
74LVC02AD
2
3
C105
100nF
VCC3V3
C106
B1
VCCFF2VCCS
100nF
B6
VSSD1VSS
2Mbytes FLASH MEMORY
A025A124A223A322A421A520A619A718A88A97A106A124A133A142A151A1648A1717A1816A1915NC9NC10NC14NC / Vpp13CE26WE11OE28RESET
U1
A1
A2
A5
A3
A[0..19]
A11
5
NCS0_1
A9A7A6
A8
A12
A18
A15
A14
A13
A16
A11
A17 D15
A10
A19
A20B
1 2
VCC3V3
R1
100k
CB9
1 2
NWE
NCS0
NOE
CB10
12
NRST_1NRST
1 2
1 2
AT49BV1604-90TC
VCC3V3
R2
100k
A0D5A1D6A2E6A3E5A4F6A5C3A6E4A7F5A8B3A9H6A10A5A11A3A12H2A13G3A14A2A15H5A16
U7
A2A3A4A5A6A7A8A9A10
A1
A0
A11
A12
A13
A14
A15
A17C1A18B2A19
NW
A17
A18
F4
A19
NEF
NRP
D2
G4
NCS0_1
NRST_1
M36W108AB
NG
NE1SA6E2S
A1
A4
H4
G6
A16
NCS1
VCC3V3
NRD
NWR0
6-4 AT91EB42 Evaluation Board User Guide
Figure 6-4. I/O and EBI Expansion Connectors
Appendix B – Schematics
AT91EB42 Evaluation Board User Guide 6-5
Appendix B – Schematics
Figure 6-5. Push Buttons, LEDs and Serial Interface
Usart 0:
SERIAL
A
Usart 1:
SERIAL
B
PB[6..15]
PB[6..15]
VCC3V3
VCC3V3
100R
100R
R6
Red LED
D1
D2 R7
16
18
EN
U8
12468
PB9
PB8
R43
100k
R42
100k
VCC3V3
100R
D3 R8
VCC3V3
100R
14
PB10
VCC3V3
D4 R9
12
PB11
VCC3V3
VCC3V3
VCC3V3
100R
100R
100R
R11
R12
D5 R10
D6
D7
579
EN
1911131517 3
PB12
PB13
PB14
PB21
VCC3V3
100R
D8 R13
GND SIGNAL
PB15
R44
R45
VCC3V3
VCC3V3
20
C13
10
74LV244D
100k
100k
100nF
VCC3V3
C16
P3
DCD0
VCC3V3
100nF
RTS0
CTS0
DSR0
DTR0
TX0
RX0
100nF
C17
3
V+
19
VCC
18
GND
C1+2C1-4C2+5C2-
Sub D 9b F
594837261
C21
22pF
C20
22pF
100nF
C19
7
V-
6
C25
C24
C23
8
T1OUT17T2OUT
T1IN13T2IN
12
10nF
22pF
22pF
9
R1IN16R2IN
R1OUT15R2OUT
10
P4
20
11
INVALID
FORCEOFF
EN1FORCEON
14
TX1
RX1
C27
C26
U10
MAX3223ECAP
594837261
22pF
22pF
VCC3V3
Sub D 9b M
VCC3V3
VCC3V3 VCC3V3
TIOA0PB7
IRQ0PA0
VCC3V3
PB21 TCLK5
PB6 TCLK0
3
6
8
5109
11
13
12
VCC3V3
VCC3V3
14
C12
100nF
7
1 2
VCC3V3
VCC3V3
R15
100K
R14
100K
C15
SW4
C14
SW3
47nF
TP 33
47nF
TP 33
VCC3V3
JP2
jumper_NO
R5
100k
C11
SW2
C10
SW1
47nF
TP 33
47nF
TP 33
74LV125D
EN
U9
124
1
2
VALBP
VALBP VALBP
R4
100K
R3
100K
D30
ORANGE LED
D29
ORANGE LED
C18
100nF
C22
100nF
TXD0PA6
R76
100R
D32
jumper_NO
RS232onIOB
1
GREEN LED
D31
GREEN LED
R17
VCC3V3
VCC3V3
100K
R74
100R
R75
VAL_RS232
VCC3V3
2
100R
JP3
VALID
R73
100R
PA9 TXD1
PA7 RXD0
PA7
PA[6..7]
PA[6..7]
PA10 RXD1
PA[9..10]
PA[9..10]
R16
100k
PA0
PA0
6-6 AT91EB42 Evaluation Board User Guide
Figure 6-6. AT91M42800
Appendix B – Schematics
VCC3V3
CB16
R48
12
NWAIT CTL3
R46
VT
PA[0..29]
100K
100K
C43
1 2
XOUT
PA26
PLLRCA
PLLRCB
PA27
PA28
JTAG[0..4]
PA29
JTAG[0..4]
1 2
C46
100nF 10%
100R 1%
1 2
C29
VDDIO
100nF
109
110
111
112
113
114
115
116
117
118
119
VDDIO
120
121
122
123
124
125
126
127
128
129
130
131
VDDIO
132
133
134
135
136
137
138
139
140
141
142
143
144
VDDIO
C30
R19
1K50 1%
PLL filter A
1 2
1 2
R18
C45
10nF 10%
PLLRCA
Guard ring
PA23
PA24
PA25
VDDCORE
106
104
105
108
107
VDDIO
VDDCORE
PA25 / MCKO
GND
GND
PA26
GND
XIN
XOUT
GND
PLLRCA
VDDPLL
PLLRCB
VDDPLL
VDDIO
GND
NWDOVF
PA27 / BMS
JTAGSEL
TMS
TDI
TDO
TCK
NTRST
NRST
PA28 / HOLDA
VDDIO
GND
PA29 / HOLD
NWAIT
NOE / NRD
NWE / NWR0
NUB / NWR1
NCS0
NCS1
PB0 / NCS2
PB1 / NCS3
VDDCORE
VDDIO
100nF
PA23 / NPCSB2
PA24 / NPCSB3
GND1GND
NLB / A03A14A25A36A47A58A69A710A811A914A1015A1116A1217A1318A1419A1520A1621A1722A1823A1926PB2 / A20 / CS7
2
PA22
PA21
PA19
PA20
103
102
99
100
101
PA19 / MISOB
PA20 / MOSIB
PA22 / NPCSB1
PA21 / NPCSB0 / NSSB
Y1
32,768kHz
12
C44
1 2
XIN
Guard ring
100nF
C28
VT
XIN
XOUT
VDDPLL
NWDOVF
JTAGSEL
JTAG2
JTAG1
JTAG4
JTAG3
JTAG0
CTL5 D14
CTL3
CTL2
CTL0
CTL1
CTL4
CTL6
CTL[0..6]
PB0
PB1
PB[0..23]
VDDCORE
1 2
120R 1%
1 2
R21
680R 1%
PLL filter B
1 2
1 2
R20
C47
PLLRCB
PA18
PA17
PA16
VDDIO
94
95
98
97
96
GND
VDDIO
PA18 / SPCKB
PA16 / NPCSA2
PA17 / NPCSA3
U11
AT91M42800
VDDIO12GND
13
VDDIO
1µF 10%
C48
100nF 10%
PA9
PA12
PA15
PA13
PA8
PA11
PA14
PA10
88
89
93
90
91
92
87
PA10 / RXD1
PA11 / SPCKA
PA12 / MISOA
PA13 / MOSIA
PA15 / NPCSA1
PA9 / TXD1 / NTRI
PA14 / NPCSA0 / NSSA
JTAGSEL
JTAGSEL
PA7
VDDIO
86
85
84
GND
PA7 / RXD0
PA8 / SCK1
GND
VDDIO
25
24
VDDIO
NRST
NWDOVF
CTL5
NWDOVF
PA5
PA6
82
83
VDDIO
PA6 / TXD0
PA5 / SCK0
PB3 / A21 / CS6
27
28
PB3
PB2
IOB_[0..29]
PA[0..29]
PA1
PA4
PA0
PA3
PA2
77
78
79
80
81
PA0 / IRQ0
PA1 / IRQ1
PA2 / IRQ2
PA3 / IRQ3
PA4 / FIQ
PB4 / A22 / CS5
PB5 / A23 / CS4
29
30D031D132D233D334
PB4
PB5
D0
D2
D1
IOB_[30..53]
PB[0..23]
PB22
PB23
75
76
74
GND73GND
PB22 / TIOA5
PB23 / TIOB5
VDDIO
VDDCORE
PB21 / TCLK5
PB20 / TIOB4
PB19 / TIOA4
PB18 / TCLK4
PB17 / TIOB3
PB16 / TIOA3
PB15 / TCLK3
PB14 / TIOB2
PB13 / TIOA2
GND
VDDIO
PB12 / TCLK2
PB11 / TIOB1
PB10 / TIOA1
PB9 / TCLK1
PB8 / TIOB0
PB7 / TIOA0
PB6 / TCLK0
D15
D14
D13
GND
VDDIO
D12
D11
D10
D9
D8
D7
D6
D5
D4
GND
GND
VDDCORE35VDDIO
36
D3
IOB_[0..53]
C51
100nF
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
C49
100nF
VDDCORE
C50
VDDIO
VDDIO
VDDCORE
PB21
PB20
PB19
PB18
PB17
PB16
PB15
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
100nF
VDDCORE
VDDIO
D15
VDDIO
PB[0..23]
D13
D12
D11
D10
D9
D7
D6
D5
D4
BMS PA27
R41
CB12
100K
1 2
VCC3V3 VCC3V3
Default
boot Mode :
16 Bits
A0
A2
A1
A[0..19]
A5
A7
A6
A4
A8
A3
A9
A10D8A12
A11
A15
A13
A16
A14
A19
A17
A18
D[0..15]
A[0..19]
CTL[0..6]
PB[0..23]
EBI_[0..15]
EBI_[16..35]
EBI_[36..42]
EBI_[0..42]
AT91EB42 Evaluation Board User Guide 6-7
Appendix B – Schematics
Figure 6-7. Reset and JTAG Interface
D11
Red LED
3V3 SUPPLY
VCC3V3
R24
100R
VCC3V3
U12
5
SC11D
432
C73
G5
D10
Red LED
R23
100R
RSTLEDRSTLEDRSTLED
6
9
8
74LVC74AD
R
1
101112
13
4
U6B
1
5
6
VCC3V3
14
7
R78
100K
S1
B.P.
CLEAR
74LVC02AD
RESET
R25
VCC3V3
100nF
100nF
C52
C53
U13
VCC3V3
RST LED
100k
4
1
VCC
GND
NRST
CTL5
3
MR
RST
MAX6315US30D4-T
2
PBRST CTL6
SW5
TP 33
VCC3V3
3
IEEE
CB20
2
JTAGSEL
JTAGSEL
1
ICE
VCC3V3VCC3V3
C94
C71
P5
R27
100nF
U14
C75
10nF
G6
C72
G1
G2
G1
10nF
VCC2GND4GND6GND8GND10GND12GND14GND16GND18GND
10nF
10nF
G3
C77
10nF
G7
G2
G4
C74
G5
G8G7
10nF
G3
G6
JTAG
VCC1NTRST3TDI5TMS7TCK9TCK11TDO13NRST15NC17NC
100k
4
1
VCC
GND
JTAG0
JTAG1
JTAG2
3
MR
RST
MAX6315US30D4-T
2
JTAG3
NRST
JTAG4
C83
C76
G8
10nF
10nF
G9
20
19
JTAG0 JTAG1 JTAG2 JTAG3
C86
G9
C82
G4
HE10 2x10
C81
10pF
C80
10pF
C79
10pF
C78
10pF
10nF
10nF
JTAG4 NRST
C85
C84
10pF
10pF
NWDOVF
NRST
RESET
JTAG[0..4]
6-8 AT91EB42 Evaluation Board User Guide
Figure 6-8. Power Supply and Battery Charger
Appendix B – Schematics
VCC3V3
L1
C54
U15
LT1507CS8-3.3
1
1N914
D12
Vps
100nF
3
BOOST
2
VIN_1VIN
D24
VIN1F
F1
VINplug1
2
10 H
VSW
VIN
SHTDN
4
10MQ100N
D17
D16
1000m A/30V
C55
VDDPLL
I Vddio
JP5
jumper_NO
D15
7
VC
SENSE
GND
SYNC
5
C57
10 F / 25V
10 F / 25V
C57B
D19
10MQ100N
D18
10MQ100N
D14
22pF / 25V
J1
1
+
C58
100 F / 10V
+
C58B
100 F / 10V
1N5817
8
6
10MQ100N
10MQ100N
SMT6T15CA
VINplug2
Jack Dia.2.1mm
C60
3,3nF / 10%
JP6
C59
22pF / 25V
1 2
VDDIO
jumper_NO
C98
VIN
Q1
MJD45H11
10nF
8
V-1R2V+3NC
U22
R77
6R8
150R
C99
R30
10 F / 25V
Vbatt+
U16
14
C100
NC5NC6NC7NC
4
D26
10MQ100N
D25
10MQ100N
Vbatt+
2
MAX 713CSE
Batt+
DRV
V+
15
V+
1F
12
LM334SM
TP2
Test Point Corner 2
TP1
Test Point Corner 1
123
J3
5 cel. NiCd
Timeout 264mn
10
PGM29PGM3
Vlimit
FASTCHG
REF
8
1
16
R59
Rth1
D28
Red LED
R29
100R
VCC3V3
TP3
Test Point Corner 3
TP4
Test Point Corner 4
in place only if
con. male
43045-0400+43031-0007
MOLEX
4
Vbatt-
V+
Vbatt-
CB23
CB22
CB21
1 2
1 2
1 2
4
12
Batt-
PGM03PGM1
GND
CC
THI5TLO
Temp
6
7
4k7
CB19
1 2
PB18
Rth2
R58
C102
R60
1 2
C101
Therm sensor on
Batt. is not use.
Rth2
10K
R79
Rth1
R62a
10R
R62b
10R
R62c
10R
R62d
10R
13
C103
10nF
11
10K
10nF
Vbatt-
10K CTN
TC
1F
VDDCORE
JP8
jumper_3P
3
VDDCORE=3.3V
VDDIO
2R5 / 1W
I Vddcore
2
1
VDDCORE=1.8V
VCC1V8
C64
C63
+
C62
1F
6
1
8
C2-
C2+
Vout
Vin
C1+3C1-
U17
4
2
C61
1F
VCC3V3
1F
10 F / 16V
7
GND
SHDN/SS
5
LT1503CS8-1.8
AT91EB42 Evaluation Board User Guide 6-9
Appendix B – Schematics
Figure 6-9. Battery Type and Connection
J2
43025-0400+43030-0007
con. fem.
MOLEX
Wire: gauge 20 AWG
1
2
3
4
Wire: gauge 20 AWG
1 2
BT1
6V / 300mAH
R61
T˚C
10K CTN SIEMENS B57861S103F40
SAFT : VRE 1/2 AA
Ref 139 663
Tmax 45˚C
Battery : 6V / 300mAH NiCd
6-10 AT91EB42 Evaluation Board User Guide
Figure 6-10. SPI Memories, I2C Memories and SPI ADC
C65
100nF
CS13NC4NC5NC6NC9NC10NC11NC
14SI15SO16
NPCSA0
MOSIA
MISOA
SPCKA
1 2
CB15
R40
100k
8
NC17NC18NC19NC20NC21NC22NC23NC24NC25NC26NC27NC28NC29NC30NC31NC
GND
12
Data Flash Memory
AT45DB321-TC
VCC3V3
VCC3V3
VCC3V3
R32
R34
U18
100k
100k
VCC3V3
32
7
VCC
RDY/BUSY1WP3RESET2SCK
NRST
VCC3V3
R53
R52
R66
100k
100K
100K
8
U21
1
NPCSA1_1
CB17
1 2
C70
VCC3V3
3
7
VCC
HOLD
CS
MOSIA
MISOA
NPCSA1
100nF
4
WP
GND
SO2SI5SCK
AT25256W-10SC-2.7
6
SPCKA
Appendix B – Schematics
Serial EEPROM memory on SPIA
VCC3V3VCC3V3
VCC3V3
U19
R31
R51
NRST
20
VCC
1
100k
100K
18
19
WP
A12A0
MISOA
MOSIA
SPCKA
NPCSA0
100nF
C67
NC13NC14NC15NC16NC17NC
NC3NC4NC5NC6NC7NC8NC
9
CB13
1 2
SDA
10
GND
SCL12SDA
AT24C512W1-10SC-2.7
11
SCL1SCL
SDA1
CB14
1 2
SPCKA
MOSIA
MISOA
RD/WR
14
13
15
16
12
Din
Dout
SCLK
DGND
RD / WR
AGND
CONVST1BUSY2OTI3CS
R63
VCC3V3
100k
R64
VCC3V3
U20
100k
CB2
1 2
Serial EEPROM memory on PIO
4
NPCSA2_1
NCONVST
BUSY
CB4
CB3
1 2
5
R65
VCC3V3
1 2
C90
+
C104
100k
12
CB612CB8
VCC3V3
100nF
VIN4
10µF / 16V
10
11
VDD
REFin6Vin17Vin2
8
VIN1
12
12
CB5
VIN3VIN2
Vin39Vin4
AD7817ARU
A/D converter on SPIA
10pF
C6
CB7
1K50 1%
R68
750R / 1%
R67
Vbatt+
Vps
10pF
C7
4K30 / 1%
R70
750R / 1%
R69
74LVC02AD
U6C
100k
R71
VCC3V3
8
CB18
NPB20
10
1
9
PB20_1
1 2
RD/WR
13
74LVC02AD
1
U6D
11
12
NPB20
NPCSA2_1
14
7
VCC3V3
100nF
C89
PB17
PB16
PB19
IRQ3
NPCSA2
VIN[1..4]
PB20
AT91EB42 Evaluation Board User Guide 6-11
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