ATMEL AT90USB646, AT90USB647, AT90USB1286, AT90USB1287 User Manual

Features

• High Performance, Low Power AVR

• Advanced RISC Architecture

– 135 Powerful Instructions – Most Single Clock Cycle Execu tion – 32 x 8 General Purpose Working Registers – Fully Static Operation – Up to 16 MIPS Throughput at 16 MHz – On-Chip 2-cycle Multiplier

• Non-volatile Program and Data Memories

– 64/128K Bytes of In-System Self-Programmable Flash

• Endurance: 100,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• In-System Programming by On-chip Boot Program hardware activated after reset

• True Read-While-Write Operation

– 2K/4K (64K/128K Flash version) Bytes EEPROM

• Endurance: 100,000 Write/Erase Cycles

– 4K/8K (64K/128K Flash version) Bytes Internal SRAM – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Extensive On-chip Debug Support – Programming of Flash, EEPROM, Fuses, and Lock Bits through th e JTAG I nterface

• USB 2.0 Full-speed/Low-speed Device and On-The-Go Module

– Complies fully with: – Universal Serial Bus Specification REV 2.0 – On-The-Go Supplement to the USB 2.0 Specification Rev 1.0 – Supports data transfer rates up to 12 Mbit/s and 1.5 Mbit/s

• USB Full-speed/Low Speed Device Module with Interrupt on Transfer Completion

– Endpoint 0 for Control Transfers : up to 64-bytes – 6 Programmable Endpoints with IN or Out Directions and with Bulk, Interrupt or

Isochronous Transfers – Configurable Endpoints size up to 256 bytes in double bank mode – Fully independant 832 bytes USB DPRAM for endpoint memory allocation – Suspend/Resume Interrupts – Power-on Reset and USB Bus Reset – 48 MHz PLL for Full-speed Bus Operation – USB Bus Disconnection on Microcontroll e r Request

• USB OTG:

– Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)

for OTG dual-role devices – Provide Status and control signals for software implementation of HNP and SRP – Provides programmable times required for HNP and SRP

• Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode – Two16-bit Timer/Counter with Separate Prescaler, Compare- and Capture Mode – Real Time Counter with Separate Oscillator – Two 8-bit PWM Channels

8-Bit Microcontroller

8-bit Microcontroller with 64/128K Bytes of ISP Flash and USB Controller

AT90USB646 AT90USB647 AT90USB1286 AT90USB1287

Preliminary

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– Six PWM Channels with Programmable Resolution from 2 to 16 Bits – Output Compare Modulator – 8-channels, 10-bit ADC – Programmable Serial USART – Master/Slave SPI Serial Interface – Byte Oriented 2-wire Serial Interface – Programmable Watchdog Timer with Separate On-chip Oscillator – On-chip Analog Comparator – Interrupt and Wake-up on Pin Change

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated Oscillator – External and Internal Interrupt Sources – Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and Extended Standby

• I/O and Packages

– 48 Programmable I/O Lines – 64-lead TQFP and 64-lead QFN

• Operating Voltages

– 2.7 - 5.5V – 2.2 - 5.5V (Check availabilty)

• Operating temperature

– Industrial (-40°C to +85°C)

• Maximum Frequency

– 8 MHz at 2.7V - Industrial range – 16 MHz at 4.5V - Industrial range

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1. Pin Configurations

(

)

Figure 1-1. Pinout AT90USB64/128-TQFP

AT90USB64/128

(INT.6/AIN.0) PE6

(INT.7/AIN.1/UVcon) PE7

UVcc

UGnd UCap

VBus

(IUID) PE3

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6

D+

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

1 2 3 4

D-

5 6 7 8

9 10 11 12 13 14 15 16

INDEX CORNER

PF5 (ADC5/TMS

PF3 (ADC3)

PF4 (ADC4/TCK

AVR USB

TQFP64

PF6 (ADC6/TDO

PF7 (ADC7/TDI)

GND

VCC

PA0 (AD0)

PA1 (AD1)

PA2 (AD2)

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PE2 (ALE/HWB) PC7 (A15/IC.3/CLK0 PC6 (A14/OC.3A) PC5 (A13/OC.3B) PC4 (A12/OC.3C) PC3 (A11/T.3) PC2 (A10) PC1 (A9) PC0 (A8) PE1 (RD) PE0 (WR)

VCC

GND

XTAL2

RESET

(INT4/TOSC1) PE4

(INT.5/TOSC2) PE5

PCINT7/OC.0A/OC.1C) PB7

XTAL1

(RXD1/INT2) PD2

(OC0B/SCL/INT0) PD0

(OC2B/SDA/INT1) PD1

(T1) PD6

(ICP1) PD4

(XCK1) PD5

(TXD1/INT3) PD3

(T0) PD7

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Figure 1-2. Pinout AT90USB64/128-QFN

)

(

)

(INT.6/AIN.0) PE6

(INT.7/AIN.1/UVcon) PE7

UVcc

UGnd UCap

VBus

(IUID) PE3

(SS/PCINT0) PB0

(PCINT1/SCLK) PB1

(PDI/PCINT2/MOSI) PB2

PDO/PCINT3/MISO) PB3

(PCINT4/OC.2A) PB4 (PCINT5/OC.1A) PB5 (PCINT6/OC.1B) PB6

AVCC

GND

AREF

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

6463625361

1 2

D-

D+

5 6 7 8

9 10 11 12 13 14 15 16 33

(64-lead QFN top view)

182019

INDEX CORNER

AT90USB128

21222324252627

VCC

GND

RESET

PF5 (ADC5/TMS

PF3 (ADC3)

PF4 (ADC4/TCK

XTAL2

XTAL1

PF6 (ADC6/TDO

PF7 (ADC7/TDI)

GND

VCC

525150

(ICP1) PD4

PA0 (AD0)

(XCK1) PD5

PA1 (AD1)

PA2 (AD2)

(T1) PD6

(T0) PD7

PA3 (AD3)

PA4 (AD4)

PA5 (AD5)

PA6 (AD6)

PA7 (AD7)

PE2 (ALE/HWB)

PC7 (A15/IC.3/CLK0

PC6 (A14/OC.3A)

PC5 (A13/OC.3B)

PC4 (A12/OC.3C)

PC3 (A11/T.3)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PE1 (RD) PE0 (WR)

(TXD1/INT3) PD3

(INT4/TOSC1) PE4

(INT.5/TOSC2) PE5

PCINT7/OC.0A/OC.1C) PB7

Note: The large center pad underneath the MLF packages is made of metal and internally connected to

(RXD1/INT2) PD2

(OC0B/SCL/INT0) PD0

(OC2B/SDA/INT1) PD1

GND. It should be soldered or glued to the board to ensure good mechanical stability . If the center pad is left unconnected, the package might loosen from the board.

1.1 Disclaimer

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

2. Overview

The AT90USB64/128 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the

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AT90USB64/128 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

AT90USB64/128

AVCC

AGND AREF

VCC

GND

DATAREGISTER

JTAG T AP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF

PORTF DRIVERS

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

CONTROL

LINES

DATADIR.

REG. PORTF

DATAREGISTER

POR - BOD

RESET

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

ALU

STATUS

PORTA

PA7 - PA0PF7 - PF0

PORTA DRIVERS

REG. PORTA

DATADIR.

INTERNAL

OSCILLATOR

WATCHDOG

MCU CONTROL

COUNTERS

INTERRUPT

8-BIT DATA BUS

TIMER

TIMER/

UNIT

EEPROM

PORTC DRIVERS

DATAREGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC7 - PC0

PLL

DATADIR.

REG. PORTC

XTAL1

XTAL2

RESET

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ANALOG

COMPARATOR

DATAREGISTER

PORTE

REG. PORTE

PORTE DRIVERS

DATADIR.

DATAREGISTER

PORTB

REG. PORTB

PORTB DRIVERS

PB7 - PB0PE7 - PE0

DATADIR.

SPIUSART0

DATAREGISTER

PORTD

PORTD DRIVERS

USB

REG. PORTD

PD7 - PD0

DATADIR.

TWO-WIRE SERIAL

INTERFACE

DATAREG.

PORTG

PORTG DRIVERS

PG4 - PG0

DATADIR.

REG. PORTG

The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90USB64/128 provides the following features: 64/128K bytes of In-System Programmable Flash with Read-While-Write capabilities, 2K/4K bytes EEPROM, 4K/8K bytes SRAM, 48 general purpose I/O lines, 32 general purpose working registers, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, one USART, a byte oriented 2-wire Serial Interface, a 8-channels, 10-bit ADC with optional differential input stage with programmable gain, programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std.

1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and six software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching no ise during ADC co nversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel AT90USB64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90USB64/128 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Pin Descriptions

2.2.1 VCC

Digital supply voltage.

2.2.2 GND

Ground.

2.2.3 Port A (PA7..PA0)

Port A is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port A also serves the functions of various special features of the AT90USB64/128 as listed on

page 81.

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2.2.4 Port B (PB7..PB0)

Port B is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port B has better driving capabilities than the other ports. Port B also serves the functions of various special features of the AT90USB64/128 as listed on

page 82.

2.2.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port C also serves the functions of special features of the AT90USB64/128 as listed on page 85.

2.2.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pins are tri-stated when a reset condition becomes active, even if the clock is not running.

AT90USB64/128

Port D also serves the functions of v arious special features of the AT90USB64/128 as listed on

page 86.

2.2.7 Port E (PE7..PE0)

Port E is an 8-bit bi-directional I/O port wit h intern al pull-up r esistors ( selecte d for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated when a reset co ndition becomes active, even if the clock is not running.

Port E also serves the functions of various special features of the AT90USB64/128 as listed on

page 89.

2.2.8 Port F (PF7..PF0)

Port F serves as analog inputs to the A/D Converter. Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins

can provide internal pull-up resistors (selected for each bit). The Port F output buffe rs have symmetrical drive characteristics with both high sink and source capability. As inputs, Port F pins that are externally pulled low will source current if the pull-up resistors are activated. The Port F pins are tri-stated when a res et cond ition b ecomes a ctive, ev en if th e clock is not ru nning. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

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Port F also serves the functions of the JTAG interface.

2.2.9 D-

2.2.10 D+

2.2.11 UGND

2.2.12 UVCC

2.2.13 UCAP

2.2.14 VBUS

USB Full speed / Low Speed Negative Data Upstream Port. Should be connected to the USB Dconnector pin with a serial 22 Ohms resistor.

USB Full speed / Low Speed Positive Data Upstream Port. Should be connected to the USB D+ connector pin with a serial 22 Ohms resistor.

USB Pads Ground.

USB Pads Internal Regulator Input supply voltage.

USB Pads Internal Regulator Output supply voltage. Should be connected to an external capacitor (1µF).

USB VBUS monitor and OTG negociations.

2.2.15

2.2.16 XTAL1

2.2.17 XTAL2

2.2.18 AVCC

2.2.19 AREF

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. The minimum pulse length is given in Table 8-1 on page

60. Shorter pulses are not guaranteed to generate a reset.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for Port F and the A/D Converter. It should be externally connected to V through a low-pass filter.

This is the analog reference pin for the A/D Converter.

3. About Code Examples

This documentation contains simple code examples that briefly sh ow how to use vari ous parts of the device. Be aware that not all C compiler vendors include bit def initions in the header files and interrupt handling in C is compiler dependent. Plea se con firm with th e C com piler d ocumentation for more details.

, even if the ADC is not used. If the ADC is used, it should be connected to V

These code examples assume that the part spe cific header file is included before compilation. For I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBI C", "CBI", and "SBI"

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7593D–AVR–07/06

AT90USB64/128

instructions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

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4. AVR CPU Core

4.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

4.2 Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Program

Counter

Control Lines

Direct Addressing

Indirect Addressing

Status

and Control

32 x 8 General Purpose

Registrers

ALU

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buses for program and data. Instructions in the program memory are executed with a single level pipe lining. While one instruc tion is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

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AT90USB64/128

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer fo r look up tables in Flash pr ogram memory. Thes e added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whole address space. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program section and the Application Program section. Both sections have dedicated Lock bits for write and read/write protection. The SPM instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector position. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be acces sed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90USB64/128 has Extended I/O space from 0x60 - 0x0FF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

4.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. The ALU opera tions are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. See the “Instruction Set” section for a detailed description.

7593D–AVR–07/06

4.4 Status Register

The Status Register contains information about the result of the most recently executed arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in man y case s re move th e need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. This must be ha nd le d by software.

The AVR Status Register – SREG – is defined as:

Bit 76543210

I THSVNZCSREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual interrupt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry Is useful in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

4.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output opera nd and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10 Registers R17 0x11

AT90USB64/128

70Addr. R0 0x00

R1 0x01 R2 0x02 … R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have some a dded functions to their general purpose usage. These registers are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and Z are defined as described in Figure 4-3.

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4.6 Stack Pointer

Figure 4-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed d isplacem ent, automatic increment, and automatic decrement (see the instruction set reference fo r details).

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. The Stack Pointer Register always points to the top of the Stack. Note that the Stack is implemented as growing from higher memor y locations to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt Stacks are located. This Stack space in the data SRAM must be defined by the program before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to point above 0x0100. The initial value of the stack pointer is the last address of the internal SRAM. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by three when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack with the POP instruction, and it is incremented by three when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 1514131211109 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 1 0 0 0 0 0

11111111

AT90USB64/128

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4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ

Bit 7654321 0

RAMPZ7RAMPZ6RAMPZ5RAMPZ4RAMPZ3RAMPZ2RAMPZ1 RAMPZ0 RAMPZ

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

For ELPM/SPM instructions, the Z-point er is a concatenation of RAMPZ, ZH, and ZL, as shown in Figure 4-4. Note that LPM is not affected by the RAMPZ setting.

Figure 4-4. The Z-pointer used by ELPM and SPM

AT90USB64/128

Bit ( Individually)

Bit (Z-pointer) 23 16 15 8 7 0

707070

RAMPZ ZH ZL

The actual number of bits is implementation dependent. Unused bits in an implementation will always read as zero. For compatibility with future devices, be sure to write these bits to zero.

4.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast- access Register File concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.

Figure 4-5. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

, directly generated from the selected clock source for the

CPU

T1 T2 T3 T4

Figure 4-6 shows the internal timing concept for the Register File. In a single clock cycl e an ALU

operation using two register operands is executed, and the result is stored back to the destination register.

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Figure 4-6. Single Cycle ALU Operation

Total Execution Time

egister Operands Fetch

ALU Operation Execute

Result Write Back

4.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be written logic one together with th e Global Interrupt Enable bit in the Status Register in order to enable the interrupt. Depending on the Program Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 368 for details.

The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 70. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 70 for more information. The Reset Vector can also be moved to the start of the Boot Flash section by programming the BOOTRST Fuse, see “Memory Programming” on page 368.

clk

T1 T2 T3 T4

CPU

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessarily have Interrupt Flags. If the interrupt condition disap pears befo re the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

AT90USB64/128

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AT90USB64/128

Note that the Status Register is not automatically stored when entering an interrupt routine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence..

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMPE ; start EEPROM write

sbi EECR, EEPE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

__disable_interrupt();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

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Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

__enable_interrupt(); /* set Global Interrupt Enable */

__sleep(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1 Interrupt Response Time

The interrupt execution response for all the enabl ed AVR interrupts is five clock cycles minimum. After five clock cycles the program vector address for the actual interrupt handling ro utine is executed. During these five clock cycle period, the Program Counter is pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by five clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incremented by three, and the I-bit in SREG is set.

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5. AVR AT90USB64/128 Memories

This section describes the different memories in the AT90USB64/128. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90USB64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

Table 5-1. Memory Mapping.

Memory Mnemonic AT90USB64 AT90USB128

Size

Flash

32 Registers

I/O Registers

Ext I/O Registers

Internal SRAM

External Memory

EEPROM

Start Address

End Address

Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address

AT90USB64/128

Flash size 64 K bytes 128K bytes

- 0x00000

Flash end

0x0FFFF

0x7FFF

- 32 bytes

- 0x0000

- 0x001F

- 64 bytes

- 0x0020

- 0x005F

- 160 bytes

- 0x0060

- 0x00FF ISRAM size 4 K bytes 8 K bytes ISRAM start 0x0100

ISRAM end 0x10FF 0x20FF

XMem size 0-64 K bytes

XMem start 0x1100 0x2100

XMem end 0xFFFF

E2 size 2 K bytes 4K bytes

- 0x0000

E2 end 0x07FF 0x0FFF

(1)

(2)

0x1FFFF

0xFFFF

(1)

(2)

Notes: 1. Byte address.

2. Word (16-bit) address.

5.1 In-System Reprogrammable Flash Program Memory

The AT90USB64/128 contains 128K bytes On-chip In-System Reprogrammable Flash memory for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 64K x 16. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 100,000 write/erase cycles. The AT90USB64/128 Program Counter (PC) is 16 bits wide, thus addressing the 128K program

7593D–AVR–07/06

memory locations. The operation of Boot Program section and associated Boot Lock bits for

software protection are described in detail in “Memory Programming” on page 368. “Memory

Programming” on page 368 contains a detailed description on Flash data serial downloading

using the SPI pins or the JTAG interface. Constant tables can be allocated within the entire program memory address space (see the LPM

– Load Program Memory instruction description and ELPM - Ex tended Load Program Me mory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 15.

Figure 5-1. Program Memory Map

Program Memory

0x00000

Application Flash Section

5.2 SRAM Data Memory

Figure 5-2 shows how the AT90USB64/128 SRAM Memory is organized.

The AT90USB64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instruction s. For the Extended I/O space from $060 - $1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The first 4,608/8,704 Data Memory locations address both the Register File, the I/O Memory, Extended I/O Memory, and the internal data SRAM. The first 32 locations address the Register file, the next 64 location the standard I/O Memory, then 416 locations of Extended I/O memory and the next 8,192 locations address the internal data SRAM.

AT90USB64/128

Boot Flash Section

Flash En

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AT90USB64/128

An optional external data SRAM can be used with the AT90USB64/128. This SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest 4,608/8,704 bytes, so when using 64KB (65,536 bytes) of External Memo ry, 60,478/56,832 Bytes of External Memory are available. See “External Memory Interface” on

page 30 for details on how to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory locations, the external data SRAM is accessed using the same instructions as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PE0 enabled by setting the SRE bit in the XMCRA Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cycles extra because the three-byte program counter is pushed and popped, and external memory access does not take advantage of the internal pipeline memory access. When external SRAM in terface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.

and PE1) are inactive during the whole access cycle. External SRAM operation is

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Indirect with Pre-decrement, and In direct with Post-incremen t. In the Register file, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base addres s given

by the Y- or Z-register. When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented. The 32 general purpose working registers, 64 I/O registers, and the 8,192 bytes of internal data

SRAM in the AT90USB64/128 are all accessible through all these addressing modes. The Register File is described in “General Purpose Register File” on page 13.

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Figure 5-2. Data Memory Map

ata

emory

32 R

egister

I/O

egister

160

Ext I/O

nterna

SRA

(

8192

x 8)

xternal

(0 - 64K x 8)

SRA

Reg.

$0000 - $001 $0020 - $005 $0060 - $00

ISRAM start

ISRAM end XMem start

F F

5.2.1 Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

FFFF

cycles as described in Figure 5-3.

CPU

AT90USB64/128

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Figure 5-3. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

ddress

Compute Address

Address valid

Data

AT90USB64/128

5.3 EEPROM Data Memory

The AT90USB64/128 contains 2K/4K bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

page 382, page 387, and page 371 respectively.

5.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

Data

Memory Access Instruction

Write

Read

Next Instruction

The write access time for the EEPROM is given in Table 5-3. A self-timing function, however, lets the user software detect when the next byte can be written. If the user code contains instructions that write the EEPROM, some precautions must be taken. In heavily filtered power supplies, V

is likely to rise or fall slowly on power-up/down. This causes the device for some

period of time to run at a voltage lower than specif ied as m inimu m for the clock fre que ncy us ed.

See “Preventing EEPROM Corruption” on page 28. for details on how to avoid problems in these

situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this. When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next instruction is executed.

5.3.2 The EEPROM Address Register – EEARH and EEARL

Bit 1514131211 10 9 8

––––EEAR11EEAR10EEAR9EEAR8EEARH EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

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76543 2 10

Read/Write R R R R R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value0000X XXX

XXXXX X XX

• Bits 15..12 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 11..0 – EEAR8..0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 4096. The initial value of EEAR is undefined. A proper value must be written before the EEPROM may be accessed.

5.3.3 The EEPROM Data Register – EEDR

Bit 76543210

MSB LSB EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to b e written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

5.3.4 The EEPROM Control Register – EECR

Bit 765432 10

– – EEPM1 EEPM0 EERIE EEMPE EEPE EERE EECR

Read/Write R R R/W R/W R/W R/W R/W R/W Initial Value 0 0 X X 0 0 X 0

• Bits 7..6 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and will always read as zero.

• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEPE. It is possible to program data in one atomic operation (erase the old value and program the new value) or to split the Erase and Write operations in two different operations. The Programming times for th e differen t modes are shown in Table 5- 2. While EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00 unless the EEPROM is busy programming.

AT90USB64/128

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AT90USB64/128

Table 5-2. EEPROM Mode Bits

Programming

EEPM1 EEPM0

0 0 3.4 ms Erase and Write in one operation (Atomic Operation) 0 1 1.8 ms Erase Only 1 0 1.8 ms Write Only 1 1 – Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrupt. The EEPROM Ready interrupt generates a constant interrupt when EEPE is cleared.

• Bit 2 – EEMPE: EEPROM Master Programming Enable

The EEMPE bit determines whether setting EEPE to one causes the EEPROM to be written. When EEMPE is set, setting EEPE within four clock cycles will write data to the EEPROM at the selected address If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been written to one by software, hardware clears the bit to zero after four clock cycles. See the description of the EEPE bit for an EEPROM write procedure.

Time Operation

• Bit 1 – EEPE: EEPROM Programming Enable

The EEPROM Write Enable Signal EEPE is the write strobe to the EEPROM. When address and data are correctly set up, the EEPE bit must be written to one to write the value into the EEPROM. The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no EEPROM write takes place. The following procedure should be followed when writing the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEPE becomes zero.

2. Wait until SELFPRGEN in SPMCSR becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMPE bit while writing a zero to EEPE in EECR.

6. Within four clock cycles after setting EEMPE, write a logical one to EEPE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Me mory Pr o-

gramming” on page 368 for details about Boot programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

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When the write access time has elapsed, the EEPE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEPE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR Register, the EERE bit must be written to a log ic one to trig ger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediately. When the EEPROM is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEPE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 5-3 lists the typic al programming time for EEPROM access from the CPU.

Table 5-3. EEPROM Programming Time

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU)

The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of these functions. The examples also assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

26,368 3.3 ms

AT90USB64/128

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AT90USB64/128

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to Data Register

out EEDR,r16

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address and Data Registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

(1)

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Note: 1. See “About Code Examples” on page 8.

The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from Data Register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from Data Register */

return EEDR;

}

(1)

Note: 1. See “About Code Examples” on page 8.

5.3.5 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM to operate properly. These issues a re the same as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situ at ion s wh en the vo lt age is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-ou t Detector (BOD). If the detection level of the internal BOD does not match the needed detection level, an external low V be used. If a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient.

AT90USB64/128

the EEPROM data can be corrupted because the supply voltage is

CC,

reset Protection circuit can

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5.4 I/O Memory

AT90USB64/128

The I/O space definition of the AT90USB64/128 is shown in “Register Summary” on page 414. All AT90USB64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructio ns, transferring data be tween the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set section for more details. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90USB64/128 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 0x1FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

5.4.1 General Purpose I/O Registers

The AT90USB64/128 contains three General Purpose I/O Registers. These registers can be used for storing any inform ation, and th ey are particularly useful for storing global variables and Status Flags. General Purpose I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.

5.4.2 General Purpose I/O Register 2 – GPIOR2

Bit 76543210

MSB LSB GPIOR2

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

5.4.3 General Purpose I/O Register 1 – GPIOR1

Bit 76543210

MSB LSB GPIOR1

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

5.4.4 General Purpose I/O Register 0 – GPIOR0

Bit 76543210

MSB LSB GPIOR0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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5.5 External Memory Interface

With all the features the External Memory Interface provides, it is well suited to operate as an interface to memory devices such as External SRAM and Flash, and peripherals such as LCDdisplay, A/D, and D/A. The main features are:

•

Four different wait-state settings (including no wait-state).

• Independent wait-state setting for different external Memory sectors (configurable sector size).

• The number of bits dedicated to address high byte is selectable.

• Bus keepers on data lines to minimize current consumption (optional).

5.5.1 Overview

When the eXternal MEMory (XMEM) is enabled, address space outside the internal SRAM becomes available using the dedicated External Memory pins (see Figure 2-1 on page 5, Table

10-3 on page 81, and Table 10-9 on page 85). The memory configuration is shown in Figure 5-4.

Figure 5-4. External Memory with Sector Select

emory

nterna

onfiguration

l memor

0x0000

5.5.2 Using the External Memory Interface

The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus.

• A15:8: High-order address bus (configurable number of bits).

• ALE: Address latch enable.

•RD

: Read strobe.

•WR

: Write strobe.

The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

xternal

(0-60K x 8)

emory

owe

SRW SRW

ppe

SRW SRW

r sector

01 00

r sector

11 10

ISRAM end XMem start

SRL[2..0

]

0xFFFF

AT90USB64/128

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When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that corresponds to the po rts dedicated to the XMEM inter face. For details about the port override, see the alternate fun ctions in section “I/O-Ports” on page 74 . The XMEM interface will auto-detect whether an access is internal or external. If the access is external, the XMEM interface will output address, data, and the control signals on the ports according to Fig-

ure 5-6 (this figure shows the wave forms without wait-states). When ALE goes fr om high-to-low,

there is a valid address on AD7:0. ALE is low during a data transfer. When the XMEM interface is enabled, also an internal access will cause activity on address, data and ALE ports, but the RD

and WR strobes will not toggle during internal access. When the External Memory Interface is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 5-5 illustrates how to connect an external SRAM to the AVR using an octal latch (typically “74 x 573” or equivalent) which is transparent when G is high.

5.5.3 Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typic al old sty l e 74HC series latch becomes inadequate. The External Memory Interface is designed in compliance to the 74AHC series latch. However, most latches can be used as long they comply with the main timing par ameters. The m ain paramete rs for the address latch are:

AT90USB64/128

• D to Q propagation delay (t

• Data setup time before G low (t

• Data (address) hold time after G low (

The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of t 7 through Tables 30-13 on pages 408 - 411. The D-to-Q propagation delay (t

= 5 ns. Refer to t

LAXX_LD/tLLAXX_ST

in “External Data Memory Timing” Tables 30-

) must be taken

into consideration when calculating the access time requirement of the external component. The data setup time before G low (t

) must not exceed address valid to ALE low (t

) minus PCB

AVLLC

wiring delay (dependent on the capacitive load).

Figure 5-5. External SRAM Connected to the AVR

D[7:0]

AD7:0

AVR

ALE

A15:8

A[7:0]

SRAM

A[15:8]

7593D–AVR–07/06

5.5.4 Pull-up and Bus-keeper

The pull-ups on the AD7:0 ports may be activated if the corresponding Port register is written to one. To reduce power consumption in sleep mode, it is recommended to disable the pull-ups by writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in software as described in “External Memory Control Register B – XMCRB”

on page 35. When enabled, the bus-keeper will keep the previous value on the AD7:0 bus while

these lines are tri-stated by the XMEM interface.

5.5.5 Timing

External Memory devices have different timing requirements. To meet these requiremen ts, the XMEM interface provides four differ ent wait -states as shown in Table 5-5. It is important to consider the timing specification of the External Memory device before selecting the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement. The access time for the External Memory is defined to be the time from receiving the chip select/address until the data of this address actually is driven on the bus. The access time cannot exceed the time from the ALE pulse must be asserted low until data is stable during a read sequence (See t

411). The different wait-state s are set up in so ftware. As an a dditional featur e, it is possible t o divide the external memory space in two sectors with individual wait-state settings. Thi s makes i t possible to connect two different memory devices with different timing requirements to the same XMEM interface. For XMEM interface timing details, please refer to Tables 30-6 through Tables 30-13 and Figure 30-7 to Figure 30-10 in the “External Data Memory Timing” on page 408.

LLRL

+ t

RLRH

- t

in Tables 30-6 through Tables 30-13 on pages 408 -

DVRH

Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guarantied (varies between devices temperature, and sup ply voltage). Consequently, the XMEM interface is not suited for synchronous operation.

Figure 5-6. External Data Memory Cycles without Wait-state (SRWn1=0 and SRWn0=0)

System Clock (CLK

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

CPU

ALE

A15:8

DA7:0

T1 T2 T3

)

AddressPrev. addr.

Address DataPrev. data XX

DataPrev. data Address

Write

Read

Note: 1. SRWn1 = SR W1 1 (upper sector) or SRW01 (lower sector), SR Wn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

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Figure 5-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1

System Clock (CLK

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

CPU

ALE

A15:8

DA7:0

T1 T2 T3

)

AddressPrev. addr.

Address DataPrev. data XX

DataPrev. data Address

(1)

Write

Read

Note: 1. SRWn1 = SR W1 1 (upper sector) or SRW01 (lower sector), SR Wn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T5 is only present if the next instruction accesses the RAM (internal or external).

Figure 5-8. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 0

System Clock (CLK

CPU

T1 T2 T3

)

(1)

ALE

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

Address DataPrev. data XX

AddressPrev. addr.

Write

DataPrev. data Address

Read

Note: 1. SRWn1 = SR W1 1 (upper sector) or SRW01 (lower sector), SR Wn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T6 is only present if the next instruction accesses the RAM (internal or external).

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Figure 5-9. External Data Memory Cycles with SRWn1 = 1 and SRWn0 = 1

System Clock (CLK

CPU

)

T1 T2 T3

ALE

T4 T5

(1)

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

Note: 1. SRWn1 = SR W1 1 (upper sector) or SRW01 (lower sector), SR Wn0 = SRW10 (upper sector) or

SRW00 (lower sector). The ALE pulse in period T7 is only present if the next instruction accesses the RAM (internal or external).

5.5.6 External Memory Control Register A – XMCRA

Bit 76543210

SRE SRL2 SRL1 SRL0 SRW11 SRW10 SRW01 SRW00 XMCRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value00000000

• Bit 7 – SRE: External SRAM/XMEM Enable

Writing SRE to one enables the External Memory Interface.The pin functions AD7:0, A15:8, ALE, WR

, and RD are activated as the alternate pin functions. The SRE bit overrides any pin direction settings in the respective data direction registers. Writing SRE to zero, disables the External Memory Interface and the normal pin and data direction settings are used.

Address DataPrev. data XX

AddressPrev. addr.

Write

DataPrev. data Address

Read

• Bit 6..4 – SRL2:0: Wait-state Sector Limit

It is possible to configure different wait-states for different External Memory addresses. The external memory address space can be divid ed in t wo secto rs that have sepa rate wait- state bits. The SRL2, SRL1, and SRL0 bits select the split of the sectors, see Table 5-4 and Figure 5-4. By default, the SRL2, SRL1, and SRL0 bits are set to zero and the entire external memory address space is treated as one sector. When the entire SRAM address space is configured as one sector, the wait-states are configured by the SRW11 and SRW10 bits.

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Table 5-4. Sector limits with different settings of SRL2..0

SRL2 SRL1 SRL0 Sector Limits

00x

010

011

Lower sector = N/A Upper sector = 0x2100 - 0xFFFF

Lower sector = 0x2100 - 0x3FFF Upper sector = 0x4000 - 0xFFFF

Lower sector = 0x2100 - 0x5FFF Upper sector = 0x6000 - 0xFFFF

AT90USB64/128

100

101

110

111

Lower sector = 0x2100 - 0x7FFF Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x2100 - 0x9FFF Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x2100 - 0xBFFF Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x2100 - 0xDFFF Upper sector = 0xE000 - 0xFFFF

• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the external memory address space, see Table 5-5.

• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the external memory address space, see Table 5-5.

Table 5-5. Wait States

SRWn1 SRWn0 Wait States

0 0 No wait-states 0 1 Wait one cycle during read/write strobe 1 0 Wait two cycles during read/write strobe

(1)

Wait two cycles during read/write and wait one cycle before driving out new address

Note: 1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see Figures 5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.

5.5.7 External Memory Control Register B – XMCRB

Bit 7654 3 210

XMBK – – – – XMM2 XMM1 XMM0 XMCRB Read/Write R/W R R R R R/W R/W R/W Initial Value0000 0 000

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tristated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,

7593D–AVR–07/06

so even if the XMEM interface is disabled, the bus keepers are still activated as long as XMBK is one.

• Bit 6..3 – Res: Reserved Bits

These bits are reserved and will always read as zero. When writing to this address location, write these bits to zero for compatibility with future devices.

• Bit 2..0 – XMM2, XMM1, XMM0: External Memory High Mask

When the External Memory is enabled, all Port C pins are default used for the high address byte. If the full 60KB address space is not required to access the External Memory, some, or all, Port C pins can be released for normal Port Pin function as described in Table 5-6 . As described in

“Using all 64KB Locations of External Memory” on page 37, it is po ssible to use the XMMn bits to

access all 64KB locations of the External Memory.

Table 5-6. Port C Pins Released as Normal Port Pins when the External Memory is Enabled

XMM2 XMM1 XMM0 # Bits for External Memory Address Released Port Pins

0 0 0 8 (Full 56KB space) None 0017 PC7 0106 PC7 - PC6 0115 PC7 - PC5 1004 PC7 - PC4 1013 PC7 - PC3 1102 PC7 - PC2 1 1 1 No Address high bits Full Port C

5.5.8 Using all Locations of External Memory Smaller than 64 KB

Since the external memory is mapped after the internal memory as shown in Figure 5-4, the external memory is not addressed when addressing the first 8,448/4,352 bytes (128/64Kbytes version) of data space. It may appear that the first 8,448/4,352 b ytes of the e xternal memor y are inaccessible (external memory addresses 0x0000 to 0x10FF or 0x0000 to 0x20FF). However, when connecting an external memory smaller than 64 KB, for example 32 KB, these locations are easily accessed simply by addressing from address 0x8000 to 0xA1FF. Since the External Memory Address bit A15 is not connected to the external memory, addresse s 0x8000 to 0xA1FF will appear as addresses 0x0000 to 0x21FF for the external memory. Addressing above address 0xA1FF is not recommended, since this will address an external memory location that is already accessed by another (lower) address. To the Application software, the external 32 KB memory will appear as one linear 32 KB address space from 0x2200 to 0xA1FF. This is illustrated in Fig-

ure 5-10.

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Figure 5-10. Address Map with 32 KB External Memory

emory

onfiguration

AVR

emory

0x0000

0x20

0x2100

0x7

FFF

0x8000

ISRAM end + 0x8000 XMem start + 0x8000

0xFFFF

nterna

(

xternal

emory

nused

emory

)

xternal

32K SRA

AT90USB64/128

0x0000

ISRAM end XMem start

FFF

5.5.9 Using all 64KB Locations of External Memory

Since the External Memory is mapped after the Internal Memory as shown in Figure 5-4, only 56KB of External Memory is available by default (address space 0x0000 to 0x20FF is reserved for internal memory). However, it is possible to take advantage of the entire Exte rnal Memo ry by masking the higher address bits to zero. This can be done by using the XMMn bits and control by software the most significant bits of the address. By setting Port C to output 0x00, and releasing the most significant bits for normal Port Pin operation, the Memory Interface will address 0x0000 - 0x2FFF. See the following code examples.

Care must be exercised using this option as most of the memory is masked away.

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Assembly Code Example

; OFFSET is defined to 0x4000 to ensure ; external memory access ; Configure Port C (address high byte) to ; output 0x00 when the pins are released ; for normal Port Pin operation

ldi r16, 0xFF out DDRC, r16 ldi r16, 0x00 out PORTC, r16

; release PC7:6

ldi r16, (1<<XMM1) sts XMCRB, r16

; write 0xAA to address 0x0001 of external ; memory

ldi r16, 0xaa sts 0x0001+OFFSET, r16

; re-enable PC7:6 for external memory

ldi r16, (0<<XMM1) sts XMCRB, r16

; store 0x55 to address (OFFSET + 1) of ; external memory

ldi r16, 0x55 sts 0x0001+OFFSET, r16

C Code Example

(1)

#define OFFSET 0x4000

void XRAM_example(void)

{

unsigned char *p = (unsigned char *) (OFFSET + 1);

DDRC = 0xFF;

PORTC = 0x00;

XMCRB = (1<<XMM1);

*p = 0xaa;

XMCRB = 0x00;

*p = 0x55;

}

Note: 1. See “About Code Examples” on page 8.

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6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 53. The clock systems are detailed below.

Figure 6-1. Clock Distribution

USB

Asynchronous Timer/Counter

General I/O

Modules

ADC

AT90USB64/128

CPU Core RAM

clk

ADC

Flash and EEPROM

6.1.1 CPU Clock – clk

CPU

clk

USB PLL

X24

clk

PLL Clock

Prescaler

clk

USB (48MHz)

Pllin (2MHz)

XTAL (2-16 MHz)

Timer/Counter

Oscillator

clk

ASY

Oscillator

I/O

Crystal

AVR Clock

Control Unit

Source clock

System Clock

Prescaler

Clock

Multiplexer

External Clock

clk

CPU

clk

FLASH

Watchdog TimerReset Logic

Watchdog clock

Watchdog

Oscillator

Calibrated RC

Oscillator

The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing general operations and calculations.

6.1.2 I/O Clock – clk

I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and USART. The I/O clock is also used by the External Interrupt module, but note that some external interrupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted. Also note that start condition detection in the USI module is carried out asynchronously when clk

6.1.3 Flash Clock – clk

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simultaneously with the CPU clock.

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FLASH

is halted, TWI address recognition in all sleep modes.

I/O

6.1.4 Asynchronous Timer Clock – clk

The Asynchronous Timer clock allows the Asynchronous Timer/Counter to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.

ASY

6.1.5 ADC Clock – clk

6.1.6 USB Clock – clk

6.2 Clock Sources

ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion results.

USB

The USB is provided with a dedicated clock domain. This clock is generated with an on-chip PLL running at 48MHz. The PLL always multiply its input frequency by 24. Thus the PLL clock register should be programmed by software to generate a 2MHz clock on the PLL input.

The device has the following clock source options, selec table by Flash Fuse bits as shown below. The clock from the selected source is input to the AVR clock generator, and routed to the appropriate modules.

Table 6-1. Device Clocking Options Select

Device Clocking Option CKSEL3..0

Low Power Crystal Oscillator 1111 - 1000 Reserved 0111 - 0110 Low Frequency Crystal Oscillator 0101 - 0100 Internal 128 kHz RC Oscillator 0011

(1)

Calibrated Internal RC Oscillator 0010 External Clock 0000 Reserved 0001

Note: 1. For all fuses “1” means unprogrammed while “0” means programmed.

6.2.1 Default Clock Source

The device is shipped with internal RC oscillator at 8.0MHz and with the fuse CKDIV8 programmed, resulting in 1.0MHz system clock. The startup time is set to maximum and time-out period enabled. (CKSEL = "0010", SUT = "10", CKDIV8 = "0"). The default setting ensures that all users can make their desired clock source setting u sing a ny available prog ramming inter face.

6.2.2 Clock Startup Sequence

Any clock source needs a sufficient V cycles before it can be considered stable.

To ensure sufficient V the device reset is released by all other reset sources. “On-chip Debug System” on page 58 describes the start conditions for the internal reset. The delay (t Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The selectable delays are shown in Table 6-2. The frequency of the Watchdog Oscillator is voltage

to start oscillating and a minimum number of oscillating

, the device issues an internal reset with a time-out delay (t

) is timed from the Watchdog

TOUT

) after

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AT90USB64/128

dependent as shown in “AT90USB64/128 Typical Characteristics – Preliminary Data” on page

429.

Table 6-2. Number of Watchdog Oscillator Cycles

Typ Time-out (VCC = 5.0V) Typ Time-out (VCC = 3.0V) Number of Cycles

0 ms 0 ms 0

4.1 ms 4.3 ms 512 65 ms 69 ms 8K (8,192)

Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The delay will not monitor the actual voltage and it will be required to select a delay longer than the Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is not recommended.

The oscillator is required to oscillate for a minimum number of cycles before the clock is considered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal reset active for a given number of clock cycles. The reset is then released and the device will start to execute. The recommended oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.

The start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is assumed to be at a sufficient level and only the start-up time is included.

6.3 Low Power Crystal Oscillator

Pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an On-chip Oscillator, as shown in Figure 6-2. Either a quartz crystal or a ceramic resonator may be used.

This Crystal Oscillator is a low power oscillator, with reduced voltage swing on the XTAL2 output. It gives the lowest power con sumption, bu t is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. In these cases, refer to the “These

options are intended for use with ceramic resonators and will ensure frequency stability at startup. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.” on page 43.

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for use with crystals are given in Table 6-3. For ceramic resonators, the capacitor values given by the manufacturer should be used.

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Figure 6-2. Crystal Oscillator Connections

The Low Power Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-3.

XTAL

GND

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AT90USB64/128

Table 6-3. Low Power Crystal Oscillator Operating Modes

Recommended Range for Capacitors

Frequency Range

0.4 - 0.9 100

(1)

(MHz) CKSEL3..1

(2)

(3)

C1 and C2 (pF)

–

0.9 - 3.0 101 12 - 22

3.0 - 8.0 110 12 - 22

8.0 - 16.0 111 12 - 22

Notes: 1. The frequency ranges are preliminary values. Actual values are TBD.

2. This option should not be used with crystals, only with ceramic resonators.

3. If 8 MHz frequency exceeds the specification of the device (depends on V

), the CKDIV8

Fuse can be programmed in order to divide the internal frequency by 8. It must be ensured that the resulting divided clock meets the frequency specification of the device.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

6-4.

Table 6-4. Start-up Times for the Low Power Crystal Oscillator Clock Selection

Oscillator Source / Power Conditions

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Ceramic resonator, BOD enabled

Start-up Time from

Power-down and

Power-save

258 CK 14CK + 4.1 ms

258 CK 14CK + 65 ms

1K CK 14CK

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

(1)

(2)

000

001

010

Ceramic resonator, fast rising power

Ceramic resonator, slowly rising power

Crystal Oscillator, BOD enabled

Crystal Oscillator, fast rising power

Crystal Oscillator, slowly rising power

1K CK 14CK + 4.1 ms

1K CK 14CK + 65 ms

16K CK 14CK 1 01

16K CK 14CK + 4.1 ms 1 10

16K CK 14CK + 65 ms 1 11

(2)

011

100

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability at start-up. They can also be used with crystals when not operating close to the maximum frequency of the device, and if frequency stability at start-up is not important for the application.

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Table 6-5. Start-up times for the internal calibrated RC Oscillator clock selection

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms

Note: 1. The device is shipped with this option selected.

6.4 Low Frequency Crystal Oscillator

The device can utilize a 32.768 kHz watch crystal as clock source by a dedicated Low Frequency Crystal Oscillator. The crystal should be connected as shown in Figure 6-2. When this Oscillator is selected, start-up times are determined by the SUT Fuses and CKSEL0 as shown in

Table 6-6.

Table 6-6. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Power Conditions

BOD enabled 1K CK 14CK Fast rising power 1K CK 14CK + 4.1 ms Slowly rising power 1K CK 14CK + 65 ms

Start-up Time from Power-

down and Power-save

Reserved 11

Start-up Time from

Power-down and

Power-save

Reserved 0 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

(1)

Additional Delay

from Reset

(VCC = 5.0V) CKSEL0 SUT1..0

(1)

000 001 010

BOD enabled 32K CK 14CK 1 00 Fast rising power 32K CK 14CK + 4.1 ms 1 01 Slowly rising power 32K CK 14CK + 65 ms 1 10

Note: 1. These options should only be used if frequency stability at start-up is not important for the

application.

6.5 Calibrated Internal RC Oscillator

The calibrated internal RC Oscillator by default provides a 8.0 MHz clock. The frequency is nominal value at 3V and 25°C. The device is shipped with the CKDIV8 Fuse programmed. See

“System Clock Prescaler” on page 48 for more details. This clock may be selected as the system

clock by programming the CKSEL Fuses as shown in Table 6-7. If selected, it will operate with no external components. During reset, hardware loads the calibration byte into the OSCCAL Register and thereby automatically calibrates the RC Oscillator. At 3V and 25°C, this calibration gives a frequency of 8 MHz ± 1%. The oscillator can be calibrated to any frequency in the range

7.3 - 8.1 MHz within ±1% accuracy, by changing the OSCCAL regist er. When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the Watchdog Timer and for

Reserved 1 11

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the Reset Time-out. For more information on the pre-programmed calibration value, see the section “Calibration Byte” on page 371

Table 6-7. Internal Calibrated RC Oscillator Operating Modes

Frequency Range

7.3 - 8.1 0010

Notes: 1. The device is shipped with this option selected.

2. The frequency ranges are preliminary values. Actual values are TBD.

3. If 8 MHz frequency exceeds the specification of the device (depends on V Fuse can be programmed in order to divide the internal frequency by 8.

(2)

(MHz) CKSEL3..0

(1)(3)

), the CKDIV8

When this Oscillator is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-5 on page 44.

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Table 6-8. Start-up times for the internal calibrated RC Oscillator clock selection

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms

Note: 1. The device is shipped with this option selected.

6.5.1 Oscillator Calibration Register – OSCCAL

Bit 76543210

CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 OSCCAL Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value Device Specific Calibration Value

• Bits 7..0 – CAL7..0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from the oscillator frequency. The factory-calibrated value is automatically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at 25°C. The application software can write this register to change the oscillator frequency. The oscillator can be calibrated to any frequency in the range 7.3 - 8.1 MHz within ±1% accuracy. Calibration outside that range is not guaranteed.

Additional Delay from

down and Power-save

Reserved 11

Reset (VCC = 5.0V) SUT1..0

(1)

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. The two frequency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 MHz.

6.6 128 kHz Internal Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The frequency is nominal at 3V and 25°C. This clock may be select as the system clock by programming the CKSEL Fuses to “11” as shown in Table 6-9.

Table 6-9. 128 kHz Internal Oscillator Operating Modes

Note: 1. The frequency is preliminary value. Actual value is TBD.

Nominal Frequency CKSEL3..0

128 kHz 0011

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7593D–AVR–07/06

AT90USB64/128

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-10.

Table 6-10. Start-up Times for the 128 kHz Internal Oscillator

6.7 External Clock

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4 ms 01 Slowly rising power 6 CK 14CK + 64 ms 10

down and Power-save

Reserved 11

Additional Delay from

Reset SUT1..0

The device can utilize a external clock source as shown in Figure 6-3. To run the device on an external clock, the CKSEL Fuses must be programmed as shown in Table 6-1.

Figure 6-3. External Clock Drive Configuration

EXTERNAL

CLOCK

SIGNAL

XTAL2

XTAL1

GND

7593D–AVR–07/06

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-11.

Table 6-11. Start-up Times for the External Clock Selection

Start-up Time from Power-

Power Conditions

BOD enabled 6 CK 14CK 00 Fast rising power 6 CK 14CK + 4.1 ms 01 Slowly rising power 6 CK 14CK + 65 ms 10

down and Power-save

Reserved 11

Additional Delay from

Reset (VCC = 5.0V) SUT1..0

When applying an external clock, it is required to avoid sudden changes in the applied clock frequency to ensure stable operation of the MCU. A variation in frequency of more than 2% from one clock cycle to the next can lead to unpredictable behavior. If changes of more than 2% is required, ensure that the MCU is kept in Reset during the changes.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

48 for details.

6.8 Clock Output Buffer

The device can output the system clock on the CLKO pin. To enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip clock is used to d rive other circuits on the system. The clock also will be output during reset, and the normal operation of I/O pin will be overridden when the fuse is programmed. Any clock source, including the internal RC Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is output.

6.9 Timer/Counter Oscillator

The device can operate its Timer/Counter2 from an external 32.768 kHz watch crystal or a external clock source. See Figure 6-2 on page 42 for crystal connection.

Applying an external clock source to TOSC1 requires EXCLK in the ASSR Register written to logic one. See “Asynchronous operation of the Timer/Counter” on page 167 for further description on selecting external clock as input instead of a 32 kHz crystal.

6.10 System Clock Prescaler

The AVR USB has a system clock prescaler, and the system clock can be divided by setting the

“Clock Prescale Register – CLKPR” on page 48. This feature can be used to decrease the sys-

tem clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk as shown in Table 6-12.

I/O

, clk

ADC

, clk

, and clk

CPU

are divided by a factor

FLASH

When switching between prescaler settings, the System Clock Prescaler ensures that no glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to th e pr eviou s setting, nor the clock frequency co rresponding to the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2 * T2 before the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the period corresponding to the new prescaler setting.

To avoid unintentional changes of clock frequency, a special write procedure must be followed to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write proce dure is not interrupted.

6.10.1 Clock Prescale Register – CLKPR

Bit 76543210

CLKPCE

Read/Write R/W R R R R/W R/W R /W R/W Initial Value 0 0 0 0 See Bit Description

–––CLKPS3CLKPS2CLKPS1CLKPS0CLKPR

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AT90USB64/128

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by hardware four cycles after it is written or when CLKPS bits are written. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.

• Bits 3..0 – CLKPS3..0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system clock. These bits can be written run-time to vary the clock frequency to suit the application requirements. As the divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-12.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a division factor of 8 at start up. This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. Note that any value can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software m ust ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse programmed.

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Table 6-12. Clock Prescaler Select

CLKPS3 CLKPS2 CLKPS1 CLKPS0 Clock Division Factor

0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 Reserved 1010 Reserved 1011 Reserved 1100 Reserved 1101 Reserved 1110 Reserved 1111 Reserved

6.1 1 PLL

The PLL is used to generate internal high frequency (48 MHz) clock for USB interface, the PLL input is generated from an external low-frequency (the crystal oscillator or external clock input pin from XTAL1). The internal RC Oscillator can not be used for USB operations.

6.11.1 Internal PLL for USB interface

The internal PLL in AT90USB64/128 generates a clock frequency that is 24x multiplie d from nominally 2 MHz input. The source of the 2 MHz PLL input clock is the output of the internal PLL clock prescaler that generates the 2 MHz (See Section 6.11.2 for PLL interface).

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Figure 6-4. PLL Clocking System

X X

PLLE

AT90USB64/128

PLOCK

Lock

Detector

PLL clock Prescaler

TAL1 TAL2

OSCILLATORS

RC OSCILLATOR 8 MHz

Watchdog

OSCILLATOR

6.11.2 PLL Control and Status Register – PLLCSR

Bit 76543210 $29 ($29) PLLP2 PLLP1 PLLP0 PLLE PLOCK PLLCSR Read/WriteRRRRRRR/WR Initial Value 0 0 0 0 0 0 0/1 0

• Bit 7..5 – Res: Reserved Bits

These bits are reserved bits in the AT90USB64/128 and always read as zero.

• Bit 4..2 – PLLP2:0 PLL prescaler

These bits allow to configure the PLL input prescaler to generate the 2MHz input clock for the PLL.

clk

2MHz

PLL 24x

clk

USB (48MHz)

System Cloc

Table 6-13. PLL input prescaler configurations

Clock Division

PLLP2 PLLP1 PLLP0

Factor

000 Reserved 001 Reserved 010 Reserved 011 4 8 100 Reserved 101 Reserved 110 8 16 111 Reserved -

External XTAL required for USB

operation (MHz)

• Bit 1 – PLLE: PLL Enable

When the PLLE is set, the PLL is started.

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• Bit 0 – PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock, and it is safe to enable PCK for Timer/Counter1. After the PLL is enabled, it takes about 100 ms for the PLL to lock.

To clear PLOCK, clear PLLE and PLLPx bits.

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7. Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the po wer consumption to the application’s requirements.

To enter any of the five sleep modes, the SE bit in SMCR must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the SMCR Register select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, or Standby) will be activated by the SLEEP instruction. See Table 7-1 for a summary. If an enabled interrup t occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and resum es execution from the instruction following SLEEP. The contents of the Register File and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector.

Figure 6-1 on page 39 presents the different clock systems in the AT90USB64/128, and their

distribution. The figure is helpful in selecting an appropriate sleep mode.

7.0.1 Sleep Mode Control Register – SMCR

The Sleep Mode Control Register contains control bits for power management.

Bit 76543210

––––SM2SM1SM0SESMCR

Read/WriteRRRRR/WR/WR/WR/W Initial Value00000000

AT90USB64/128

• Bits 3, 2, 1 – SM2..0: Sleep Mode Select Bits 2, 1, and 0

These bits select between the six available sleep modes as shown in Table 7-1.

Table 7-1. Sleep Mode Select

SM2 SM1 SM0 Sleep Mode

000Idle 0 0 1 ADC Noise Reduction 010Power-down 011Power-save 100Reserved 101Reserved 110Standby 1 1 1 Extended Standby

Note: 1. Standby mode s are only recommended for use with external crystals or resonators.

(1)

• Bit 1 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s purpose, it is recommended to write the Sleep Enab le (SE) bit to one just before the exec ution of the SLEEP instruction and to clear it immediately after waking up.

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7.1 Idle Mode

When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing the USB, SPI, USART, Analog Comparator, ADC, 2-wire Serial Interface, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep mode basically halts clk

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be po wered down by setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

7.2 ADC Noise Reduction Mode

When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, 2-wire Serial Interface address match, Timer/Counter2 and the Watchdog to continue operating (if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the other clocks to run (including clkUSB).

This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a Watchdog interrupt, a Brown-out Reset, a 2-wire serial inte rface interrupt, a Timer/Counter 2 interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT7:4 or a pin change interrupt can wakeup the MCU from ADC Noise Reduction mode.

CPU

and clk

, while allowing the other clocks to run.

FLASH

7.3 Power-down Mode

When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Powerdown mode. In this mode, the external Oscillator is stopped, while the external interrupts, the 2wire Serial Interface, and the Watchdog continue operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, 2-wire Serial Interface address match, an external level interrupt on INT7:4, an external interrupt on INT3:0, a pin change interrupt or an asynchronous USB interrupt sources (VBUSTI, WAKEUPI, IDTI and HWUPI), can wake up the MCU. This sleep mode basically halts all generated clocks, allowing operation of asynchronou s modules only.

Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level must be held for some time to wake up the MCU. Refer to “External Interrupts” on page 96 for details.

When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. This allows the clock to restart and become stable after having been stopped. The wake-up period is defined by the same CKSEL Fuses that define the Reset Time-out period, as described in “Clock Sources” on page 40.

7.4 Power-save Mode

When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Powersave mode. This mode is identical to Power-down, with one exception:

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7.5 Standby Mode

AT90USB64/128

If Timer/Counter2 is enabled, it will keep running during sleep. The device can wake up from either Timer Overflow or Output Compare event from Timer/Counter2 if the corresponding Timer/Counter2 interrupt enable bits are set in TIMSK2, and the Global Interrupt Enable bit in SREG is set.

If Timer/Counter2 is not running, Power-down mode is recommended instead of Power-save mode.

The Timer/Counter2 can be clocked both synchronously and asynchronously in Power-save mode. If the Timer/Counter2 is not using the asynchronous clock, the Timer/Counter Oscillator is stopped during sleep. If the Timer/Counter2 is not using the synchronous clock, the clock source is stopped during sleep. Note that even if the synchronous clock is running in Power-save, this clock is only available for the Timer/Counter2.

When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the exception that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.

7.6 Extended Standby Mode

When the SM2..0 bits are 111 and an external crystal/resonator clock option is selected, the SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles.

Table 7-2. Active Clock Domains and Wake-up Sources in the Different Sleep Modes.

Active Clock Domains Oscillators Wake-up Sources

CPU

Sleep Mode

clk

Idle XXXXX ADCNRM X X X X Power-down X Power-save X X Standby

(1)

Extended Standby

Notes: 1. Only recommended with external crystal or resonator selected as clock source.

2. If Timer/Counter2 is running in asynchronous mode.

3. For INT7:4, only level interrupt.

4. Asynchronous USB interrupts are VBUSTI, WAKEUPI, IDTI, WAKEUPI and HWUPI.

FLASH

clk

ADC

clkIOclk

ASY

clk

Main Clock

Source

Enabled

Timer Osc

Enabled

INT7:0 and

Pin Change

TWI Address

Match

Timer2

SPM/

(2)

XXXXXXXXX

(2)

(3)

(2)

(3)

XXX

(3)

XXXX

(3)

XXX

(3)

XXXX

(2)

XXX XX

EEPROM Ready

ADC

(4)

WDT Interrupt

Other I/O

USB Synchronous

Interrupts

USB Asynchonous

Interrupts

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7.7 Power Reduction Register

The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power consumption. See “Supply Current of IO modules” on page 429 for examples. In all other sleep modes, the clock is already stopped.

7.7.1 Power Reduction Register 0 - PRR0

Bit 7654321 0

PRTWI PRTIM2 PRTIM0 – PRTIM1 PRSPI - PRADC PRR0

Read/Write R/W R/W R/W R R/W R/W R R/W Initial Value0000000 0

• Bit 7 - PRTWI: Power Reduction TWI

Writing a logic one to this bit shuts down the TWI by stopping the clock to the module. When waking up the TWI again, the TWI should be re initialized to ensure proper operation.

• Bit 6 - PRTIM2: Power Reduction Timer/Counter2

Writing a logic one to this bit shuts down the Timer/Co unte r2 module in synchrono us mode ( AS2 is 0). When the Timer/Counter2 is enabled, operation will continue like before the shutdown.

• Bit 5 - PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0 is enabled, operation will continue like before the shutdown.

• Bit 4 - Res: Reserved bit

This bit is reserved and will always read as zero.

• Bit 3 - PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown.

• Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface

Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to the module. When waking up the SPI again, the SPI should be re initialized to ensure proper operation.

• Bit 1 - Res: Reserved bit

These bits are reserved and will always read as zero.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disa bled before sh ut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.

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7.7.2 Power Reduction Register 1 - PRR1

Bit 7 6543 210

PRUSB–––PRTIM3––PRUSART1PRR1

Read/WriteR/WRRRR/W RRR/W Initial Value0 0000 000

• Bit 7 - PRUSB: Power Reduction USB

Writing a logic one to this bit shuts down the USB by stopping the clock to the module. When waking up the USB again, the USB should be re initialized to ensure proper operation.

• Bit 6..4 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 3 - PRTIM3: Power Reduction Timer/Counter3

Writing a logic one to this bit shuts down the Timer/Counter3 module. When the Timer/Counter3 is enabled, operation will continue like before the shutdown.

• Bit 2..1 - Res: Reserved bits

These bits are reserved and will always read as zero.

• Bit 0 - PRUSART1: Power Reduction USART1

Writing a logic one to this bit shuts down the USART1 by stopping the clock to the module. When waking up the USART1 again, the USART1 should be re initialized to ensure proper operation.

AT90USB64/128

7.8 Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device’s functions are operating. All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption.

7.8.1 Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be disabled before entering any sleep mode. When the ADC is turned off and on again, the next conversion will be an extended conversion. Refer to “Analog to Digital Converter - ADC” on page

316 for details on ADC operation.

7.8.2 Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is set up to use the Internal Voltage Reference as input, the Analog Comparator should be disabled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled, independe nt of sleep mode. Refer to “Analog Comparator” on page 313 for details on how to configure the Analog Comparator.

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7.8.3 Brown-out Detector

If the Brown-out Detector is not needed by the a pplication, this modu le should be turned off . If the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Brown-out Detection” on page 61 for details on how to configure the Brown-out Detector.

7.8.4 Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the Analog Comparator or the ADC. If these modules are disabled as described in the sections above, the internal voltage reference will be disabled and it will not be consuming power. When turned on again, the user must allow the reference to start up before the output is used. If the reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 64 for details on the start-up time.

7.8.5 Watchdog Timer

If the Watchdog Timer is not needed in the application, the module should be turned off. If the Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume power. In the deeper sleep modes, this will contribute significantly to the total current consumption. Refer to “Interrupts” on page 70 for details on how to configure the Watchdog Timer.

7.8.6 Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk be disabled. This ensures that no power is consumed by the input logic when not needed. In some cases, the input logic is needed for detecting wake-up conditions, and it will then be enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 78 for details on which pins are enabled. If the input buffer is enabled and the input signal is left floating or have an analog signal level close to V

For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close to V input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and DIDR0). Refer to “Digital Input Disable Register 1 – DIDR1” on page 315 and “Digital Input Dis-

able Register 1 – DIDR1” on page 315 for details.

) and the ADC clock (clk

I/O

/2, the input buffer will use excessive power.

/2 on an input pin can cause significant current even in active mode. Digital

) are stopped, the input buffers of the device will

ADC

7.8.7 On-chip Debug System

If the On-chip debug system is enabled by the OCDEN Fuse and the chip enters sleep mode, the main clock source is enabled, and hence, always consumes power. In the deeper sleep modes, this will contribute significantly to the total current consumption.

There are three alternative ways to disable the OCD system:

• Disable the OCDEN Fuse.

• Disable the JTAGEN Fuse.

• Write one to the JTD bit in MCUCR.

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8. System Control and Reset

8.0.1 Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP – Absolute Jump – instruction to the reset handling routine. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. The circuit diagram in Figure 8-1 shows the reset logic. Table 8-1 defines the electrical parameters of the reset circuitry.

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. This allows the power to reach a stable level before normal operation starts. The time-out period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The different selections for the delay period are presented in “Clock Sources” on page 40.

8.0.2 Reset Sources

The AT90USB64/128 has five sources of reset:

AT90USB64/128

• Power-on Reset. The MCU is reset when the su pply voltage is below the Power-on Reset

threshold (V

• External Reset. The MCU is reset when a low level is present on the RESET

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply vo ltage V

Reset threshold (V

• JTAG AVR Reset. The MCU is reset as long as there is a logic one in the Reset Register, one

of the scan chains of the JTAG system. Refer to the section “IEEE 1149.1 (JTAG) Boundary-

scan” on page 341 for details.

POT

) and the Brown-out Detector is enabled.

BOT

pin for longer

is below the Brown-out

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Figure 8-1. Reset Logic

Power-on Reset

Circuit

DATA BU S

MCU Status

JTRF

BORF

PORF

WDRF

EXTRF

BODLEVEL [2..0]

Pull-up Resistor

SPIKE

FILTER

JTAG Reset

Table 8-1. Reset Characteristics

Brown-out

Reset Circuit

Watchdog

Oscillator

Clock

Generator

CKSEL[3:0]

SUT[1:0]

(1)

Delay Counters

TIMEOUT

Symbol Parameter Condition Min Typ Max Units

POT

Power-on Reset Threshold Voltage (rising)

Power-on Reset Threshold Voltage (falling)

(2)

TBD TBD TBD V

8.0.3 Power-on Reset

AT90USB64/128

RST

RESET Pin Threshold Voltage TBD TBD TBD V Minimum pulse width on RESET

TBD TBD TBD ns

Notes: 1. Values are guidelines only. Actual values are TBD.

2. The Power-on Reset will not work unless the supply voltage has been below V

POT

(falling)

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined in Table 8-1. The POR is activated whenever V

is below the detection level. The

POR circuit can be used to trigger the start-up Reset, as well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reac hing the Power-on Reset threshold voltage invokes the delay counter, which determines how long the device is kept in RESET after V when V

decreases below the detection level.

rise. The RESET signal is activated again, without any delay,

7593D–AVR–07/06

AT90USB64/128

RESET

Figure 8-2. MCU Start-up, RESET Tied to V

RESET

IME-OUT

NTERNAL

POT

RST

TOUT

Figure 8-3. MCU Start-up, RESET Extended Externally

RESET

IME-OUT

POT

RST

TOUT

8.0.4 External Reset

NTERNAL

RESET

An External Reset is generated by a low level on the RESET

pin. Reset pulses longer than the minimum pulse width (see Table 8-1) will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage – V the Time-out period – t

TOUT –

– on its positive edge, the delay counter starts the MCU after

RST

has expired.

Figure 8-4. External Reset During Operation

8.0.5 Brown-out Detection

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AT90USB64/128 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V

level

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the BODLEVEL Fuses. The trigger level has a hyste resis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V V

+ V

BOT

Table 8-2. BODLEVEL Fuse Coding

HYST

/2 and V

BOT-

= V

BOT

- V

HYST

/2.

(1)

BOT+

BODLEVEL 2..0 Fuses Min V

BOT

Typ V

BOT

Max V

BOT

Units

111 BOD Disabled 110 2.0 101 2.2 100 2.4 011 2.6 010 3.4 001 3.5 000 4.3

Note: 1. V

may be below nominal minimum operating voltage for some devices. For devices where

BOT

this is the case, the device is tested down to VCC = V antees that a Brown-Out Reset will occur before V

during the production test. This guar-

BOT

drops to a voltage where correct

operation of the microcontroller is no longer guaranteed. The test is performed using BODLEVEL = 110 for AT90USB64/128 and BODLEVEL = 101 for AT90USB64/128L.

Table 8-3. Brown-out Characteristics

Symbol Parameter Min Typ Max Units

V t

BOD

HYST

Brown-out Detector Hysteresis 50 mV Min Pulse Width on Brown-out Reset ns

When the BOD is enabled, and VCC decreases to a value below the trigger level (V

8-5), the Brown-out Reset is immediately activated. When V

in Figure 8-5), the delay counter starts the MCU after the Time-out period t

BOT+

increases above the trigger level

expired. The BOD circuit will only detect a drop in V

longer than t

given in Table 8-1.

BOD

if the voltage stays below the trigger level for

Figure 8-5. Brown-out Reset During Operation

RESET

IME-OUT

NTERNAL

RESET

BOT-

BOT+

TOUT

in Figure

BOT-

TOUT

has

AT90USB64/128

7593D–AVR–07/06

8.0.6 Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t

page 64 for details on operation of the Watchdog Timer.

Figure 8-6. Watchdog Reset During Operation

8.0.7 MCU Status Register – MCUSR

The MCU Status Register provides information on which reset source caused an MCU reset.

AT90USB64/128

. Refer to

TOUT

Bit 76543210

– – – JTRF WDRF BORF EXTRF PORF MCUSR

Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 See Bit Description

• Bit 4 – JTRF: JTAG Reset Flag

This bit is set if a reset is being caused by a logic one in the JTAG Reset Register selected by the JTAG instruction AVR_RESET. This bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

7593D–AVR–07/06

To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags.

8.1 Internal Voltage Reference

AT90USB64/128 features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.1.1 Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in Table 8-4. To save power, the reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse).

2. When the bandgap reference is connected to the Analog Comparator (by setting the ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user must always allow the reference to start up before the output from the Analog Comparator or ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering Power-down mode.

Table 8-4. Internal Voltage Reference Characteristics

Note: 1. Values are guidelines only. Actual values are TBD.

8.2 Watchdog Timer

AT90USB64/128 has an Enhanced Watchdog Timer (WDT). The main features are:

•

• 3 Operating modes

(1)

Symbol Parameter Condition Min Typ Max Units

Clocked from separate On-chip Oscillator

–Interrupt – System Reset – Interrupt and System Reset

Bandgap reference voltage TBD TBD 1.1 TBD V

Bandgap reference start-up time TBD 40 70 µs Bandgap reference current

consumption

TBD 10 TBD µA

AT90USB64/128

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AT90USB64/128

• Selectable Time-out period from 16ms to 8s

• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode

Figure 8-7. Watchdog Timer

128kHz

OSCILLATOR

OSC/2K

OSC/4K

OSC/8K

OSC/16K

OSC/32K

OSC/64K

OSC/128K

OSC/256K

OSC/512K

OSC/1024K

WDP0

WATCHDOG RESET

WDP1 WDP2 WDP3

WDE

WDIF

WDIE

MCU RESET

INTERRUPT

The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode, it is required that the system uses the WDR - Watchdog Timer Reset

- instruction to restart the counter before the time-out value is reached. If the system doesn't restart the counter, an interrupt or system reset will be issued.

In Interrupt mode, the WDT gives an interrupt when the timer expires. T his inter rupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. In System Reset mode, the WDT gives a reset when the timer expires. This is typically used to prevent system hang-up in case of runaway code. The third mode, Interrupt and System Reset mode, combines the other two modes by first giving an interrupt and then switch to System Reset mode. This mode will for instance allow a safe shutdown by saving critical parameters before a system reset.

The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Interrupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security, alterations to the Watchdog set-up must follow timed sequences. The sequen ce for clearing WDE and changing time-out configuration is as follows:

7593D–AVR–07/06

1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE) and WDE. A logic one must be written to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP) a s desired, but with the WDCE bit cleared. This must be done in one operation.

The following code example shows one assembly and one C function for turning off the Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of these functions.

Assembly Code Example

WDT_off:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Clear WDRF in MCUSR

in r16, MCUSR

andi r16, (0xff & (0<<WDRF))

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional time-out

in r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCSR, r16

; Turn on global interrupt

sei

ret

C Code Example

(1)

void WDT_off(void)

{

__disable_interrupt();

__watchdog_reset();

/* Clear WDRF in MCUSR */

MCUSR &= ~(1<<WDRF);

/* Write logical one to WDCE and WDE */

/* Keep old prescaler setting to prevent unintentional time-out

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

__enable_interrupt();

}

Note: 1. The example code assumes that the part specific header file is included.

Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code is n ot set up to handle the Watchdog, this might lead to an eternal loop of time-out resets. To avoid this situation, the application software should always clear the Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialisation routine, even if the Watchdog is not in use.

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

The following code example shows one assembly and one C function for changing the time-out value of the Watchdog Timer.

Assembly Code Example

WDT_Prescaler_Change:

; Turn off global interrupt

cli

; Reset Watchdog Timer

wdr

; Start timed sequence

in r16, WDTCSR

ori r16, (1<<WDCE) | (1<<WDE)

out WDTCSR, r16

; -- Got four cycles to set the new values from here -

; Set new prescaler(time-out) value = 64K cycles (~0.5 s)

ldi r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)

out WDTCSR, r16

; -- Finished setting new values, used 2 cycles -

; Turn on global interrupt

sei

ret

C Code Example

void WDT_Prescaler_Change(void)

{

__disable_interrupt();

__watchdog_reset();

/* Start timed equence */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */

WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);

__enable_interrupt();

}

(1)

Note: 1. The example code assumes that the part specific header file is included.

Note: The Watchdog Timer should be reset before any change of the WDP bits, since a change in the WDP bits can result in a time-out when switching to a shorter time-out period.

8.2.1 Watchdog Timer Control Register - WDTCSR

Bit 76543210

WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 WDTCSR

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value0000X000

• Bit 7 - WDIF: Watchdog Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is configured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

7593D–AVR–07/06

handling vector. Alternatively, WDIF is cleared by writing a logic on e to the flag. When the I-bit in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 - WDIE: Watchdog Interrupt Enable

When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Interrupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer occurs.

If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This sho uld however not be don e within the interrupt service routine itself, as this might compromise the safety-function of the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a System Reset will be applied.

Table 8-5. Watchdog Timer Configuration

WDTON WDE WDIE Mode Action on Time-out

0 0 0 Stopped None 0 0 1 Interrupt Mode Interrupt 0 1 0 System Reset Mode Reset

011

1 x x System Reset Mode Reset

Interrupt and System Reset Mode

Interrupt, then go to System Reset Mode

• Bit 4 - WDCE: Watchdog Change Enab le

This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE bit, and/or change the prescaler bits, WDCE must be set.

Once written to one, hardware will clear WDCE after four clock cycles.

• Bit 3 - WDE: Watchdog System Reset Enable

WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets dur ing conditions causing failure, and a safe start-up after the failure.

• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0

The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is running. The different prescaling values and their corresponding time-out periods are shown in

Table 8-6 on page 69.

AT90USB64/128

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Table 8-6. Watchdog Timer Prescale Select

AT90USB64/128

Number of WDT Oscillator

WDP3 WDP2 WDP1 WDP0

0 0 0 0 2K (2048) cycles 16 ms 0 0 0 1 4K (4096) cycles 32 ms 0 0 1 0 8K (8192) cycles 64 ms 0 0 1 1 16K (16384) cycles 0.125 s 0 1 0 0 32K (32768) cycles 0.25 s 0 1 0 1 64K (65536) cycles 0.5 s 0 1 1 0 128K (131072) cycles 1.0 s 0 1 1 1 256K (262144) cycles 2.0 s 1 0 0 0 512K (524288) cycles 4.0 s 1 0 0 1 1024K (1048576) cycles 8.0 s 1010 1011 1100 1101 1110 1111

Cycles

Reserved

Typical Time-out at

VCC = 5.0V

7593D–AVR–07/06

9. Interrupts

This section describes the specifics of the interrupt handling as performed in AT90USB64/128. For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 16.

9.1 Interrupt Vectors in AT90USB64/128

Table 9-1. Reset and Interrupt Vectors

Vector

No.

1 $0000

2 $0002 INT0 External Interrupt Request 0 3 $0004 INT1 External Interrupt Request 1 4 $0006 INT2 External Interrupt Request 2 5 $0008 INT3 External Interrupt Request 3 6 $000A INT4 External Interrupt Request 4 7 $000C INT5 External Interrupt Request 5 8 $000E INT6 External Interrupt Request 6 9 $0010 INT7 External Interrupt Request 7

10 $0012 PCINT0 Pin Change Interrupt Request 0

11 $0014 USB General USB General Interrupt request

12 $0016

13 $0018 WDT Watchdog Time-out Interrupt 14 $001A TIMER2 COMPA Timer/Counter2 Compare Match A 15 $001C TIMER2 COMPB Timer/Counter2 Compare Match B 16 $001E TIMER2 OVF Timer/Counter2 Overflow 17 $0020 TIMER1 CAPT Timer/Counter1 Capture Event

Program

Address

(2)

Source Interrupt Definition

(1)

RESET

USB Endpoint/Pipe

External Pin, Power-on Reset, Brown-out Reset, Watchdog Reset, and JTAG AVR Reset

USB ENdpoint/Pipe Interrupt request

18 $0022 TIMER1 COMPA Timer/Counter1 Compare Match A 19 $0024 TIMER1 COMPB Timer/Counter1 Compare Match B 20 $0026 TIMER1 COMPC Timer/Counter1 Compare Match C 21 $0028 TIMER1 OVF Timer/Counter1 Overflow 22 $002A TIMER0 COMPA Timer/Counter0 Compare Match A 23 $002C TIMER0 COMPB Timer/Counter0 Compare match B 24 $002E TIMER0 OVF Timer/Counter0 Overflow 25 $0030 SPI, STC SPI Serial Transfer Complete 26 $0032 USART1 RX USART1 Rx Complete 27 $0034 USART1 UDRE USART1 Data Register Empty 28 $0036 USART1TX USART1 Tx Complete

AT90USB64/128

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Table 9-1. Reset and Interrupt Vectors (Continued)

AT90USB64/128

Vector

No.

29 $0038 ANALOG COMP Analog Comparator 30 $003A ADC ADC Conversion Complete 31 $003C EE READY EEPROM Ready 32 $003E TIMER3 CAPT Timer/Counter3 Capture Event 33 $0040 TIMER3 COMPA Timer/Counter3 Compare Match A 34 $0042 TIMER3 COMPB Timer/Counter3 Compare Match B 35 $0044 TIMER3 COMPC Timer/Counter3 Compare Match C 36 $0046 TIMER3 OVF Timer/Counter3 Overflow 37 $0048 TWI 2-wire Serial Interface 38 $004A SPM READY Store Program Memory Ready

Notes: 1. When the BOOTRST Fuse is programmed, the device will jump to the Boot Loader address at

Program

Address

reset, see “Memory Programming” on page 368.

2. When the IVSEL bit in MCUCR is set, Interrupt Vectors will be moved to the start of the Boot Flash Section. The address of each Interrupt Vector will then be the address in this table added to the start address of the Boot Flash Section.

(2)

Source Interrupt Definition

Table 9-2 shows reset and Interrupt Vectors placement for the various combinations of

BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these lo cations. This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa.

7593D–AVR–07/06

Table 9-2. Reset and Interrupt Vectors Placement

BOOTRST IVSEL Reset Address Interrupt Vectors Start Address

1 0 0x0000 0x0002 1 1 0x0000 Boot Reset Address + 0x0002 0 0 Boo t Rese t Address 0x0002 0 1 Boot Reset Address Boot Reset Address + 0x0002

Note: 1. The Boot Reset Address is shown in Table 28-8 on page 366. For the BOOTRST Fuse “1”

means unprogrammed while “0” means programmed.

9.1.1 Moving Interrupts Between Application and Boot Space

The General Interrupt Control Register controls the placement of the Interrupt Vector table.

9.1.2 MCU Control Register – MCUCR

Bit 76543210

JTD – – PUD – – IVSEL IVCE MCUCR

Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 1 – IVSEL: Interrupt Vector Select

When the IVSEL bit is cleared (zero), the Interrupt Vectors are placed at the start of the Flash memory. When this bit is set (one), the Interrupt Vectors are moved to the beginning of the Boot Loader section of the Flash. The actual address of the start of the Boot Flash Section is determined by the BOOTSZ Fuses. Refer to the section “Memory Programming” on p age 368 for details. To avoid unintentional changes of Interrupt Vector tables, a special write procedur e must be followed to change the IVSEL bit:

(1)

a. Write the Interrupt Vector Change Enable (IVCE) bit to one. b. Within four cycles, write the desired value to IVSEL while writing a zero to IVCE.

Interrupts will automatically be disabled while this sequence is executed. Interrupts are disabled in the cycle IVCE is set, and they remain disabled until after the instruction following the write to IVSEL. If IVSEL is not written, interrupts remain disabled for four cycles. The I-bit in the Status Register is unaffected by the automatic disabling.

Note: If Interrupt Vectors are placed in the Boot Loader section and Boot Lock bit BLB02 is pro-

grammed, interrupts are disabled while executing from the Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section “Memory Programming”

on page 368 for details on Boot Lock bits.

• Bit 0 – IVCE: Interrupt Vector Change Enable

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

The IVCE bit must be written to logic one to enable change of the IVSEL bit. IVCE is cleared by hardware four cycles after it is written or when IVSEL is written. Setting the IVCE bit will disable interrupts, as explained in the IVSEL description above. See Code Example below .

Assembly Code Example

Move_interrupts:

; Enable change of Interrupt Vectors

ldi r16, (1<<IVCE)

out MCUCR, r16

; Move interrupts to Boot Flash section

ldi r16, (1<<IVSEL)

out MCUCR, r16

ret

C Code Example

void Move_interrupts(void)

{

/* Enable change of Interrupt Vectors */

MCUCR = (1<<IVCE);

/* Move interrupts to Boot Flash section */

MCUCR = (1<<IVSEL);

}

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10. I/O-Ports

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the SBI and CBI instructions. The same applies when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if con figured as input). Each output buffer has symmetrical drive characteristics with both high sink and source capability. The pin driver is strong enough to drive LED displays directly. All port pins have individually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have protection diodes to both V

acteristics” on page 400 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

and Ground as indicated in Figure 10-1. Refer to “Electrical Char-

All registers and bit references in this section are written in general form. A lower case “x” represents the numbering letter for the port, and a lower case “n” represents the bit number. However, when using the register or bit defines in a program, the precise form must be used. For example, PORTB3 for bit no. 3 in Port B, here documented ge nerally a s PORTxn . The physical I/O Registers and bit locations are listed in “Register Description for I/O-Ports” on page 92.

Three I/O memory address locations are allocated for each port, one each for the Data Register – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins I/O location is read only, while the Data Register and the Da ta Dir ec tion Register are read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

75. Most port pins are multiplexed with alternate func tions for the peripheral feat ures on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 79. Refer to the individual module sections for a full description of the alter-

nate functions.

AT90USB64/128

7593D–AVR–07/06

Note that enabling the alternate function of some of the port pins does not affect the use of the other pins in the port as general digital I/O.

10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 sho ws a func- tional description of one I/O-port pin, here generically called Pxn.

AT90USB64/128

Figure 10-2. General Digital I/O

Pxn

PUD: PULLUP DISABLE SLEEP: SLEEP CONTROL clk

: I/O CLOCK

I/O

(1)

SLEEP

SYNCHRONIZER

DLQ

PINxn

PUD

DDxn

CLR

RESET

PORTxn

CLR

RESET

WDx: WRITE DDRx RDx: READ DDRx WRx: WRITE PORTx RRx: READ PORTx REGISTER RPx: READ PORTx PIN WPx: WRITE PINx REGISTER

WDx

RDx

RRx

RPx

clk

I/O

WRx

DATA BUS

WPx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

10.2.1 Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description for I/O-Ports” on page 92, the DDxn bits are accessed at the DDRx I/O address, the

PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O address. The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to be configured as an output pin. The por t pins are tri-stated when reset condition becomes active, even if no clocks are running.

7593D–AVR–07/06

SLEEP, and PUD are common to all ports.

I/O

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero).

10.2.2 Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port.

10.2.3 Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn} = 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output low ({DDxn, PORTxn} = 0b10) occurs. Normally, the pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to dis able all pullups in all ports.

Switching between input with pull-up and output low generates the same problem. The user must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn} = 0b11) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

DDxn PORTxn

0 0 X Input No Tri-state (Hi-Z)

(in MCUCR) I/O Pull-up Comment

PUD

0 1 0 Input Yes

0 1 1 Input No Tri-state (Hi-Z) 1 0 X Output No Output Low (Sink) 1 1 X Output No Output High (Source)

10.2.4 Reading the Pin Value

Independent of the setting of Data Direction b it DDxn, the port pin can be read through the PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit a nd th e precedin g latch constitute a synchronizer. This is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. Figure 10- 3 shows a timing diagram of the synchronization when reading an externally applied pin value. The maximum and minimum propagation delays are deno te d t

pd,max

Pxn will source current if ext. pulled low.

and t

respectively.

pd,min

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

INSTRUCTIONS

XXX in r17, PINx

XXX

SYNC LATCH

PINxn

r17

0x00 0xFF

pd, max

pd, min

Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indicated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

r16

INSTRUCTIONS

out PORTx, r16 nop in r17, PINx

0xFF

SYNC LATCH

PINxn

r17

0x00 0xFF

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The resulting pin values are read back again, but as previously discussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins.

7593D–AVR–07/06

Assembly Code Example

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in r16,PINB

...

(1)

C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

__no_operation();

/* Read port pins */

i = PINB;

...

Note: 1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers.

10.2.5 Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode, Power-save mode, and Standb y mode to avoid high power consu mption if some input signals are left floating, or have an analog signal level close to V

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various other alternate functions as described in “Alternate Port Functions” on page 79.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as “Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from the above mentioned Sleep mode, as the clamping in these sleep mode produces the requested logic change.

10.2.6 Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins h ave a de fined level. Even though most of the digital inputs are disabled in the deep sleep modes as descri bed above, float-

/2.

AT90USB64/128

7593D–AVR–07/06

ing inputs should be avoided to reduce current consumption in all other modes where the digital inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during reset is important, it is recommended to use an extern al pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5 shows how the port pin control signals from th e simplified Figure 10-2 can be overridden by alternate functions. The overriding signals may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the AVR microcontroller family.

AT90USB64/128

or GND is not recommended, since this may cause exce ssive curr ents if the pin is

Figure 10-5. Alternate Port Functions

Pxn

(1)

PUOExn

PUOVxn

DDOExn

DDOVxn

PVOExn

PVOVxn

DIEOExn

DIEOVxn

SLEEP

SYNCHRONIZER

SET

DLQ

CLR

PINxn

CLR

PORTxn

CLR

RESET

DDxn

PUD

CLR

WDx

RDx

RRx

RPx

clk

I/O

WRx

PTOExn

WPx

DATA BUS

7593D–AVR–07/06

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE PUOVxn: Pxn PULL-UP OVERRIDE VALUE DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE PVOExn: Pxn PORT VALUE OVERRIDE ENABLE PVOVxn: Pxn PORT VALUE OVERRIDE VALUE DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: SLEEP CONTROL PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

PUD: PULLUP DISABLE WDx: WRITE DDRx RDx: READ DDRx RRx: READ PORTx REGISTER WRx: WRITE PORTx RPx: READ PORTx PIN WPx: WRITE PINx clk

: I/O CLOCK

I/O

DIxn: DIGITAL INPUT PIN n ON PORTx AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx

Note: 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

I/O

Table 10-2 summarizes the function of the overriding signals. The pin and por t indexes from Fig- ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name Full Name Description

If this signal is set, the pull-up enable is controlled by the PUOV signal. If this signal is cleared, the pull-up is enabled when {DDxn, PORTxn, PUD} = 0b010.

If PUOE is set, the pull-up is enabled/disabled when PUOV is set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD Register bits.

If this signal is set, the Output Driver Enable is controlled by the DDOV signal. If this signal is cleared, the Output driver is enabled by the DDxn Register bit.

If DDOE is set, the Output Driver is enabled/disabled when DDOV is set/cleared, regardless of the setting of the DDxn Register bit.

If this signal is set and the Output Driver is enabled, the port value is controlled by the PVOV signal. If PVOE is cleared, and the Output Driver is enabled, the port Value is controlled by the PORTxn Register bit.

PUOE

PUOV

DDOE

DDOV

PVOE

Pull-up Override Enable

Pull-up Override Value

Data Direction Override Enable

Data Direction Override Value

Port Value Override Enable

PVOV

PTOE

DIEOE

DIEOV

DI Digital Input

AIO

Port Value Override Value

Port Toggle Override Enable

Digital Input Enable Override Enable

Digital Input Enable Override Value

Analog Input/Output

If PVOE is set, the port value is set to PVOV, regardless of the setting of the PORTxn Register bit.

If PTOE is set, the PORTxn Register bit is inverted.

If this bit is set, the Digital Input Enable is controlled by the DIEOV signal. If this signal is cleared, the Digital Input Enable is determined by MCU state (Normal mode, sleep mode).

If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is set/cleared, regardless of the MCU state (Normal mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer.

This is the Analog Input/output to/from alternate functions. The signal is connected directly to the pad, and can be used bi-directionally.

The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function description for further details.

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10.3.1 MCU Control Register – MCUCR

Bit 7 6 5 4 3 2 1 0

JTD – –PUD– – IVSEL IVCE MCUCR Read/Write R/W R R R/W R R R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 4 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 75 for more details about this feature.

10.3.2 Alternate Functions of Port A

The Port A has an alternate function as the address low byte and data lines for the External Memory Interface.

Table 10-3. Port A Pins Alternate Functions

Port Pin Alternate Function

PA7 AD7 (External memory interface address and data bit 7) PA6 AD6 (External memory interface address and data bit 6) PA5 AD5 (External memory interface address and data bit 5) PA4 AD4 (External memory interface address and data bit 4) PA3 AD3 (External memory interface address and data bit 3)

AT90USB64/128

PA2 AD2 (External memory interface address and data bit 2) PA1 AD1 (External memory interface address and data bit 1) PA0 AD0 (External memory interface address and data bit 0)

Table 10-4 and Table 10-5 relates the alternate functions of Port A to the overriding signals

shown in Figure 10-5 on page 79.

Table 10-4. Overriding Signals for Alternate Functions in PA7..PA4

Signal Name PA7/AD7 PA6/AD6 PA5/AD5 PA4/AD4

PUOE SRE SRE SRE SRE

| ADA

(1)

) •

~(WR | ADA) • PORTA6 • PUD

A6 • ADA | D6 OUTPUT • WR

~(WR | ADA) • PORTA5 • PUD

A5 • ADA | D5 OUTPUT • WR

~(WR | ADA) • PORTA4 • PUD

A4 • ADA | D4 OUTPUT • WR

PUOV

DDOE SRE SRE SRE SRE DDOV WR PVOE SRE SRE SRE SRE

PVOV

DIEOE 0 0 0 0 DIEOV 0 0 0 0 DID7 INPUTD6 INPUTD5 INPUTD4 INPUT

~(WR PORTA7 • PUD

| ADA WR | ADA WR | ADA WR | ADA

A7 • ADA | D7 OUTPUT • WR

7593D–AVR–07/06

AIO – – – –

Note: 1. ADA is short for ADdress Active and represents the time when address is output. See “Exter-

nal Memory Interface” on page 30 for details.

Table 10-5. Overriding Signals for Alternate Functions in PA3..PA0

Signal Name PA3/AD3 PA2/AD2 PA1/AD1 PA0/AD0

PUOE SRE SRE SRE SRE

PUOV

DDOE SRE SRE SRE SRE DDOV WR PVOE SRE SRE SRE SRE

~(WR | ADA) • PORTA3 • PUD

| ADA WR | ADA WR | ADA WR | ADA

~(WR | ADA) • PORTA2 • PUD

~(WR | ADA) • PORTA1 • PUD

~(WR | ADA) • PORTA0 • PUD

PVOV

DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI D3 INPUT D2 INPUT D1 INPUT D0 INPUT AIO – – – –

A3 • ADA | D3 OUTPUT • WR

10.3.3 Alternate Functions of Port B

The Port B pins with alternate functions are shown in Table 10-6.

Table 10-6. Port B Pins Alternate Functions

Port Pin Alternate Functions

PB7

PB6

PB5

PB4

PB3

OC0A/OC1C/PCINT7 (Output Compare and PWM Output A for Timer/Counter0, Output Compare and PWM Output C for Timer/Counter1 or Pin Change Interrupt 7)

OC1B/PCINT6 (Output Compare and PWM Output B for Timer/Counter1 or Pin Change Interrupt 6)

OC1A/PCINT5 (Output Compare and PWM Output A for Timer/Counter1 or Pin Change Interrupt 5)

OC2A/PCINT4 (Output Compare and PWM Output A for Timer/Counter2 or Pin Change Interrupt 4)

PDO/MISO/PCINT3 (Programming Data Output or SPI Bus Master Input/Slave Output or Pin Change Interrupt 3)

A2• ADA | D2 OUTPUT • WR

A1 • ADA | D1 OUTPUT • WR

A0 • ADA | D0 OUTPUT • WR

PB2

PB1 SCK/PCINT1 (SPI Bus Serial Clock or Pin Change Interrupt 1) PB0 SS

PDI/MOSI/PCINT2 (Programming Data Input orSPI Bus Master Output/Slave Input or Pin Change Interrupt 2)

The alternate pin configuration is as follows:

• OC0A/OC1C/PCINT7, Bit 7

OC0A, Output Compare Match A output: The PB7 pin can serve as an external output for the Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB7 set “one”) to serve this function. The OC0A pin is also the output pin for the PWM mode timer function.

AT90USB64/128

/PCINT0 (SPI Slave Select input or Pin Change Interrupt 0)

7593D–AVR–07/06

AT90USB64/128

OC1C, Output Compare Match C output: The PB7 pin can serve as an external output for the Timer/Counter1 Output Compare C. The pin has to be configur ed as a n o utput ( DDB7 set ( one )) to serve this function. The OC1C pin is also the output pin for the PWM mode timer function.

PCINT7, Pin Change Interrupt source 7: The PB7 pin can serve as an external interrupt source.

• OC1B/PCINT6, Bit 6

OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one )) to serve this function. The OC1B pin is also the output pin for the PWM mode timer function.

PCINT6, Pin Change Interrupt source 6: The PB7 pin can serve as an external interrupt source.

• OC1A/PCINT5, Bit 5

OC1A, Output Compare Match A output: The PB5 pin can serve as an external output for the Timer/Counter1 Output Compare A. The pin has to be configured as an output (DDB5 set (one )) to serve this function. The OC1A pin is also the output pin for the PWM mode timer function.

PCINT5, Pin Change Interrupt source 5: The PB7 pin can serve as an external interrupt source.

• OC2A/PCINT4, Bit 4

OC2A, Output Compare Match output: The PB4 pin can serve as an external output for the Timer/Counter2 Output Compare. The pin has to be configured as an output (DDB4 set (one)) to serve this function. The OC2A pin is also the output pin for the PWM mode timer function.

PCINT4, Pin Change Interrupt source 4: The PB7 pin can serve as an external interrupt source.

• PDO/MISO/PCINT3 – Port B, Bit 3

PDO, SPI Serial Programming Data Output. During Serial Program Downloading, this pin is used as data output line for the AT90USB64/128.

MISO: Master Data input, Slave Data outp ut pin for SPI channel. When the SPI is enabled as a master, this pin is configured as an input regardless of the setting of DDB3. When the SPI is enabled as a slave, the data direction of this pin is controlle d by DDB3. When the pin is forc ed to be an input, the pull-up can still be controlled by the PORTB3 bit.

PCINT3, Pin Change Interrupt source 3: The PB7 pin can serve as an external interrupt source.

• PDI/MOSI/PCINT2 – Port B, Bit 2

PDI, SPI Serial Programming Data Input. During Serial Program Downloading, this pin is use d as data input line for the AT90USB64/128.

MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.

PCINT2, Pin Change Interrupt source 2: The PB7 pin can serve as an external interrupt source.

• SCK/PCINT1 – Port B, Bit 1

SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB1. When the SPI0 is enabled as a master, the data direction of this pin is controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.

7593D–AVR–07/06

PCINT1, Pin Change Interrupt source 1: The PB7 pin can serve as an external interrupt source.

•SS

/PCINT0 – Port B, Bit 0

: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an input regardless of the setting of DDB0. As a slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB0 bit.

Table 10-7 and Table 10-8 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 79. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI MSTR OUTPUT and SPI SLAVE INPUT.

PCINT0, Pin Change Interrupt source 0: The PB7 pin can serve as an external interrupt source..

Table 10-7. Overriding Signals for Alternate Functions in PB7..PB4

Signal Name

PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE OC0/OC1C ENABLE OC1B ENABLE OC1A ENABLE OC2A ENABLE PVOV OC0/OC1C OC1B OC1A OC2A DIEOE PCINT7 • PCIE0 PCINT6 • PCIE0 PCINT5 • PCIE0 PCINT4 • PCIE0 DIEOV 1 1 1 1 DI PCINT7 INPUT PCINT6 INPUT PCINT5 INPUT PCINT4 INPUT AIO – – – –

PB7/PCINT7/OC0A/ OC1C

PB6/PCINT6/OC1BPB5/PCINT5/OC1APB4/PCINT4/OC

Table 10-8. Overriding Signals for Alternate Functions in PB3..PB0

Signal Name

PUOE SPE • MSTR SPE • MSTR PUOV PORTB3 • PUD PORTB2 • PUD PORTB1 • PUD PORTB0 • PUD DDOE SPE • MSTR SPE • MSTR SPE • MSTR SPE • MSTR

PB3/PD0/PCINT3/ MISO

PB2/PDI/PCINT2/ MOSI

PB1/PCINT1/ SCK

SPE • MSTR SPE • MSTR

PB0/PCINT0/ SS

DDOV 0 0 0 0 PVOE SPE • MSTR PVOV SPI SLAVE OUTPUT SPI MSTR OUTPUT SCK OUTPUT 0

DIEOE PCINT3 • PCIE0 PCINT2 • PCIE0

DIEOV 1 1 1 1

AIO – – – –

SPI MSTR INPUT PCINT3 INPUT

AT90USB64/128

SPE • MSTR SPE • MSTR 0

PCINT1 • PCIE0

SPI SLAVE INPUT PCINT2 INPUT

SCK INPUT PCINT1 INPUT

PCINT0 • PCIE0

SPI SS PCINT0 INPUT

7593D–AVR–07/06

10.3.4 Alternate Functions of Port C

The Port C alternate function is as follows:

Table 10-9. Port C Pins Alternate Functions

Port Pin Alternate Function

AT90USB64/128

PC7

PC6

PC5

PC4

PC3

PC2 A10(External Memory interface address bit 10) PC1 A9(External Memory interface address bit 9) PC0 A8(External Memory interface address bit 8)

A15/IC.3/CLKO(External Memory interface address bit 15 or Input Capture Timer 3 or CLK0 (Divided System Clock)

A14/OC.3A(External Memory interface address bit 14 or Output Compare and PWM output A for Timer/Counter3)

A13/OC.3B(External Memory interface address bit 13 or Output Compare and PWM output B for Timer/Counter3)

A12/OC.3C(External Memory interface address bit 12 or Output Compare and PWM output C for Timer/Counter3)

A1 1/T.3(External Memory interface address bit 11or Timer/Counter3 Clok Input)

Table 10-10 and Table 10-11 relate the alternate functions of Port C to the overriding signals

shown in Figure 10-5 on page 79.

Table 10-10. Overriding Signals for Alternate Functions in PC7..PC4

Signal Name

PC7/A15/IC.3/CLK O PC6/A14/OC.3A PC5/A13/OC.3B PC4/A12/OC.3C

SRE •

PUOE SRE • (XMM<1)

PUOV 0 0 0 0 DDOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4) DDOV 1 1 1 1 PVOE SRE • (XMM<1) SRE • (XMM<2) SRE • (XMM<3) SRE • (XMM<4)

PVOV A15

DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI ICP3 input – – – AIO – – – –

(XMM<2)|OC3A enable

if (SRE.XMM<2) then A14

else OC3A

SRE • (XMM<3)|OC3B enable

if (SRE.XMM<2) then A13

else OC3B

SRE • (XMM<4)|OC3C enable

if (SRE.XMM<2) then A12

else OC3C

7593D–AVR–07/06

Table 10-11. Overriding Signals for Alternate Functions in PC3..PC0

Signal Name PC3/A11/T.3 PC2/A10 PC1/A9 PC0/A8

PUOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PUOV0000 DDOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) DDOV 1 1 1 1 PVOE SRE • (XMM<5) SRE • (XMM<6) SRE • (XMM<7) SRE • (XMM<7) PVOV A11 A10 A9 A8 DIEOE0000 DIEOV0000 DI T3 input – – – AIO––––

10.3.5 Alternate Functions of Port D

The Port D pins with alternate functions are shown in Table 10-12.

Table 10-12. Port D Pins Alternate Functions

Port Pin Alternate Functi on

PD7 T0 (Timer/Counter0 Clock Input) PD6 T1 (Timer/Counter1 Clock Input) PD5 XCK1 (USART1 External Clock Input/Output) PD4 ICP1 (Timer/Counter1 Input Capture Trigger) PD3 INT3 PD2 INT2/RXD1

PD1

PD0

/TXD1 (External Interrupt3 Input or USART1 Transmit Pin)

(External Interrupt2 Input or USART1 Receive Pin)

/SDA/OC2B (External Interrupt1 Input or TWI Serial DAta or Output

INT1 Compare for Timer/Counter2)

INT0

/SCL/OC0B (External Interrupt0 Input or TWI Serial CLock or Output

Compare for Timer/Counter0)

The alternate pin configuration is as follows:

• T0 – Port D, Bit 7

T0, Timer/Counter0 counter source.

• T1 – Port D, Bit 6

T1, Timer/Counter1 counter source.

• XCK1 – Port D, Bit 5

XCK1, USART1 External clock. The Data Direction Register (DDD5) controls whether the clock is output (DDD5 set) or input (DDD5 cleared). The XCK1 pin is active only when the USART1 operates in Synchronous mode.

AT90USB64/128

7593D–AVR–07/06

AT90USB64/128

• ICP1 – Port D, Bit 4

ICP1 – Input Capture Pin 1: The PD4 pin can act as an input capture pin for Timer/Counter1.

•INT3

INT3, External Interrupt source 3: The PD3 pin can serve as an external interrupt source to the MCU.

TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3.

•INT2

INT2, External Interrupt source 2. The PD2 pin can serve as an External Interrupt source to the MCU.

RXD1, Receive Data (Data input pin for the USART1). When the USART1 receiver is enabled this pin is configured as an input regardless of the value of DDD2. When the USART forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.

•INT1

INT1, External Interrupt source 1. The PD1 pin can serve as an external interrupt source to the MCU.

SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the 2-wire Serial Interface, pin PD1 is disconnected from the port and becomes the Serial Data I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slewrate limitation.

/TXD1 – Port D, Bit 3

/RXD1 – Port D, Bit 2

/SDA/OC2B – Port D, Bit 1

•INT0

INT0, External Interrupt source 0. The PD0 pin can serve as an external interrupt source to the MCU.

SCL, 2-wire Serial Interface Clock: When the TWEN bit in TWCR is set (one) to enable the 2wire Serial Interface, pin PD0 is disconnected from the port and becomes the Serial Clock I/O pin for the 2-wire Serial Interface. In this mode, there is a spike filter on the pin to suppress spikes shorter than 50 ns on the input signal, and the pin is driven by an open drain driver with slew-rate limitation.

Table 10-13 and Table 10-14 relates the alternate functions of Port D to the overriding sign als

shown in Figure 10-5 on page 79.

/SCL/OC0B – Port D, Bit 0

7593D–AVR–07/06

Table 10-13. Overriding Signals for Alternate Functions PD7..PD4

Signal Name PD7/T0 PD6/T1 PD5/XCK1 PD4/ICP1

PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE 0 0 XCK1 OUTPUT ENABLE 0 DDOV 0 0 1 0 PVOE 0 0 XCK1 OUTPUT ENABLE 0 PVOV 0 0 XCK1 OUTPUT 0 DIEOE 0 0 0 0 DIEOV 0 0 0 0 DI T0 INPUT T1 INPUT XCK1 INPUT ICP1 INPUT AIO – – – –

Table 10-14. Overriding Signals for Alternate Functions in PD3..PD0

(1)

PD1/INT1/SDA/

Signal Name PD3/INT3/TXD1 PD2/INT2/RXD1

PUOE TXEN1 RXEN1 TWEN TWEN PUOV 0 PORTD2 • PUD PORTD1 • PUD PORTD0 • PUD DDOE TXEN1 RXEN1 TWEN TWEN DDOV 1 0 SDA_OUT SCL_OUT

PVOE TXEN1 0

PVOV TXD1 0 OC2B OC0B DIEOE INT3 ENABLE INT2 ENABLE INT1 ENABLE INT0 ENABLE DIEOV 1 1 1 1 DI INT3 INPUT INT2 INPUT/RXD1 INT1 INPUT INT0 INPUT AIO – – SDA INPUT SCL INPUT

Note: 1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0

and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module.

OC2B

TWEN | OC2B ENABLE

PD0/INT0/SCL/ OC0B

TWEN | OC0B ENABLE

AT90USB64/128

7593D–AVR–07/06

10.3.6 Alternate Functions of Port E

The Port E pins with alternate functions are shown in Table 10-15.

Table 10-15. Port E Pins Alternate Functions

Port Pin Alternate Function

PE7

PE6 INT6/AIN.0 (External Interrupt 6 Input or Analog Comparator Positive Input) PE5 INT5/TOSC2 (External Interrupt 5 Input or RTC Oscillator Timer/Counter2)) PE4 INT4/TOSC2 (External Interrupt4 Input or RTC Oscillator Timer/Counter2) PE3 UID PE2 ALE/HWB (Address latch to extenal memory or Hardware bootloader activation)

INT7/AIN.1/UVCON (External Interrupt 7 Input, Analog Comparator Positive Input or VBUS Control)

AT90USB64/128

PE1 RD PE0 WR

(Read strobe to external memory)

(Write strobe to external memory)

• INT7/AIN.1/UVCON – Port E, Bit 7

INT7, External Interrupt source 7: The PE7 pin can serve as an external interrupt source. AIN1 – Analog Comparator Negative input. This pin is dire ctly con nected to the ne gative inpu t of

the Analog Comparator. UVCON - When using USB host mode, this pi n allows to control an external VBUS generator

(active high).

• INT6/AIN.0 – Port E, Bit 6

INT6, External Interrupt source 6: The PE6 pin can serve as an external interrupt source. AIN0 – Analog Comparator Negative input. This pin is dire ctly con nected to the ne gative inpu t of

the Analog Comparator.

• INT5/TOSC2 – Port E, Bit 5

INT5, External Interrupt source 5: The PE5 pin can serve as an External Interrupt source. TOSC2, Timer/Counter2 Oscillator pin1. When the AS2 bit in ASSR is set to enable asynchro-

nous clocking of Timer/Counter2, pin PE5 is disconnected from the port, and becomes the ouput of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin can not be used as an I/O pin.

7593D–AVR–07/06

• INT4/TOSC1 – Port E, Bit 4

INT4, External Interrupt source 4: The PE4 pin can serve as an External Interrupt source. TOSC1, Timer/Counter2 Oscillator pin2. When the AS2 bit in ASSR is set to enable asynchro-

nous clocking of Timer/Counter2, pin PE4 is disconnected from the port, and becomes the input of the inverting Oscillator amplifier. In this mode, a crystal is connected to this pin, and the pin can not be used as an I/O pin.

• UID – Port E, Bit 3

ID pin of the USB bus.

• ALE/HWB – Port E, Bit 2

ALE is the external data memory Address latch enable. HWB allows to execute the bootloader section after reset when tied to ground during external

reset pulse. The HWB mode of this pin is active only when the HWBE fuse is enable.

•RD

– Port E, Bit 1

is the external data memory read control enable.

– Port E, Bit 0

•WR

is the external data memory write control enable.

Table 10-16. Overriding Signals for Alternate Functions PE7..PE4

Signal Name

PUOE 0 0 0 0 PUOV 0 0 0 0 DDOE UVCONE 0 0 0 DDOV UVCONE 0 0 0 PVOE UVCONE 0 0 0 PVOV UVCON 0 0 0 DIEOE INT7 ENABLE INT6 ENABLE INT5 ENABLE INT4 ENABLE DIEOV 1 1 1 1 DI INT7 INPUT INT6 INPUT INT5 INPUT INT4 INPUT AIO AIN1 INPUT AIN0 INPUT – –

PE7/INT7/AIN.1/ UVCON PE6/INT6/AIN.0

PE5/INT5/ TOSC1

PE4/INT4/ TOSC2

Table 10-17. Overriding Signals for Alternate Functions in PE3..PE0

Signal Name PE3/UID PE2/ALE/HWB PE1/RD PE0/WR

PUOE UIDE 0 SRE SRE PUOV 1 0 0 0 DDOE UIDE SRE SRE SRE

DDOV 0 1 1 0 PVOE 0 SRE SRE SRE PVOV 0 ALE RD WR DIEOE UIDE 0 0 0 DIEOV 1 0 0 1 DI UID HWB – – PE0 0 0 0 0 AIO – – – –

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10.3.7 Alternate Functions of Port F

The Port F has an alternate function as analog input for the ADC as shown in Table 10-18. If some Port F pins are configured as outputs, it is essential that these do not switch when a conversion is in progress. This might corrupt the result of the conversion. If the JTAG interface is enabled, the pull-up resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a Reset occurs.

Table 10-18. Port F Pins Alternate Functions

Port Pin Alternate Function

PF7 ADC7/TDI (ADC input channel 7 or JTAG Test Data Input) PF6 ADC6/TDO (ADC input channel 6 or JTAG Test Data Output) PF5 ADC5/TMS (ADC input channel 5 or JTAG Test Mode Select) PF4 ADC4/TCK (ADC input channel 4 or JTAG Test ClocK) PF3 ADC3 (ADC input channel 3) PF2 ADC2 (ADC input channel 2) PF1 ADC1 (ADC input channel 1) PF0 ADC0 (ADC input channel 0)

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• TDI, ADC7 – Port F, Bit 7

ADC7, Analog to Digital Converter, Channel 7

TDI, JTAG Test Data In: Serial input data to be shifted in to the Instruction Register or Data Register (scan chains). When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TDO, ADC6 – Port F, Bit 6

ADC6, Analog to Digital Converter, Channel 6

TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

The TDO pin is tri-stated unless TAP states that shift out data are entered.

• TMS, ADC5 – Port F, Bit 5

ADC5, Analog to Digital Converter, Channel 5

TMS, JTAG Test Mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

• TCK, ADC4 – Port F, Bit 4

ADC4, Analog to Digital Converter, Channel 4

TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin.

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• ADC3 – ADC0 – Port F, Bit 3..0

Analog to Digital Converter, Channel 3..0.

Table 10-19. Overriding Signals for Alternate Functions in PF7..PF4

Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK

PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 1 0 1 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN

DDOV 0

PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 0 0 0 0 DI – – – –

SHIFT_IR + SHIFT_DR

AIO TDI/ADC7 INPUT ADC6 INPUT

Table 10-20. Overriding Signals for Alternate Functions in PF3..PF0

Signal Name PF3/ADC3 PF2/ADC2 PF1/ADC1 PF0/ADC0

PUOE0000 PUOV0000 DDOE 0 0 0 0 DDOV 0 0 0 0 PVOE 0 0 0 0 PVOV 0 0 0 0 DIEOE0000 DIEOV0000 DI–––– AIO ADC3 INPUT ADC2 INPUT ADC1 INPUT ADC0 INPUT

10.4 Register Description for I/O-Ports

10.4.1 Port A Data Register – PORTA

Bit 76543210

PORTA7PORTA6PORTA5PORTA4PORTA3PORTA2PORTA1PORTA0PORTA

TMS/ADC5 INPUT

TCK/ADC4 INPUT

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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10.4.2 Port A Data Direction Register – DDRA

Bit 76543210

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.3 Port A Input Pins Address – PINA

Bit 76543210

PINA7 PINA6 PINA5 PINA4 PINA3 PINA2 PINA1 PINA0 PINA

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

10.4.4 Port B Data Register – PORTB

Bit 76543210

PORTB7PORTB6PORTB5PORTB4PORTB3PORTB2PORTB1PORTB0PORTB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.5 Port B Data Direction Register – DDRB

Bit 76543210

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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10.4.6 Port B Input Pins Address – PINB

Bit 76543210

PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 PINB

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

10.4.7 Port C Data Register – PORTC

Bit 76543210

PORTC7PORTC6PORTC5PORTC4PORTC3PORTC2PORTC1PORTC0PORTC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.8 Port C Data Direction Register – DDRC

Bit 76543210

DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 DDRC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.9 Port C Input Pins Address – PINC

Bit 76543210

PINC7 PINC6 PINC5 PINC4 PINC3 PINC2 PINC1 PINC0 PINC

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

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10.4.10 Port D Data Register – PORTD

Bit 76543210

PORTD7PORTD6PORTD5PORTD4PORTD3PORTD2PORTD1PORTD0PORTD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.11 Port D Data Direction Register – DDRD

Bit 76543210

DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 DDRD

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.12 Port D Input Pins Address – PIND

Bit 76543210

PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 PIND

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

10.4.13 Port E Data Register – PORTE

Bit 76543210

PORTE7PORTE6PORTE5PORTE4PORTE3PORTE2PORTE1PORTE0PORTE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.14 Port E Data Direction Register – DDRE

Bit 76543210

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 DDE1 DDE0 DDRE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.15 Port E Input Pins Address – PINE

Bit 76543210

PINE7 PINE6 PINE5 PINE4 PINE3 PINE2 PINE1 PINE0 PINE

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

10.4.16 Port F Data Register – PORTF

Bit 76543210

PORTF7PORTF6PORTF5PORTF4PORTF3PORTF2PORTF1PORTF0PORTF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

10.4.17 Port F Data Direction Regist er – DDRF

Bit 76543210

DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 DDRF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

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10.4.18 Port F Input Pins Address – PINF

Bit 76543210

PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value N/A N/A N/A N/A N/A N/A N/A N/A

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11. External Interrupts

The External Interrupts are triggered by the INT7:0 pin or any of the PCINT23..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT7:0 or PCINT23..0 pins are configured as outputs. This feature provides a way of generating a software interrupt.

The Pin change interrupt PCI0 will trigger if any enabled PCINT7:0 pin toggles. PCMSK0 Register control which pins contribute to the pin change interrupts. Pin change interrupts on PCINT7 ..0 are detected asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode.

The External Interrupts can be triggered by a falling or rising edge or a low level. This is set up as indicated in the specification for the External Interrupt Control Registers – EICRA (INT3:0) and EICRB (INT7:4). When the external interrupt is enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held low. Note that recognition of falling or rising edge interrupts on INT7:4 requires the presence of an I/O clock, described in “System Clock and

Clock Options” on page 39. Low level interrupts and the edge interrupt on INT3:0 are detected

asynchronously. This implies that these interrupts can be used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power -down, the required level must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still wake up, but no interrupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described in “System Clock and Clock Options” on page 39.

11.0.1 External Interrupt Control Register A – EICRA

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit 76543210

ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 EICRA

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value00000000

• Bits 7..0 – ISC31, ISC30 – ISC00, ISC00: External Interrupt 3 - 0 Sense Control Bits

The External Interrupts 3 - 0 are activated by the external pins INT3:0 if the SREG I-flag and the corresponding interrupt mask in the EI MS K is set. Th e leve l and edg es on the e xtern al pins that activate the interrupts are defined in Table 11-1. Edges on INT3..INT0 are registered asynchronously. Pulses on INT3:0 pins wider than the minimum pulse width given in Table 11-2 will generate an interrupt. Shorter pulses are not gu aranteed to generate an interr upt. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low. When changing the ISCn bit, an interrupt can occur. Therefore, it is recommended to first disable INTn by clearing its In terrupt Enable bit in the EIMSK Register. Then, the ISCn bit can be changed. Finally, the INTn interrupt flag should be cleared by writing a logical one to its Interrupt Flag bit (INTFn) in the EIFR Registe r before the interrupt is re-enabled.

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Table 11-1. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request. 0 1 Any edge of INTn generates asynchronously an interrupt request. 1 0 The falling edge of INTn generates asynchronously an interrupt request. 1 1 The rising edge of INTn generates asynchronously an interrupt request.

Note: 1. n = 3, 2, 1or 0.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Table 11-2. Asynchronous External Interrupt Characteristics

Symbol Parameter Condition Min Typ Max Units

INT

Minimum pulse width for asynchronous external interrupt

11.0.2 External Interrupt Control Register B – EICRB

Bit 76543210

ISC71 ISC70 ISC61 ISC60 ISC51 ISC50 ISC41 ISC40 EICRB

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value00000000

(1)

50 ns

• Bits 7..0 – ISC71, ISC70 - ISC41, ISC40: External Int errupt 7 - 4 Sense Control Bits

The External Interrupts 7 - 4 are activated by the external pins INT7:4 if the SREG I-flag and the corresponding interrupt mask in the EI MS K is set. Th e leve l and edg es on the e xtern al pins that activate the interrupts are defined in Table 11-3. The value on the INT7:4 pins are sampled before detecting edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. Observe that CPU clock frequency can be lower than the XTAL frequency if the XTAL divider is enabled. If low level interrupt is selected, the low level must be held until the completion of the currently executing instruction to generate an interrupt. If enabled, a level triggered interrupt will generate an interrupt request as long as the pin is held low.

Table 11-3. Interrupt Sense Control

ISCn1 ISCn0 Description

0 0 The low level of INTn generates an interrupt request. 0 1 Any logical change on INTn generates an interrupt request

Note: 1. n = 7, 6, 5 or 4.

When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed.

The falling edge between two samples of INTn generates an interrupt request.

The rising edge between two samples of INTn generates an interrupt request.

(1)

11.0.3 External Interrupt Mask Register – EIMSK

Bit 76543210

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INT7 INT6 INT5 INT4 INT3 INT2 INT1 IINT0 EIMSK

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value00000000

• Bits 7..0 – INT7 – INT0: External Interrupt Request 7 - 0 Enable

When an INT7 – INT0 bit is written to one and the I-bit in the Status Register (SREG) is set (one), the corresponding external pin interrupt is enabled. The Interrupt Sense Control bits in the External Interrupt Control Registers – EICRA and EICRB – defines whether the external interrupt is activated on rising or falling edge or level sensed. Activity on any of these pins will trigger an interrupt request even if the pin is enabled as an output. This provides a way of generating a software interrupt.

11.0.4 External Interrupt Flag Register – EIFR

Bit 76543210

INTF7 INTF6 INTF5 INTF4 INTF3 INTF2 INTF1 IINTF0 EIFR

Read/Write R/W R/W R/W R/W R/W R/W R/W R /W Initial Value00000000

• Bits 7..0 – INTF7 - INTF0: External Interrupt Flags 7 - 0

When an edge or logic change on the INT7:0 pin tri ggers an interrupt requ est, INTF 7:0 becomes set (one). If the I-bit in SREG and the corresponding interrupt enable bit, INT7:0 in EIMSK, are set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical o ne to it. Thes e flags are always cleared when INT7:0 are configured as level interrupt. Note that when entering sleep mode with the INT3:0 interrupts disabled, the input buffers on these pins will be disabled. This may cause a logic change in internal signals which will set the INTF3:0 flags. See “Digital Input

Enable and Sleep Modes” on page 78 for more information.

11.0.5 Pin Change Interrupt Control Register - PCICR

Bit 76543210

– – – – –PCIE0PCICR

Read/WriteRRRRRRRR/W Initial Value 0 0 0 0 0 0 0 0

• Bit 0 – PCIE0: Pin Change Interrupt Enable 0 When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an

interrupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Registe r.

11.0.6 Pin Change Interrupt Flag Register – PCIFR

Bit 76543210

– – – – –PCIF0PCIFR

Read/WriteRRRRRRRR/W Initial Value 0 0 0 0 0 0 0 0

• Bit 0 – PCIF0: Pin Change Interrupt Flag 0

When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set (one). If the I-bit in SREG and the PCIE0 bit in EIMSK are set (one), the MCU will jump to the

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corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it.

11.0.7 Pin Change Mask Register 0 – PCMSK0

Bit 76543210

PCINT7 PCIN T6 PCINT5 PCINT4 PCINT3 PCINT2 PCINT1 PCINT0 PCMSK0

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0

• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0

Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled.

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12. Timer/Counter0, Timer/Counter1, and Timer/Counter3 Prescalers

Timer/Counter0, 1, and 3 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to all Timer/Counters. Tn is used as a general name, n = 0, 1 or 3.

12.1 Internal Clock Source

The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system clock frequency (f clock source. The prescaled clock has a frequency of either f f

12.2 Prescaler Reset

The prescaler is free running, i.e., operates independently o f the Clock Select logic of the Timer/Counter, and it is shared by the Timer/Counter Tn. Since the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will have implications for situations where a prescaled clock is used. One example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The numbe r of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).

It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execution. However, care must be taken if the other Timer/Counter that shares the same prescaler also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is connected to.

CLK_I/O

/1024.

). Alternatively, one of four taps from the prescaler can be used as a

CLK_I/O

/8, f

CLK_I/O

/64, f

CLK_I/O

/256, or

12.3 External Clock Source

An external clock source applied to the Tn pin can be used as Timer/Counter clock (clkTn). The Tn pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then passed through the edge detector. Figure 1 shows a functional equivalent block diagram of the Tn synchronization and edge detector logic. The registers are clocked at the positive edge of the internal system clock ( high period of the internal system clock.

The edge detector generates one clk = 6) edge it detects.

Figure 1. Tn/T0 Pin Sampling

clk

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles from an edge has been applied to the Tn pin to the counter is updated.

Enabling and disabling of the clock input must be done when Tn has been stable for at least one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is generated.

clk

). The latch is transparent in the

I/O

pulse for each positive (CSn2:0 = 7) or ne gative (CSn2 :0

DQDQ

I/O

Edge DetectorSynchronization

Tn_sync

(To Clock Select Logic)

100

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ATMEL AT90USB646, AT90USB647, AT90USB1286, AT90USB1287 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

1. Pin Configurations

1.1 Disclaimer

2. Overview

2.1 Block Diagram

2.2 Pin Descriptions

2.2.1 VCC

2.2.2 GND

2.2.3 Port A (PA7..PA0)

2.2.4 Port B (PB7..PB0)

2.2.5 Port C (PC7..PC0)

2.2.6 Port D (PD7..PD0)

2.2.7 Port E (PE7..PE0)

2.2.8 Port F (PF7..PF0)

2.2.9 D-

2.2.10 D+

2.2.11 UGND

2.2.12 UVCC

2.2.13 UCAP

2.2.14 VBUS

2.2.16 XTAL1

2.2.17 XTAL2

2.2.18 AVCC

2.2.19 AREF

RESET

3. About Code Examples

4. AVR CPU Core

4.1 Introduction

4.2 Architectural Overview

4.4 Status Register

4.5 General Purpose Register File

4.5.1 The X-register, Y-register, and Z-register

4.6 Stack Pointer

4.6.1 Extended Z-pointer Register for ELPM/SPM - RAMPZ

4.7 Instruction Execution Timing

4.8 Reset and Interrupt Handling

4.8.1 Interrupt Response Time

5. AVR AT90USB64/128 Memories

5.1 In-System Reprogrammable Flash Program Memory

5.2 SRAM Data Memory

5.2.1 Data Memory Access Times

5.3 EEPROM Data Memory

5.3.1 EEPROM Read/Write Access

5.3.5 Preventing EEPROM Corruption

5.4 I/O Memory

5.4.1 General Purpose I/O Registers

5.5 External Memory Interface

5.5.1 Overview

5.5.2 Using the External Memory Interface

5.5.3 Address Latch Requirements

5.5.4 Pull-up and Bus-keeper

5.5.5 Timing

5.5.8 Using all Locations of External Memory Smaller than 64 KB

5.5.9 Using all 64KB Locations of External Memory

6. System Clock and Clock Options

6.1 Clock Systems and their Distribution

6.2 Clock Sources

6.2.1 Default Clock Source

6.2.2 Clock Startup Sequence

6.3 Low Power Crystal Oscillator

6.4 Low Frequency Crystal Oscillator

6.5 Calibrated Internal RC Oscillator

6.6 128 kHz Internal Oscillator

6.7 External Clock

6.8 Clock Output Buffer

6.9 Timer/Counter Oscillator

6.10 System Clock Prescaler

6.1 1 PLL

6.11.1 Internal PLL for USB interface

7. Power Management and Sleep Modes

7.1 Idle Mode

7.2 ADC Noise Reduction Mode

7.3 Power-down Mode

7.4 Power-save Mode

7.5 Standby Mode

7.6 Extended Standby Mode