BDTIC www.bdtic.com/ATMEL
Features
• High Performance, Low Power AVR ® 8-bit Microcontroller
• Advanced RISC Architecture
– 131 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 1 MIPS throughput per MHz
– On-chip 2-cycle Multiplier
• Data and Non-Volatile Program Memory
– 8K Bytes Flash of In-System Programmable Program Memory
• Endurance: 10,000 Write/Erase Cycles
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– 512 Bytes of In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512 Bytes Internal SRAM
– Programming Lock for Flash Program and EEPROM Data Security
• On Chip Debug Interface (debugWIRE)
• Peripheral Features
– Two 12-bit High Speed PSC (Power Stage Controllers) with 4-bit Resolution
Enhancement
• Non Overlapping Inverted PWM Output Pins With Flexible Dead-Time
• Variable PWM duty Cycle and Frequency
• Synchronous Update of all PWM Registers
• Auto Stop Function for Event Driven PFC Implementation
• Less than 25 Hz Step Width at 150 kHz Output Frequency
• PSC2 with four Output Pins and Output Matrix
– One 8-bit General purpose Timer/Counter with Separate Prescaler and Capture
Mode
– One 16-bit General purpose Timer/Counter with Separate Prescaler, Compare
Mode and Capture Mode
– Master/Slave SPI Serial Interface
– 10-bit ADC
• 8 Single Ended Channels and 1 Fully Differential ADC Channel Pair
• Programmable Gain (5x, 10x, 20x, 40x on Differential Channel)
• Internal Reference Voltage
– Two Analog Comparator with Resistor-Array to Adjust Comparison Voltage
– 4 External Interrupts
– Programmable Watchdog Timer with Separate On-Chip Oscillator
• Special Microcontroller Features
– Low Power Idle, Noise Reduction, and Power Down Modes
– Power On Reset and Programmable Brown Out Detection
– Flag Array in Bit-programmable I/O Space (4 bytes)
– In-System Programmable via SPI Port
– Internal Calibrated RC Oscillator ( 8 MHz)
– On-chip PLL for fast PWM ( 32 MHz, 64 MHz) and CPU (16 MHz)
8-bit
Microcontroller
with 8K Bytes
In-System
Programmable
Flash
AT90PWM1
Summary
4378BS–AVR–05/08
•
Operating Voltage: 2.7V - 5.5V
•
Extended Operating Temperature:
– -40°C to +105°
1. History
Product Revision
AT90PWM1 First revision of parts
2. Disclaimer
Typical values contained in this datasheet are based on simulations and characterization of
other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
3. Pin Configurations
Figure 3-1. SOIC 24-pin Package
2
AT90PWM1
4378BS–AVR–05/08
Figure 3-2. QFN 32 -pin Package
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(PSCIN2/OC1A/MISO_A) PD2
(OC0A/SS/MOSI_A) PD3
NC
VCC
GND
NC
NC
(MISO/PSCOUT20) PB0
PB4 (AMP0+)
PB3 (AMP0-)
NC
AREF
AGND
AVCC
NC
NC
32313029282726
25
9
10111213141516
(MOSI/PSCOUT21) PB1
(OC0B/XTAL1) PE1
(ADC0/XTAL2) PE2
(ADC2/ACMP2 ) PD5
(ADC3/ACMPM/INT0) PD6
(ACMP0) PD7
(ADC5/INT1) PB2
PD1
(PSCIN0/CLKO)
PE0
(RESET/OCD)
NC
PD0
(PSCOUT00/SS_A)
PB7 (ADC4/PSCOUT01/SCK)
PB6 (ADC7/ICP1B)
PB5 (ADC6/INT2)
NC
AT90PWM1 QFN 32
AT90PWM1
4378BS–AVR–05/08
3
3.1 Pin Descriptions
:
Table 3-1. Pin out description
S024 Pin Number Mnemonic Type Name, Function & Alternate Function
7 GND Power Ground: 0V reference
18 AGND Power Analog Ground: 0V reference for analog part
6 VCC power Power Supply:
17 AVCC Power
19 AREF Power
8 PBO I/O
9 PB1 I/O
16 PB2 I/O
20 PB3 I/O AMP0- (Analog Differential Amplifier 0 Input Channel )
21 PB4 I/O AMP0+ (Analog Differential Amplifier 0 Input Channel )
22 PB5 I/O
23 PB6 I/O
24 PB7 I/O
Analog Power Supply: This is the power supply voltage for analog part
For a normal use this pin must be connected.
Analog Reference : reference for analog converter . This is the reference voltage of the
A/D converter. As output, can be used by external analog
MISO (SPI Master In Slave Out)
PSCOUT20 output
MOSI (SPI Master Out Slave In)
PSCOUT21 output
ADC5 (Analog Input Channel5 )
INT1
ADC6 (Analog Input Channel 6)
INT 2
ADC7 (Analog Input Channel 7)
ICP1B (Timer 1 input capture alternate input)
PSCOUT11 output (see note 1)
PSCOUT01 output
ADC4 (Analog Input Channel 4)
SCK (SPI Clock)
PSCOUT00 output
1 PD0 I/O
3 PD1 I/O
4 PD2 I/O
5 PD3 I/O
4
AT90PWM1
XCK (UART Transfer Clock)
SS_A (Alternate SPI Slave Select)
PSCIN0 (PSC 0 Digital Input )
CLKO (System Clock Output)
PSCIN2 (PSC 2 Digital Input)
OC1A (Timer 1 Output Compare A)
MISO_A (Programming & alternate SPI Master In Slave Out)
TXD (Dali/UART Tx data)
OC0A (Timer 0 Output Compare A)
SS (SPI Slave Select)
MOSI_A (Programming & alternate Master Out SPI Slave In)
4378BS–AVR–05/08
Table 3-1. Pin out description (Continued)
S024 Pin Number Mnemonic Type Name, Function & Alternate Function
ADC1 (Analog Input Channel 1)
12 PD4 I/O
RXD (Dali/UART Rx data)
ICP1A (Timer 1 input capture)
SCK_A (Programming & alternate SPI Clock)
AT90PWM1
13 PD5 I/O
14 PD6 I/O
15 PD7 I/O ACMP0 (Analog Comparator 0 Positive Input )
2 PE0 I/O or I
10 PE1 I/O
11 PE2 I/O
4. Overview
ADC2 (Analog Input Channel 2)
ACMP2 (Analog Comparator 2 Positive Input )
ADC3 (Analog Input Channel 3 )
ACMPM reference for analog comparators
INT0
RESET (Reset Input)
OCD (On Chip Debug I/O)
XTAL1: XTAL Input
OC0B (Timer 0 Output Compare B)
XTAL2: XTAL OuTput
ADC0 (Analog Input Channel 0)
The AT90PWM1 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the AT90PWM1 achieves
throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.
4378BS–AVR–05/08
5
4.1 Block Diagram
Figure 4-1. Block Diagram
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The AT90PWM1 provides the following features: 8K bytes of In-System Programmable Flash
with Read-While-Write capabilities, 512 bytes EEPROM, 512 bytes SRAM, 53 general purpose
I/O lines, 32 general purpose working registers, 2 Power Stage Controllers, two flexible
Timer/Counters with compare modes and PWM, an 8-channel 10-bit ADC with two differential
6
AT90PWM1
4378BS–AVR–05/08
AT90PWM1
input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator,
an SPI serial port, an On-chip Debug system and four software selectable power saving modes.
The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI ports and interrupt
system to continue functioning. The Power-down mode saves the register contents but freezes
the Oscillator, disabling all other chip functions until the next interrupt or Hardware Reset. The
ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running
while the rest of the device is sleeping. This allows very fast start-up combined with low power
consumption.
The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial
interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program
running on the AVR core. The boot program can use any interface to download the application
program in the application Flash memory. Software in the Boot Flash section will continue to run
while the Application Flash section is updated, providing true Read-While-Write operation. By
combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,
the Atmel AT90PWM1 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.
The AT90PWM1 AVR is supported with a full suite of program and system development tools
including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators,
and evaluation kits.
4.2 Pin Descriptions
4.2.1 VCC
Digital supply voltage.
4.2.2 GND
Ground.
4.2.3 Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the AT90PWM1 as listed on page
65.
4.2.4 Port D (PD7..PD0)
Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port D output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
4378BS–AVR–05/08
Port D also serves the functions of various special features of the AT90PWM1 as listed on page
68.
7
4.2.5 Port E (PE2..0) RESET/ XTAL1/ XTAL2
Port E is an 3-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port E output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port E pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
If the RSTDISBL Fuse is programmed, PE0 is used as an I/O pin. Note that the electrical characteristics of PE0 differ from those of the other pins of Port C.
If the RSTDISBL Fuse is unprogrammed, PE0 is used as a Reset input. A low level on this pin
for longer than the minimum pulse length will generate a Reset, even if the clock is not running.
The minimum pulse length is given in Table 9-1 on page 43. Shorter pulses are not guaranteed
to generate a Reset.
Depending on the clock selection fuse settings, PE1 can be used as input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
Depending on the clock selection fuse settings, PE2 can be used as output from the inverting
Oscillator amplifier.
The various special features of Port E are elaborated in “Alternate Functions of Port E” on page
71 and “Clock Systems and their Distribution” on page 27.
4.2.6 AVCC
AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to V
through a low-pass filter.
4.2.7 AREF
This is the analog reference pin for the A/D Converter.
4.3 About Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.
CC
8
AT90PWM1
4378BS–AVR–05/08
AT90PWM1
5. Register Summary
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xFF) PICR2H page 162
(0xFE) PICR2L page 162
(0xFD) PFRC2B PCAE2B PISEL2B PELEV2B PFLTE2B PRFM2B3 PRFM2B2 PRFM2B1 PRFM2B0 page 161
(0xFC) PFRC2A PCAE2A PISEL2A PELEV2A PFLTE2A PRFM2A3 PRFM2A2 PRFM2A1 PRFM2A0 page 161
(0xFB) PCTL2 PPRE21 PPRE20 PBFM2 PAOC2B PAOC2A PARUN2 PCCYC2 PRUN2 page 160
(0xFA) PCNF2 PFIFTY2 PALOCK2 PLOCK2 PMODE21 PMODE20 POP2 PCLKSEL2 POME2 page 157
(0xF9) OCR2RBH page 157
(0xF8) OCR2RBL page 157
(0xF7) OCR2SBH page 157
(0xF6) OCR2SBL page 157
(0xF5) OCR2RAH page 156
(0xF4) OCR2RAL page 156
(0xF3) OCR2SAH page 156
(0xF2) OCR2SAL page 156
(0xF1) POM2 POMV2B3 POMV2B2 POMV2B1 POMV2B0 POMV2A3 POMV2A2 POMV2A1 POMV2A0 page 163
(0xF0) PSOC2 POS23 POS22 PSYNC21 PSYNC20
(0xEF) PICR1H
(0xEE) PICR1L
(0xED) PFRC1B PCAE1B PISEL1B PELEV1B PFLTE1B PRFM1B3 PRFM1B2 PRFM1B1 PRFM1B0 page 161
(0xEC) PFRC1A PCAE1A PISEL1A PELEV1A PFLTE1A PRFM1A3 PRFM1A2 PRFM1A1 PRFM1A0 page 161
(0xEB) PCTL1 PRUN1 page 160
(0xEA) Reserved – – – – – – – –
(0xE9) Reserved – – – – – – – –
(0xE8) Reserved – – – – – – – –
(0xE7) Reserved – – – – – – – –
(0xE6) Reserved – – – – – – – –
(0xE5) Reserved – – – – – – – –
(0xE4) Reserved – – – – – – – –
(0xE3) Reserved – – – – – – – –
(0xE2) Reserved – – – – – – – –
(0xE1) Reserved – – – – – – – –
(0xE0) PSOC1 – – PSYNC11 PSYNC10 – POEN1B – POEN1A
(0xDF) PICR0H page 162
(0xDE) PICR0L page 162
(0xDD) PFRC0B PCAE0B PISEL0B PELEV0B PFLTE0B PRFM0B3 PRFM0B2 PRFM0B1 PRFM0B0 page 161
(0xDC) PFRC0A PCAE0A PISEL0A PELEV0A PFLTE0A PRFM0A3 PRFM0A2 PRFM0A1 PRFM0A0 page 161
(0xDB) PCTL0 PPRE01 PPRE00 PBFM0 PAOC0B PAOC0A PARUN0 PCCYC0 PRUN0 page 158
(0xDA) PCNF0 PFIFTY0 PALOCK0 PLOCK0 PMODE01 PMODE00 POP0 PCLKSEL0 - page 157
(0xD9) OCR0RBH page 157
(0xD8) OCR0RBL page 157
(0xD7) OCR0SBH page 157
(0xD6) OCR0SBL page 157
(0xD5) OCR0RAH page 156
(0xD4) OCR0RAL page 156
(0xD3) OCR0SAH page 156
(0xD2) OCR0SAL page 156
(0xD1) Reserved – – – – – – – –
(0xD0) PSOC0 – – PSYNC01 PSYNC00 – POEN0B – POEN0A page 155
(0xCF) Reserved – – – – – – – –
(0xCE) Reserved – – – – – – – –
(0xCD) Reserved – – – – – – – –
(0xCC) Reserved – – – – – – – –
(0xCB) Reserved – – – – – – – –
(0xCA) Reserved – – – – – – – –
(0xC9) Reserved – – – – – – – –
(0xC8) Reserved – – – – – – – –
(0xC7) Reserved – – – – – – – –
(0xC6) Reserved – – – – – – – –
(0xC5) Reserved – – – – – – – –
(0xC4) Reserved – – – – – – – –
(0xC3) Reserved – – – – – – – –
(0xC2) Reserved – – – – – – – –
(0xC1) Reserved – – – – – – – –
(0xC0) Reserved – – – – – – – –
(0xBF) Reserved – – – – – – – –
POEN2D
POEN2B
POEN2C
POEN2A page 155
4378BS–AVR–05/08
9
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0xBE) Reserved – – – – – – – –
(0xBD) Reserved – – – – – – – –
(0xBC) Reserved – – – – – – – –
(0xBB) Reserved – – – – – – – –
(0xBA) Reserved – – – – – – – –
(0xB9) Reserved – – – – – – – –
(0xB8) Reserved – – – – – – – –
(0xB7) Reserved – – – – – – – –
(0xB6) Reserved – – – – – – – –
(0xB5) Reserved – – – – – – – –
(0xB4) Reserved – – – – – – – –
(0xB3) Reserved – – – – – – – –
(0xB2) Reserved – – – – – – – –
(0xB1) Reserved – – – – – – – –
(0xB0) Reserved – – – – – – – –
(0xAF) AC2CON AC2EN AC2IE AC2IS1 A C2IS0 AC2SADE- AC2M2 AC2M1 AC2M0 page 178
(0xAD) AC0CON AC0EN AC0IE AC0IS1 AC0IS0 - AC0M2 AC0M1 AC0M0 page 177
(0xAC) Reserved – – – – – – – – page 258
(0xAB) Reserved – – – – – – – – page 258
(0xAA) Reserved – – – – – – – – page 257
(0xA9) Reserved – – – – – – – –
(0xA8) Reserved – – – – – – – –
(0xA7) Reserved – – – – – – – –
(0xA6) Reserved – – – – – – – –
(0xA5) PIM2
(0xA4) PIFR2
(0xA3) Reserved – – – – – – – –
(0xA2) Reserved – – – – – – – –
(0xA1) PIM0
(0xA0) PIFR0
(0x9F) Reserved – – – – – – – –
(0x9E) Reserved – – – – – – – –
(0x9D) Reserved – – – – – – – –
(0x9C) Reserved – – – – – – – –
(0x9B) Reserved – – – – – – – –
(0x9A) Reserved – – – – – – – –
(0x99) Reserved – – – – – – – –
(0x98) Reserved – – – – – – – –
(0x97) Reserved – – – – – – – –
(0x96) Reserved – – – – – – – –
(0x95) Reserved – – – – – – – –
(0x94) Reserved – – – – – – – –
(0x93) Reserved – – – – – – – –
(0x92) Reserved – – – – – – – –
(0x91) Reserved – – – – – – – –
(0x90) Reserved – – – – – – – –
(0x8F) Reserved – – – – – – – –
(0x8E) Reserved – – – – – – – –
(0x8D) Reserved – – – – – – – –
(0x8C) Reserved – – – – – – – –
(0x8B) OCR1BH OCR1B15 OCR1B14 OCR1B13 OCR1B12 OCR1B11 OCR1B10 OCR1B9 OCR1B8 page 120
(0x8A) OCR1BL OCR1B7 OCR1B6 OCR1B5 OCR1B4 OCR1B3 OCR1B2 OCR1B1 OCR1B0 page 120
(0x89) OCR1AH OCR1A15 OCR1A14 OCR1A13 OCR1A12 OCR1A11 OCR1A10 OCR1A9 OCR1A8 page 120
(0x88) OCR1AL OCR1A7 OCR1A6 OCR1A5 OCR1A4 OCR1A3 OCR1A2 OCR1A1 OCR1A0 page 120
(0x87) ICR1H ICR115 ICR114 ICR113 ICR112 ICR111 ICR110 ICR19 ICR18 page 121
(0x86) ICR1L ICR17 ICR16 ICR15 ICR14 ICR13 ICR12 ICR11 ICR10 page 121
(0x85) TCNT1H TCNT115 TCNT114 TCNT113 TCNT112 TCNT111 TCNT110 TCNT19 TCNT18 page 120
(0x84) TCNT1L TCNT17 TCNT16 TCNT15 TCNT14 TCNT13 TCNT12 TCNT11 TCNT10 page 120
(0x83) Reserved – – – – – – – –
(0x82) TCCR1C FOC1A FOC1B – – – – – – page 119
(0x81) TCCR1B ICNC1 ICES1 – WGM13 WGM12 CS12 CS11 CS10 page 118
(0x80) TCCR1A COM1A1 COM1A0 COM1B1 COM1B0 – – WGM11 WGM10 page 116
(0x7F) DIDR1 – – ACMP0D AMP0PD AMP0ND
(0x7E) DIDR0 ADC7D ADC6D ADC5D ADC4D
(0x7D) Reserved – – – – – – – –
- - PSEIE2 PEVE2B PEVE2A - - PEOPE2
- - PSEI2 PEV2B PEV2A PRN21 PRN20 PEOP2
- - PSEIE0 PEVE0B PEVE0A - - PEOPE0
- - PSEI0 PEV0B PEV0A PRN01 PRN00 PEOP0
ADC3D/ACMPMD ADC2D/ACMP2D
ADC10D/ACMP1D ADC9D/AMP1PD ADC8D/AMP1ND
ADC1D ADC0D page 199
page 164
page 164
page 164
page 164
page 199
10
AT90PWM1
4378BS–AVR–05/08
AT90PWM1
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
(0x7C) ADMUX REFS1 RE FS0 ADLAR – MUX3 MUX2 MUX1 MUX0 page 194
(0x7B) ADCSRB ADHSM – – ADASCR ADTS3 ADTS2 A DTS1 ADTS0 page 196
(0x7A) ADCSRA ADEN ADSC ADATE ADIF ADIE ADPS2 ADPS1 ADPS0 page 195
(0x79) ADCH - / ADC9 - / ADC8 - / ADC7 - / ADC6 - / ADC5 - / ADC4 ADC9 / ADC3 ADC8 / ADC2 page 198
(0x78) ADCL ADC7 / ADC1 ADC6 / ADC0 ADC5 / - ADC4 / - ADC3 / - ADC2 / - ADC1 / - ADC0 / page 198
(0x77)
(0x76) AMP0CSR AMP0EN - AMP0G1 AMP0G0 - AMP0TS2 AMP0TS1 AMP0TS0 page 202
(0x75) Reserved – – – – – – – –
(0x74) Reserved – – – – – – – –
(0x73) Reserved – – – – – – – –
(0x72) Reserved – – – – – – – –
(0x71) Reserved – – – – – – – –
(0x70) Reserved – – – – – – – –
(0x6F) TIMSK1 – – ICIE1 – – OCIE1B OCIE1A TOIE1 page 121
(0x6E) TIMSK0 – – – – – OCIE0B OCIE0A TOIE0 page 94
(0x6D) Reserved – – – – – – – –
(0x6C) Reserved – – – – – – – –
(0x6B) Reserved – – – – – – – –
(0x6A) Reserved – – – – – – – –
(0x69) EICRA ISC31 ISC30 ISC21 ISC20 ISC11 ISC10 ISC01 ISC00 page 74
(0x68) Reserved – – – – – – – –
(0x67) Reserved – – – – – – – –
(0x66) OSCCAL – CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 page 31
(0x65) Reserved – – – – – – – –
(0x64) PRR PRPSC2 PRPSC1 PRPSC0 PRTIM1 PRTIM0 PRSPI – PRADC page 39
(0x63) Reserved – – – – – – – –
(0x62) Reserved – – – – – – – –
(0x61) CLKPR CLKPCE – – – CLKPS3 CLKPS2 CLKPS1 CLKPS0 page 35
(0x60) WDTCSR WDIF WDIE WDP3 WDCE WDE WDP2 WDP1 WDP0 page 50
0x3F (0x5F) SREG I T H S V N Z C page 11
0x3E (0x5E) SPH SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 page 13
0x3D (0x5D) SPL SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 page 13
0x3C (0x5C) Reserved – – – – – – – –
0x3B (0x5B) Reserved – – – – – – – –
0x3A (0x5A) Reserved – – – – – – – –
0x39 (0x59) Reserved – – – – – – – –
0x38 (0x58) Reserved – – – – – – – –
0x37 (0x57) SPMCSR SPMIE RWWSB – RWWSRE BLBSET PGWRT PGERS SPMEN page 211
0x36 (0x56) Reserved – – – – – – – –
0x35 (0x55) MCUCR SPIPS – – PUD – – IVSEL IVCE page 56 & page 65
0x34 (0x54) MCUSR – – – – WDRF BORF EXTRF PORF page 46
0x33 (0x53) SMCR – – – – SM2 SM1 SM0 SE page 37
0x32 (0x52) MSMCR Monitor Stop Mode Control Register reserved
0x31 (0x51) MONDR Monitor Data Register reserved
0x30 (0x50) ACSR ACCKDIV AC2IF – AC0IF – AC2O – AC0O page 179
0x2F (0x4F) Reserved – – – – – – – –
0x2E (0x4E) SPDR SPD7 SPD6 SPD5 SPD4 SPD3 SPD2 SPD1 SPD0 page 174
0x2D (0x4D) SPSR SPIF WCOL – – – – – SPI2X page 173
0x2C (0x4C) SPCR SPIE SPE DORD MSTR CPOL CPHA SPR1 SPR0 page 172
0x2B (0x4B) Reserved – – – – – – – –
0x2A (0x4A) Reserved – – – – – – – –
0x29 (0x49) PLLCSR - - - - - PLLF PLLE PLOCK page 33
0x28 (0x48) OCR0B OCR0B7 OCR0B6 OCR0B5 OCR0B4 OCR0B3 OCR0B2 OCR0B1 OCR0B0 page 94
0x27 (0x47) OCR0A OCR0A7 OCR0A6 OCR0A5 OCR0A4 OCR0A3 OCR0A2 OCR0A1 OCR0A0 page 93
0x26 (0x46) TCNT0 TCNT07 TCNT06 TCNT05 TCNT04 TCNT03 TCNT02 TCNT01 TCNT00 page 93
0x25 (0x45) TCCR0B FOC0A FOC0B – – WGM02 CS02 CS01 CS00 page 92
0x24 (0x44) TCCR0A COM0A1 COM0A0 COM0B1 COM0B0 – – WGM01 WGM00 page 89
0x23 (0x43) GTCCR TSM ICPSEL1 – – – – – PSRSYNC page 77
0x22 (0x42) EEARH – – – – EEAR11 EEAR10 EEAR9 EEAR8 page 19
0x21 (0x41) EEARL EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 page 19
0x20 (0x40) EEDR EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 page 20
0x1F (0x3F) EECR – – – – EERIE EEMWE EEWE EERE page 20
0x1E (0x3E) GPIOR0 GPIOR07 GP IOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00 page 25
0x1D (0x3D) EIMSK – – – – INT3 INT2 INT1 INT0 page 75
0x1C (0x3C) EIFR – – – – INTF3 INTF2 INTF1 INTF0 page 75
0x1B (0x3B)
GPIOR3 GPIOR37 GPIOR36 GPIOR35 GPIOR34 GPIOR33 GPIOR32 GPIOR31 GPIOR30 page 25
4378BS–AVR–05/08
11
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page
0x1A (0x3A) GPIOR2 GPIOR27 GP IOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20 page 25
0x19 (0x39) GPIOR1 GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10 page 25
0x18 (0x38) Reserved – – – – – – – –
0x17 (0x37) Reserved – – – – – – – –
0x16 (0x36) TIFR1 – – ICF1 – – OCF1B OCF1A TOV1 page 122
0x15 (0x35) TIFR0 – – – – – OCF0B OCF0A TOV0 page 94
0x14 (0x34) Reserved – – – – – – – –
0x13 (0x33) Reserved – – – – – – – –
0x12 (0x32) Reserved – – – – – – – –
0x11 (0x31) Reserved – – – – – – – –
0x10 (0x30) Reserved – – – – – – – –
0x0F (0x2F) Reserved – – – – – – – –
0x0E (0x2E) PORTE – – – – – PORTE2 PORTE1 PORTE0 page 73
0x0D (0x2D) DDRE – – – – – DDE2 DDE1 DDE0 page 73
0x0C (0x2C) PINE – – – – – PINE2 PINE1 PINE0 page 73
0x0B (0x2B) PORTD PORTD7 PORTD6 PORTD5 PORTD4 PORTD3 PORTD2 PORTD1 PORTD0 page 73
0x0A (0x2A) DDRD DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 page 73
0x09 (0x29) PIND PIND7 PIND6 PIND5 PIND4 PIND3 PIND2 PIND1 PIND0 page 73
0x08 (0x28) – – – – – – – – – –
0x07 (0x27) – – – – – – – – – –
0x06 (0x26) – – – – – – – – – –
0x05 (0x25) PORTB PORTB7 PORTB6 PORTB5 PORTB4 PORTB3 PORTB2 PORTB1 PORTB0 page 72
0x04 (0x24) DDRB DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 page 72
0x03 (0x23) PINB PINB7 PINB6 PINB5 PINB4 PINB3 PINB2 PINB1 PINB0 page 73
0x02 (0x22) Reserved – – – – – – – –
0x01 (0x21) Reserved – – – – – – – –
0x00 (0x20) Reserved – – – – – – – –
Note: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operate on the specified bit, and can therefore be used on registers containing such status flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
4. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The AT90PWM1 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used.
12
AT90PWM1
4378BS–AVR–05/08
AT90PWM1
6. Instruction Set Summary
Mnemonics Operands Description Operation Flags #Clocks
ADD Rd, Rr Add two Registers Rd ← Rd + Rr Z,C,N,V,H 1
ADC Rd, Rr Add with Carry two Registers Rd ← Rd + Rr + C Z,C,N,V,H 1
ADIW Rdl,K Add Immediate to Word Rdh:Rdl ← Rdh:Rdl + K Z,C,N,V,S 2
SUB Rd, Rr Subtract two Registers Rd ← Rd - Rr Z,C,N,V,H 1
SUBI Rd, K Subtract Constant from Register Rd ← Rd - K Z,C,N,V,H 1
SBC Rd, Rr Subtract with Carry two Registers Rd ← Rd - Rr - C Z,C,N,V,H 1
SBCI Rd, K Subtract with Carry Constant from Reg. Rd ← Rd - K - C Z,C,N,V,H 1
SBIW Rdl,K Subtract Immediate from Word Rdh:Rdl ← Rdh:Rdl - K Z,C,N,V,S 2
AND Rd, Rr Logical AND Registers Rd ← Rd • Rr Z,N,V 1
ANDI Rd, K Logical AND Register and Constant Rd ← Rd • K Z,N,V 1
OR Rd, Rr Logical OR Registers Rd ← Rd v Rr Z,N,V 1
ORI Rd, K Logical OR Register and Constant Rd ← Rd v K Z,N,V 1
EOR Rd, Rr Exclusive OR Registers Rd ← Rd ⊕ Rr Z,N,V 1
COM Rd One’s Complement Rd ← 0xFF − Rd Z,C,N,V 1
NEG Rd Two’s Complement Rd ← 0x00 − Rd Z,C,N,V,H 1
SBR Rd,K Set Bit(s) in Register Rd ← Rd v K Z,N,V 1
CBR Rd,K Clear Bit(s) in Register Rd ← Rd • (0xFF - K) Z,N,V 1
INC Rd Increment Rd ← Rd + 1 Z,N,V 1
DEC Rd Decrement Rd ← Rd − 1 Z,N,V 1
TST Rd Test for Zero or Minus Rd ← Rd • Rd Z,N,V 1
CLR Rd Clear Register Rd ← Rd ⊕ Rd Z,N,V 1
SER Rd Set Register Rd ← 0xFF None 1
MUL Rd, Rr Multiply Unsigned R1:R0 ← Rd x Rr Z,C 2
MULS Rd, Rr Multiply Signed R1:R0 ← Rd x Rr Z,C 2
MULSU Rd, Rr Multiply Signed with Unsigned R1:R0 ← Rd x Rr Z,C 2
FMUL Rd, Rr Fractional Multiply Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULS Rd, Rr Fractional Multiply Signed R1:R0 ← (Rd x Rr) << 1 Z,C 2
FMULSU Rd, Rr Fractional Multiply Signed with Unsigned R1:R0 ← (Rd x Rr) << 1 Z,C 2
RJMP k Relative Jump PC ← PC + k + 1 None 2
IJMP Indirect Jump to (Z) PC ← Z None 2
RCALL k Relative Subroutine Call PC ← PC + k + 1 None 3
ICALL Indirect Call to (Z) PC ← Z None 3
RET Subroutine Return PC ← STACK None 4
RETI Interrupt Return PC ← STACK I 4
CPSE Rd,Rr Compare, Skip if Equal if (Rd = Rr) PC ← PC + 2 or 3 None 1/2/3
CP Rd,Rr Compare Rd − Rr Z, N,V,C,H 1
CPC Rd,Rr Compare with Carry Rd − Rr − C Z, N,V,C,H 1
CPI Rd,K Compare Register with Immediate Rd − K Z, N,V,C,H 1
SBRC Rr, b Skip if Bit in Register Cleared if (Rr(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBRS Rr, b Skip if Bit in Register is Set if (Rr(b)=1) PC ← PC + 2 or 3 None 1/2/3
SBIC P, b Skip if Bit in I/O Register Cleared if (P(b)=0) PC ← PC + 2 or 3 None 1/2/3
SBIS P, b Skip if Bit in I/O Register is Set if (P(b)=1) PC ← PC + 2 or 3 None 1/2/3
BRBS s, k Branch if Status Flag Set if (SREG(s) = 1) then PC←PC+k + 1 None 1/2
BRBC s, k Branch if Status Flag Cleared if (SREG(s) = 0) then PC←PC+k + 1 None 1/2
BREQ k Branch if Equal if (Z = 1) then PC ← PC + k + 1 None 1/2
BRNE k Branch if Not Equal if (Z = 0) then PC ← PC + k + 1 None 1/2
BRCS k Branch if Carry Set if (C = 1) then PC ← PC + k + 1 None 1/2
BRCC k Branch if Carry Cleared if (C = 0) then PC ← PC + k + 1 None 1/2
BRSH k Branch if Same or Higher if (C = 0) then PC ← PC + k + 1 None 1/2
BRLO k Branch if Lower if (C = 1) then PC ← PC + k + 1 None 1/2
BRMI k Branch if Minus if (N = 1) then PC ← PC + k + 1 None 1/2
BRPL k Branch if Plus if (N = 0) then PC ← PC + k + 1 None 1/2
BRGE k Branch if Greater or Equal, Signed if (N ⊕ V= 0) then PC ← PC + k + 1 None 1/2
BRLT k Branch if Less Than Zero, Signed if (N ⊕ V= 1) then PC ← PC + k + 1 None 1/2
BRHS k Branch if Half Carry Flag Set if (H = 1) then PC ← PC + k + 1 None 1/2
BRHC k Branch if Half Carry Flag Cleared if (H = 0) then PC ← PC + k + 1 None 1/2
BRTS k Branch if T Flag Set if (T = 1) then PC ← PC + k + 1 None 1/2
BRTC k Branch if T Flag Cleared if (T = 0) then PC ← PC + k + 1 None 1/2
BRVS k Branch if Overflow Flag is Set if (V = 1) then PC ← PC + k + 1 None 1/2
BRVC k Branch if Overflow Flag is Cleared if (V = 0) then PC ← PC + k + 1 None 1/2
BRIE k Branch if Interrupt Enabled if ( I = 1) then PC ← PC + k + 1 None 1/2
BRID k Branch if Interrupt Disabled if ( I = 0) then PC ← PC + k + 1 None 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS
BRANCH INSTRUCTIONS
4378BS–AVR–05/08
13
Mnemonics Operands Description Operation Flags #Clocks
SBI P,b Set Bit in I/O Register I/O(P,b) ← 1 None 2
CBI P,b Clear Bit in I/O Register I/O(P,b) ← 0 None 2
LSL Rd Logical Shift Left Rd(n+1) ← Rd(n), Rd(0) ← 0 Z,C,N,V 1
LSR Rd Logical Shift Right Rd(n) ← Rd(n+1), Rd(7) ← 0 Z,C,N,V 1
ROL Rd Rotate Left Through Carry Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7) Z,C,N,V 1
ROR Rd Rotate Right Through Carry Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0) Z,C,N,V 1
ASR Rd Arithmetic Shift Right Rd(n) ← Rd(n+1), n=0..6 Z,C,N,V 1
SWAP Rd Swap Nibbles Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0) None 1
BSET s Flag Set SREG(s) ← 1 SREG(s) 1
BCLR s Flag Clear SREG(s) ← 0 SREG(s) 1
BST Rr, b Bit Store from Register to T T ← Rr(b) T 1
BLD Rd, b Bit load from T to Register Rd(b) ← T None 1
SEC Set Carry C ← 1 C 1
CLC Clear Carry C ← 0 C 1
SEN Set Negative Flag N ← 1 N 1
CLN Clear Negative Flag N ← 0 N 1
SEZ Set Zero Flag Z ← 1 Z 1
CLZ Clear Zero Flag Z ← 0 Z 1
SEI Global Interrupt Enable I ← 1 I 1
CLI Global Interrupt Disable I ← 0 I 1
SES Set Signed Test Flag S ← 1 S 1
CLS Clear Signed Test Flag S ← 0 S 1
SEV Set Twos Complement Overflow. V ← 1 V 1
CLV Clear Twos Complement Overflow V ← 0 V 1
SET Set T in SREG T ← 1 T 1
CLT Clear T in SREG T ← 0 T 1
SEH Set Half Carry Flag in SREG H ← 1 H 1
CLH Clear Half Carry Flag in SREG H ← 0 H 1
MOV Rd, Rr Move Between Registers Rd ← Rr None 1
MOVW Rd, Rr Copy Register Word
LDI Rd, K Load Immediate Rd ← K None 1
LD Rd, X Load Indirect Rd ← (X) None 2
LD Rd, X+ Load Indirect and Post-Inc. Rd ← (X), X ← X + 1 None 2
LD Rd, - X Load Indirect and Pre-Dec. X ← X - 1, Rd ← (X) None 2
LD Rd, Y Load Indirect Rd ← (Y) None 2
LD Rd, Y+ Load Indirect and Post-Inc. Rd ← (Y), Y ← Y + 1 None 2
LD Rd, - Y Load Indirect and Pre-Dec. Y ← Y - 1, Rd ← (Y) None 2
LDD Rd,Y+q Load Indirect with Displacement Rd ← (Y + q) None 2
LD Rd, Z Load Indirect Rd ← (Z) None 2
LD Rd, Z+ Load Indirect and Post-Inc. Rd ← (Z), Z ← Z+1 None 2
LD Rd, -Z Load Indirect and Pre-Dec. Z ← Z - 1, Rd ← (Z) None 2
LDD Rd, Z+q Load Indirect with Displacement Rd ← (Z + q) None 2
LDS Rd, k Load Direct from SRAM Rd ← (k) None 2
ST X, Rr Store Indirect (X) ← Rr None 2
ST X+, Rr Store Indirect and Post-Inc. (X) ← Rr, X ← X + 1 None 2
ST - X, Rr Store Indirect and Pre-Dec. X ← X - 1, (X) ← Rr None 2
ST Y, Rr Store Indirect (Y) ← Rr None 2
ST Y+, Rr Store Indirect and Post-Inc. (Y) ← Rr, Y ← Y + 1 None 2
ST - Y, Rr Store Indirect and Pre-Dec. Y ← Y - 1, (Y) ← Rr None 2
STD Y+q,Rr S tore Indirect with Displacement (Y + q) ← Rr None 2
ST Z, Rr Store Indirect (Z) ← Rr None 2
ST Z+, Rr Store Indirect and Post-Inc. (Z) ← Rr, Z ← Z + 1 None 2
ST -Z, Rr Store Indirect and Pre-Dec. Z ← Z - 1, (Z) ← Rr None 2
STD Z+q,Rr Store Indirect with Displacement (Z + q) ← Rr None 2
STS k, Rr Store Direct to SRAM (k) ← Rr None 2
LPM Load Program Memory R0 ← (Z) None 3
LPM Rd, Z Load Program Memory Rd ← (Z) None 3
LPM Rd, Z+ Load Program Memory and Post-Inc Rd ← (Z), Z ← Z+1 None 3
SPM Store Program Memory (Z) ← R1:R0 None -
IN Rd, P In Port Rd ← P None 1
OUT P, Rr Out Port P ← Rr None 1
PUSH Rr Push Register on Stack STACK ← Rr None 2
POP Rd Pop Register from Stack Rd ← STACK None 2
BIT AND BIT-TEST INSTRUCTIONS
DATA TRANSFER INSTRUCTIONS
MCU CONTROL INSTRUCTIONS
Rd+1:Rd ← Rr+1:Rr
None 1
14
AT90PWM1
4378BS–AVR–05/08
AT90PWM1
Mnemonics Operands Description Operation Flags #Clocks
NOP No Operation None 1
SLEEP Sleep (see specific descr. for Sleep function) None 1
WDR Watchdog Reset (see specific descr. for WDR/timer) None 1
BREAK Break For On-chip Debug Only None N/A
4378BS–AVR–05/08
15
7. Ordering Information
Speed (MHz) Power Supply Ordering Code Package Operation Range
16 2.7 - 5.5V AT90PWM1-16SU SO24
16 2.7 - 5.5V AT90PWM1-16MU QFN32
Note: All packages are Pb free, fully LHF
Note: This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and
minimum quantities.
Extended (-4
Extended (-4
0°C to
105°C)
0°C to
105°C)
16
AT90PWM1
4378BS–AVR–05/08
8. Package Information
24-Lead, 0.300” Body width,
SO24
QFN32 32-Lead, Quad Flat No lead
Plastic GullWing Small Outline Package (SOIC)
AT90PWM1
Package Type
4378BS–AVR–05/08
17
8.1 SO24
18
AT90PWM1
4378BS–AVR–05/08
8.2 QFN32
AT90PWM1
4378BS–AVR–05/08
19
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