ATMEL AT90CAN64 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• High-performance, Low-power AVR

• Advanced RISC Architecture

– 133 Powerful Instructions – Most Single Clock Cycle Execution – 32 x 8 General Purpose Working Registers + Peripheral Control Registers – Fully Static Ope ration – Up to 16 MIPS Throughput at 16 MHz – On-chip 2-cycle Multiplier

• Non volatile Program and Data Memories

– 32K/64K/128K Bytes of In-System Reprogrammable Flash (AT90CAN32/64/128)

• Endurance: 10,000 Write/Erase Cycles

– Optional Boot Code Section with Independent Lock Bits

• Selectable Boot Size: 1K Bytes, 2K Bytes, 4K Bytes or 8K Bytes

• In-System Programming by On-Chip Boot Program (CAN, UART, ...)

• True Read-While-Write Operation –1K/2K/4K – 2K/4K/4K Bytes Internal SRAM (AT90CAN32/64/128) – Up to 64K Bytes Optional External Memory Space – Programming Lock for Software Security

• JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard – Programming Flash (Hardware ISP), EEPROM, Lock & Fuse Bits – Extensive On-chip Debug Support

• CAN Controller 2.0A & 2.0B - ISO 16845 Certified

– 15 Full Message Objects with Separate Identifier Tags and Masks – Transmit, Receive, Automatic Reply and Frame Buffer Receive Modes – 1Mbits/s Maximum Transfer Rate at 8 MHz – Time stamping, TTC & Listening Mode (Spying or Autobaud)

• Peripheral Features

– Programmable Watchdog Timer with On-chip Oscillator – 8-bit Synchronous Timer/Counter-0

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-bit PWM Output – 8-bit Asynchronous Timer/Counter-2

• 10-bit Prescaler

• External Event Counter

• Output Compare or 8-Bit PWM Output

• 32Khz Oscillator for RTC Operation – Dual 16-bit Synchronous Timer/Counte rs-1 & 3

• 10-bit Prescaler

• Input Capture with Noise Canceler

• External Event Counter

• 3-Output Compare or 16-Bit PWM Output

• Output Compare Modulation – 8-channel, 10-bit SAR ADC

• 8 Single-ended Channels

• 7 Differential Channels

• 2 Differential Channels With Programmable Gain at 1x, 10x, or 200x – On-chip Analog Comparator – Byte-oriented Two-wire Serial Interface – Dual Programmable Serial USART – Master/Slave SPI Serial Interface

• Programming Flash (Hardware ISP)

• Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection – Internal Calibrated RC Oscillator – 8 External Interrupt Sources – 5 Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down & Standby – Software Selectable Clock Frequency – Global Pull-up Disable

• I/O and Packages

– 53 Programmable I/O Lines – 64-lead TQFP and 64-lead QFN

• Operating Voltages: 2.7 - 5.5V

• Operating temperature: Industrial (-40°C to +85°C)

• Maximum Fre quency: 8 MHz at 2.7V, 16 MHz at 4.5V

Note: 1. Details on section 19.4.3 on page 242.

Bytes EEPROM (End uran ce: 10 0,000 Write/Erase Cycles) (AT90CAN32/64/128)

8-bit Microcontroller

(1)

8-bit Microcontroller with 32K/64K/128K Bytes of ISP Flash and CAN Controller

AT90CAN32 AT90CAN64 AT90CAN128

Rev. 7679F–C AN–11/07

AT90CAN32/64/128

1. Description

1.1 Comparison Between AT90CAN32, AT90CAN64 and AT90CAN128

AT90CAN32, AT9 0CAN64 an d AT90CAN 128 are ha rdware an d softwar e compati ble. They differ only in memory sizes as shown in Table 1-1.

Table 1-1. Memory Size Summary

Device Flash EEPROM RAM

AT90CAN32 32K Bytes 1K Byte 2K Bytes AT90CAN64 64K Bytes 2K Bytes 4K Bytes AT90CAN128 128K Bytes 4K Byte 4K Bytes

1.2 Part Description

The AT90CAN32/64/128 is a low-power CMOS 8- bit microcontroller based on the A VR enhanced RISC architecture. By executing powerful instructions in a single clock cycle , the AT90CAN32/64/128 achieves throughputs ap proaching 1 M IPS per M Hz allowin g the sys tem designer to optimize power consumption versus processing speed.

The AVR core comb ines a r ich in st ruct ion s et with 32 gene ral purp ose wor kin g re gist ers. All 3 2 registers are direc tly connec ted to the Arithme tic Logic Uni t (ALU), allowing two indepen dent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

The AT90CAN32/64/128 provides the following features: 32K/64K/128K bytes of In-System Programmable Flash wi th Read-While-W rite capabili ties, 1K/2K/4K bytes EEPROM, 2K/4K/4K bytes SRAM, 53 general purpose I/O lines, 32 general purpose working registers, a CAN controller, Real Time Counter (RTC), four flexible Timer/Counters with compare modes and PWM, 2 USARTs, a byte oriented Two-wire Serial Interface, an 8-channel 10-bit ADC with optional differential input stage with programmable gain, a programmable Watchdog Timer with Internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for accessing the On-chip Debug system and programming and five software selectable power saving modes.

The Idle mode stops the CPU while allo wing the SRAM, Ti mer/Counter s, SPI/CAN port s and interrupt system to c onti nue fun cti on ing . The Power-down mode saves the r e gister c on tents b ut freezes the Oscillator, d isabling all o ther chip functi ons until the nex t interrupt or Har dware Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the res t of the dev ice i s sleeping. The ADC Noise Reduction mode stops the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the rest of the device is sleeping. This allows very fast start-up combined with low power consumption.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The Onchip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial interface, by a conventional nonvolati le memory programmer , or by an On-chip B oot program running on the AVR core. The boot program can use any interface to download the application program in the application Flash memory. Software in the Boot Flash section will continue to run while the Application Flash section is updated, prov iding true Read-Whi le-Write operation. By

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1.3 Disclaimer

AT90CAN32/64/128

combining an 8-bit RISC CP U with In-System Self-Programm able Flash on a monolithi c chip, the Atmel AT90CAN32/64/128 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications.

The AT90CAN32/64/128 AVR is supported with a full suite of program and system development tools including: C co mpile rs, m acro as sembl ers, pr ogram deb ugg er/simu lator s, in-c ircuit e mulators, and evaluation kits.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.

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AT90CAN32/64/128

1.4 Block Diagram

Figure 1-1. Block Diagram

VCC

GND

AVCC

AGND AREF

DATA REGISTER

JTAG TAP

ON-CHIP DEBUG

BOUNDARY-

SCAN

PROGRAMMING

LOGIC

PORTF DRIVERS

PORTF

DATA DIR.

REG. PORTF

ADC

PROGRAM COUNTER

PROGRAM

FLASH

INSTRUCTION

DECODER

DATA REGISTER

PORTA

POR - BOD

RESET

STACK

POINTER

SRAM

GENERAL PURPOSE

REGISTERS

X Y Z

PA7 - PA0PF7 - PF0

PORTA DRIVERS

DATA DIR.

REG. PORTA

8-BIT DATA BUS

INTERNAL

OSCILLATOR

WATCHDOG

TIMER

MCU CONTROL

TIMER/

COUNTERS

INTERRUPT

UNIT

PORTC DRIVERS

DATA REGISTER

PORTC

CALIB. OSC

OSCILLATOR

TIMING AND

CONTROL

PC7 - PC0

DATA DIR.

REG. PORTC

CAN

CONTROLLER

XTAL1

XTAL2

RESET

ANALOG

COMPARATOR

DATA REGISTER

PORTE

CONTROL

LINES

DATA DIR.

REG. PORTE

PORTE DRIVERS

ALU

STATUS

DATA REGISTER

PORTB

PORTB DRIVERS

PB7 - PB0PE7 - PE0

DATA DIR.

REG. PORTB

EEPROM

SPIUSART0

DATA REGISTER

PORTD

PORTD DRIVERS

PD7 - PD0

USART1

DATA DIR.

REG. PORTD

TWO-WIRE SERIAL

INTERFACE

DATA REG.

PORTG

DATA DIR.

REG. PORTG

PORTG DRIVERS

PG4 - PG0

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1.5 Pin Configurations

Figure 1-2. Pinout AT90CAN32/64/128 - TQFP

AT90CAN32/64/128

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3 (OC2A) PB4 (OC1A) PB5 (OC1B) PB6

AVCC

(1)

1 2

4 5 6 7 8 9

10 11 12 13 14 15 16

AREF

GND

INDEX CORNER

PF1 (ADC1)

PF0 (ADC0)

(64-lead TQFP top view)

PF3 (ADC3)

PF2 (ADC2)

592058

PF5 (ADC5 / TMS)

PF4 (ADC4 / TCK)

572256

PF6 (ADC6 / TDO)

VCC

GND

PF7 (ADC7 / TDI)

532652

PA0 (AD0)

PA1 (AD1)

PA2 (AD2) 49

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

PA3 (AD3) PA4 (AD4) PA5 (AD5) PA6 (AD6) PA7 (AD7) PG2 (ALE) PC7 (A15 / CLKO) PC6 (A14) PC5 (A13) PC4 (A12) PC3 (A11) PC2 (A10)

PC1 (A9) PC0 (A8) PG1 (RD) PG0 (WR)

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(2)

(TOSC2 ) PG3

(TOSC1 ) PG4

(1)

NC = Do not connect (May be used in future devices)

(2)

Timer2 Oscillator

(OC0A / OC1C) PB7

VCC

RESET

GND

235524

XTAL2

XTAL1

(SCL / INT0) PD0

(SDA / INT1) PD1

(TXD1 / INT3) PD3

(RXD1 / INT2) PD2

(ICP1) PD4

(RXCAN / T1) PD6

(TXCAN / XCK1) PD5

(T0) PD7

AT90CAN32/64/128

Figure 1-3. Pinout AT90CAN32/64/128 - QFN

AREF

GND

AVCC

6463625361

(1)

(RXD0 / PDI) PE0

(TXD0 / PDO) PE1

(XCK0 / AIN0) PE2

(OC3A / AIN1) PE3

(OC3B / INT4) PE4

(OC3C / INT5) PE5

(T3 / INT6) PE6

(ICP3 / INT7) PE7

(SS) PB0

(SCK) PB1

(MOSI) PB2

(MISO) PB3 (OC2A) PB4 (OC1A) PB5 (OC1B) PB6

4 5 6 7 8

9 10 11 12 13 14 15 16 33

(64-lead QFN top view)

PF0 (ADC0)

PF1 (ADC1)

PF2 (ADC2)

PF3 (ADC3)

605958

INDEX CORNER

GND

PF4 (ADC4 / TCK)

575655

PF7 (ADC7 / TDI)

PF5 (ADC5 / TMS)

PF6 (ADC6 / TDO)

VCC

PA0 (AD0)

525150

PA1 (AD1)

PA2 (AD2) 49

PA3 (AD3)

PA4 (AD4)

PA5 (AD5) PA6 (AD6)

PA7 (AD7)

PG2 (ALE)

PC7 (A15 / CLKO)

PC6 (A14)

PC5 (A13)

PC4 (A12)

PC3 (A11)

PC2 (A10)

PC1 (A9)

PC0 (A8)

PG1 (RD)

PG0 (WR)

(1)

NC = Do not connect (May be used in future devices)

(2)

Timer2 Oscillator

Note: The large center pad underneath the QFN package is made of metal and internally connected to

1.6 Pin Descriptions

1.6.1 VCC

Digital supply voltage.

1.6.2 GND

Ground.

182019

(2)

(TOSC2 ) PG3

(OC0A / OC1C) PB7

21222324252627

VCC

(2)

RESET

(TOSC1 ) PG4

GND

XTAL1

XTAL2

(SCL / INT0) PD0

(ICP1) PD4

(SDA / INT1) PD1

(TXD1 / INT3) PD3

(RXD1 / INT2) PD2

(TXCAN / XCK1) PD5

(T0) PD7

(RXCAN / T1) PD6

GND. It should be sold ered or g lued to the boar d to ens ure good mech anica l st abili ty. If the center pad is left unconnected, the package might loosen from the board.

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1.6.3 Port A (PA7..PA0)

Port A is an 8-bi t b i- dire ctional I/O port with internal pull-up res is tors ( sele cte d f or ea ch bi t). T h e Port A output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated whe n a rese t condition bec omes ac tive, even if the clock is not running.

Port A also serves the funct ions of variou s specia l features of t he AT90CAN32/ 64/128 as list ed on page 74.

1.6.4 Port B (PB7..PB0)

Port B is an 8-bi t b i- dire ctional I/O port with internal pull-up res is tors ( sele cte d f or ea ch bi t). T h e Port B output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. The Port B pins are tri-stated whe n a rese t condition bec omes ac tive, even if the clock is not running.

Port B also serves the funct ions of variou s specia l features of t he AT90CAN32/ 64/128 as list ed on page 76.

1.6.5 Port C (PC7..PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port C output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. The Port C pi ns are tri-stated when a res et condition bec omes active, even if the clock is not running.

AT90CAN32/64/128

Port C also serves the functions of special features of the AT90CAN32/64/128 as listed on page

78.

1.6.6 Port D (PD7..PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. The Port D pi ns are tri-stated when a res et condition bec omes active, even if the clock is not running.

Port D also serves the fu nction s of v arious speci al feat ures of the AT90CAN 32/6 4/128 a s li sted on page 80.

1.6.7 Port E (PE7..PE0)

Port E is an 8-bi t b i- dire ctional I/O port with internal pull-up res is tors ( sele cte d f or ea ch bi t). T h e Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E pins that are externally pulled low will source current if the pull-up resistors are activated. The Port E pins are tri-stated whe n a rese t condition bec omes ac tive, even if the clock is not running.

Port E also serves the funct ions of variou s specia l features of t he AT90CAN32/ 64/128 as list ed on page 83.

1.6.8 Port F (PF7..PF0)

Port F serves as the analog inputs to the A/D Converter.

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AT90CAN32/64/128

Port F also serves as an 8-bit bi-directional I/O port, if the A/D Converter is not used. Port pins can provide internal pull-up resistors (selected for each bit). The Port F output buffers have symmetrical drive charac teristics wi th both hig h sink and source capabili ty. As inp uts, Port F pins that are externall y pu ll ed low wi ll sour c e cu rren t i f th e pul l- up re sis tors ar e ac tivated. The Port F pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port F also serves the functions of the JTAG interface. If the JTAG interface is enabled, the pullup resistors on pins PF7(TDI), PF5(TMS), and PF4(TCK) will be activated even if a reset occurs.

1.6.9 Port G (P G 4 .. P G 0 )

Port G is a 5-bit I/O p ort wi th inte rnal pul l-up resisto rs (s elect ed for eac h bit) . The Po rt G o utput buffers have symmetrical drive characteristics with both high sink and source capabil ity. As inputs, Port G pins that are externally pulled low will source current if the pul l-up resistors are activated. The Port G pins are tri-stated when a reset condition becomes active, even if the clock is not running.

Port G also serves th e funct ions o f va rious s peci al featu res of the AT90C AN32 /64/128 as li sted on page 88.

1.6.10 RESET

1.6.11 XTAL1

1.6.12 XTAL2

1.6.13 AVCC

1.6.14 AREF

Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset. The minimum pulse length is given in characteristics. Shorter pulses are not guaranteed to generate a reset. The I/O ports of the AVR are immediately reset to their initial state even if the clock is not running. The clock is needed to reset the rest of the AT90CAN32/64/128.

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting Oscillator amplifier.

AVCC is the supply voltage pin for the A/D Converter on Port F. It should be externally connected to V through a low-pass filter.

This is the analog reference pin for the A/D Converter.

2. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the device. These code examples assume that the part specific header file is inc luded before compilation. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C is compiler dependent. Please confirm with the C compiler documentation for more details.

, even if the ADC is not used. If the ADC is used, it should be connected to V

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3. AVR CPU Core

3.1 Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts.

3.2 Architectural Overview

Figure 3-1. Block Diagram of the AVR Architecture

AT90CAN32/64/128

Data Bus 8-bit

Flash

Program

Memory

Instruction

Decoder

Control Lines

Program

Counter

Direct Addressing

Status

and Control

32 x 8 General Purpose

Registrers

ALU

Indirect Addressing

Data

SRAM

EEPROM

Interrupt

Unit

SPI

Unit

Watchdog

Timer

Analog

Comparator

I/O Module1

I/O Module 2

I/O Module n

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I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with separate memories and buse s for program and data. Instructi ons in the p rogram memory ar e executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the p rogram memory . This concep t enabl es i nstruct ions to be ex ecute d in every clock cycle. The program memory is In-System Reprogrammable Flash memory.

AT90CAN32/64/128

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typical ALU operation, two operands are output from the Register File, the operation is executed, and the result is stored back in the Register File – in one clock cycle.

Six of the 32 r egisters can be used as three 1 6-bit i ndirect address register pointer s for Dat a Space addressing – enabling efficient address calculations. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports ar it hme tic a nd log ic o perati on s betwe en r egisters or between a co ns tan t an d a register. Single register operations can also be executed in the ALU. After an arithmetic operation, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to directly address the whol e addres s space. Mo st AVR instru ctions hav e a single 16 -bit word format. Every program memory address contains a 16- or 32-bit instruction.

Program Flash memory space is divided in two sections, the Boot Program sec tion and the Application Prog ram sect ion. Both se ctions ha ve dedicate d Lock bits for write and rea d/write protection. The SPM (Store Program Memory) instruction that writes into the Application Flash memory section must reside in the Boot Program section.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the Stack. The Stack is e ffec ti ve ly al lo ca ted in the general data SR A M, a nd co nse que ntl y the Sta ck size is only limited by th e total SRAM size a nd the usage of the SRAM . All user p rogram s mus t initialize the SP in th e Re set routi ne (bef ore s ubrou tine s o r int errup ts are e xecut ed ). The Sta ck Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps. A flexible inter rupt modul e has its cont rol registe rs in the I/O s pace with a n additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the Interrupt Vector table. T he in terr up ts h av e pri or ity in ac co rd ance wi th t hei r Interr up t Ve cto r pos ition. The lower the Interrupt Vector address, the higher is the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, SPI, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the AT90CAN32/64/128 has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used.

3.3 ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single c lock cycle, arithmetic operat ions between general purpose registers or between a register and an immediate are executed. The ALU operations are divided into three main categories – arithmetic, logical, and bit-functions. Some implementations of the architecture also provide a po werful mult iplier suppo rting both sig ned/unsig ned multipl ication and fractional format. See the “Instruction Set Summary” section for a detailed description.

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3.4 Status Register

AT90CAN32/64/128

The Status Register contains information about the result of the m ost recently exe cuted arithmetic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.

The Status Re gis ter i s no t au tomat icall y s tored w hen enteri ng a n in ter rupt routi ne a nd r estor ed when returning from an interrupt. This must be handled by software.

The AVR Status Register – SREG – is defined as:

Bit 76543210

I T H S V N Z C SREG

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set to enable d the interrupts. The in dividual interru pt enable control is then performed in separate control registers. If the Global Interrupt Enable Register is cleared, none of the interrupts are ena bled independ ent of the individual interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instr uctions BL D (Bit LoaD) and BST (B it STore) us e the T-bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a regi ster in the Register File by the BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H ind icate s a Hal f Carry in s ome ari thmetic operati ons. Ha lf Carry Is usefu l in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N

⊕ V

The S-bit is always an EXCLUSIVE OR between the negative flag N and the Two’s Complement Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

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AT90CAN32/64/128

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information.

3.5 General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 3-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 3-2. AVR CPU General Purpose Working Registers

General R14 0x0E Purpose R15 0x0F Working R16 0x10

Registers R17 0x11

70Addr.

R0 0x00 R1 0x01 R2 0x02

…

R13 0x0D

… R26 0x1A X-register Low Byte R27 0x1B X-register High Byte R28 0x1C Y-register Low Byte R29 0x1D Y-register High Byte R30 0x1E Z-register Low Byte R31 0x1F Z-register High Byte

Most of the instructions operati ng on the Regis ter File have d irect access to all register s, and most of them are single cycle instructions.

As shown i n Figure 3-2, each register is also assigned a data memory address, mapping them directly into the first 32 locations of the user Data Space. Although not being physically implemented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

3.5.1 The X-register, Y-register, and Z-register

The registers R26..R31 have s ome adde d functi ons to their gen eral purpose us age. Thes e registers are 16-bit address poin ters for indirec t addressing of the data space. The three indi rect address registers X, Y, and Z are defined as des cri bed in Figure 3-3.

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Figure 3-3. The X-, Y-, and Z-registers

15 XH XL 0

X-register 7 0 7 0

R27 (0x1B) R26 (0x1A)

15 YH YL 0

Y-register 7 0 7 0

R29 (0x1D) R28 (0x1C)

15 ZH ZL 0

Z-register 7 0 7 0

R31 (0x1F) R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details).

3.5.2 Extended Z-pointer Register for ELPM/SPM – RAMPZ

Bit 7 6 5 4 3 2 1 0

– – – – – – – RAMPZ0 RAMPZ

Read/Write R R R R R R R R/W Initial Value 0 0 0 0 0 0 0 0

AT90CAN32/64/128

• Bits 7..1 – Res: Reserved Bits

These bits are reserved for fut ur e us e an d will a lwa ys read a s z ero. F or comp ati bil it y wi th fu tur e devices, be sure to write to write them to zero.

• Bit 0 – RAMPZ0: Extended RAM Page Z-pointer

The RAMPZ Register is normally us ed to select whi ch 64K RAM Page is accesse d by the Zpointer. As the AT90CAN32/64/128 does not support more than 64K of SRAM memory, this register is used only to select which page in the program memory is accessed when the ELPM/SPM instruction is used. The different settings of the RAMPZ0 bit have the following effects:

RAMPZ0 = 0:Program memory address 0x0000 - 0x7FFF (lower 64K bytes) is accessed by

ELPM/SPM

RAMPZ0 = 1:Program memory address 0x8000 - 0xFFFF (higher 64K bytes) is accessed by

ELPM/SPM

– AT90CAN32 and AT90CAN64: RAMPZ0 exists as registe r bit but it is not used for

program memory addressing.

– AT90CAN128: RAMPZ0 exists as register bit and it is used for program memory

addressing.

Figure 3-4. The Z-pointer used by ELPM and SPM

7Bit (Individually) 0 7 0 7 0

RAMPZ ZH ZL

23Bit (Z-pointer) 16 15 8 7 0

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Note: LPM (different of ELPM) is never affected by the RAMPZ setting.

AT90CAN32/64/128

3.6 Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses aft er interrupts and subroutin e c all s . The S ta ck Po in ter Reg ister al ways poi nts to the top o f t he S t ac k. N ot e t h at t h e S tack is implemente d a s gr ow i ng f ro m hi gh e r m em or y l o ca tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack Pointer.

The Stack Point er points to the data SRAM S tack area wh ere the Su broutine a nd Interrupt Stacks are located. Thi s Stac k space i n the data S RAM mus t be defin ed by the pr ogram be fore any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be s et to point above 0xFF. The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH instruction, and it is decremented by two when the return address is pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from the Stack w ith the POP instruction, and it is incr emented by two when data is popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of bits actually used is implementation dependent. Note that the data space in some implementations of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register will not be present.

Bit 151413121110 9 8

SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SPH

SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0 SPL

76543210

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 00 000000

00000000

3.7 Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk chip. No internal clock division is used.

Figure 3-5 shows the parallel instructio n fetches an d instruc tion ex ecutions enable d by the Ha r-

vard architecture and th e fast- access Register File con cept. Thi s is the bas ic pipel ining conce pt to obtain up to 1 MIPS per MHz with the cor respondi ng unique res ults for func tions per cos t, functions per clocks, and functions per power-unit.

Figure 3-5. The Parallel Instruction Fetches and Instruction Executions

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

clk

CPU

, directly generated from the selected clock source for the

CPU

T1 T2 T3 T4

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Figure 3- 6 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two regi ster ope rands is executed , and the result is stored bac k to the de stination register.

Figure 3-6. Single Cycle ALU Operation

Total Execution Time

ALU Operation Execute

Result Write Back

3.8 Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts ar e assigned individual enable bits which must be written logic one together with the Global Interrupt Enable bit in the Status Re gister in or der to ena ble the int errupt. De pendin g on the Prog ram Counter value, interrupts may be automatically disabled when Boot Lock bits BLB02 or BLB12 are programmed. This feature improves software security. See the section “Memory Program-

ming” on page 336 for details .

clk

AT90CAN32/64/128

T1 T2 T3 T4

CPU

The lowest addresses in the p rogram memory space are by default defined as the Reset a nd Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on pag e 60. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESE T has the highe st priorit y, and next is INT 0 – the External Interrupt Requ est

0. The Interrupt Vectors can be moved to the start of the Boot Flash section by setting the IVSEL bit in the MCU Control Register (MCUCR). Refer to “Interrupts” on page 60 for more information. The Reset Vector can also be m oved to the s tart o f the Bo ot Flas h secti on by p rogram ming th e BOOTRST Fu se, s ee “Boot Loader Support – Read-While-Write Self-Programming” on page

321.

3.8.1 Interrupt Behavior

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are disabled. The user softw are c an write lo gic one to the I-bit to enab le nes ted i nterrup ts. Al l ena bled interrupts can then interrupt the current interrupt routine. The I-bit is automa tically set when a Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execut e the int errupt ha ndlin g routine , and hardware clears the cor respon ding inte rrupt flag. Interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt flag wi ll be set an d remembe red u ntil th e interr upt is enabl ed, or th e flag is c leared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt Enable bit is cleared, the c orrespond ing interru pt flag(s) wil l be set and reme mbered unti l the Globa l Interrupt Enable bit is set, and will then be executed by order of priority.

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AT90CAN32/64/128

The second type of interrupts will trigger as long as the interrupt condition is present. These interrupts do not necessa rily hav e in ter rupt fl ags . If the interr up t con dit ion disapp ear s befo re the interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served.

Note that the Status Register is not automatic ally stored when entering an in terrupt rou tine, nor restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruct ion to disable interrupts, the interrupt s will be immedia tely disab led. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence.

Assembly Code Example

in r16, SREG ; store SREG value

cli ; disable interrupts during timed sequence

sbi EECR, EEMWE ; start EEPROM write

sbi EECR, EEWE

out SREG, r16 ; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG; /* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMWE); /* start EEPROM write */

EECR |= (1<<EEWE);

SREG = cSREG; /* restore SREG value (I-bit) */

When using the SEI instruction to enable interrupts, the instruction following SEI will be executed before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep ; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

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3.8.2 Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles minimum. After four clock cycles the program vector address for the actual interrupt handling routine is executed. During this four clock cycle pe riod , the Prog ram Co unter is pu shed o nto the Stack. The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt execution response time is increased by four clock cycles. This increase comes in addition to the start-up time from the selected sleep mode.

A return from an inter rupt handli ng routine takes four clock cycles. During the se four c lock cycles, the Program Cou nter (two bytes ) is popped back fr om the Stack, the Sta ck Pointer is incremented by two, and the I-bit in SREG is set.

AT90CAN32/64/128

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AT90CAN32/64/128

4. Memories

This section describes th e di ffe re nt m emo ries in the A T90CA N32 /64/1 28. T he A V R arc hit ect ur e has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90CAN32/64/128 features an EEPROM Memory for data storage. All three memory spaces are linear and regular.

Table 4-1. Memory Mapping.

Memory Mnemonic AT90CAN32 AT90CAN64 AT90CAN128

Flash

Registers

I/O

Registers

Ext I/O

Registers

Internal

SRAM

External Memory

EEPROM

Size Start Address

End Address

Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address Size Start Address End Address

Flash size 3 2 K bytes 64 K bytes 128 K bytes

- 0x00000

Flash end

0x07FFF

0x3FFF

(1)

(2)

0x0FFFF

0x7FFF

(1)

(2)

0x1FFFF

0xFFFF

(1)

(2)

-32 bytes

- 0x0000

- 0x001F

-64 bytes

- 0x0020

- 0x005F

- 160 bytes

- 0x0060

-0x00FF

ISRAM size 2 K bytes 4 K bytes 4 K bytes

ISRAM start 0x0100

ISRAM end 0x08FF 0x10FF 0x10FF

XMem size 0-64 K bytes XMem start 0x0900 0x1100 0x1100 XMem end 0xFFFF

E2 size 1 K bytes 2 K bytes 4 K bytes

- 0x0000

E2 end 0x03FF 0x07FF 0x0FFF

Notes: 1. Byte address.

4.1 In-System Reprogrammable Flash Program Memory

The AT90CAN32/64/128 contains On-chip In-System Reprogrammable Flash memory for program storage (see “Flash size”). Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as 16 bits wide. For software security, the Flash Program memory space is divided into two sections, Boot Program section and Application Program section.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The AT90CAN32/64/128 Program Counter (PC) address the program memory locations. The operation of Boot Program section and associated Boot Lock bits for software protection are described in detail in “Boot Loader Support – Read-While-Write Self-Programming” on page 321. “Memory

Programming” on pa ge 336 contai ns a detailed de scription on Flash data ser ial download ing

using the SPI pins or the JTAG interface.

2. Word (16-bit) address.

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AT90CAN32/64/128

Constant tables can be allocated within the entire program memory address space (see the LPM – Load Program Memory and ELPM – Extended Load Program Memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 14.

Figure 4-1. Program Memory Map

Program Memory

0x0000

Application Flash Section

4.2 SRAM Data Memory

Figure 4-2 shows how the AT90CAN32/64/128 SRAM Memory is organized.

The AT90CAN32/6 4/128 i s a c omplex microc ontroller with m ore pe ripheral u nits t han can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

The lower data memory loc ati ons add re ss bo th the Register File, the I/O memor y, E xte nde d I/O memory, and the internal data SRAM. The first 32 locations address the Register File, the next 64 location the standar d I/O memo ry, then 1 60 loca tions of Extended I/O mem ory, and the next locations address the internal data SRAM (see “ISRAM size”).

An optional external data SRAM can be used with the AT90CAN32/64/128. T his SRAM will occupy an area in the remaining address locations in the 64K address space. This area starts at the address following the internal SRAM. The Register file, I/O, Extended I/O and Internal SRAM occupies the lowest bytes , so when using 64 KB (65,536 bytes) of External Memory, “XMem size” bytes of Exter nal Me mory ar e availab le. See “Exter nal Me mory Interfa ce” o n page

27 for details on how to take advantage of the external memory map.

Boot Flash Section

Flash end

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AT90CAN32/64/128

4.2.1 SRAM Data Access

When the addresses ac cessing the SRA M memory spac e exceeds the internal data me mory locations, the external data SRAM is acces sed using the sa me instructi ons as for the internal data memory access. When the internal data memories are accessed, the read and write strobe pins (PG0 enabled by setting the SRE bit in the XMCRA Register.

Accessing exte rnal SRA M takes one additi onal c lock cycl e per byte compar ed to ac cess of th e internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine calls and returns take three clock cy cles ex tra bec aus e the two- byte pr og ra m cou nter i s pushe d and popped, and external memory access does not take advantage of the internal pipe-line memory access. When external SRAM interface is used with wait-state, one-byte external access takes two, three, or four additional clock cycles for one, two, and three wait-states respectively. Interrupts, subroutine calls and returns will need five, seven, or nine clock cycles more than specified in the instruction set manual for one, two, and three wait-states.

The five different addressing modes for the data memory cover: Direct, Indirect with Displacement, Indirect, Ind irect with Pre- decrement , and Indirect with Post-inc rement. In the Re gister File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space. The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

and PG1) are inacti ve during th e whole access cycle. Exter nal SRAM oper ation is

When using register indirect addressing modes with automatic pre-decr ement and post-increment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and the “ISRAM size” bytes of internal data SRAM in the AT90CAN32/64/128 are all accessible through all these add ress ing m odes. Th e Re gister F ile is desc ribed i n “Gener al P urpose R egis-

ter File” on page 12.

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Figure 4-2. Data Memory Map

AT90CAN32/64/128

Data Memory

4.2.2 SRAM Data Access Times

This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk

32 Registers 64 I/O Registers 160 Ext I/O Reg.

Internal SRAM

(ISRAM size)

External SRAM

(XMem size)

0x0000 - 0x001F 0x0020 - 0x005F 0x0060 - 0x00FF

ISRAM start

ISRAM end XMem start

0xFFFF

cycles as described in Figure 4-3.

CPU

7679F–CAN–11/07

Figure 4-3. On-chip Data SRAM Access Cycles

T1 T2 T3

clk

CPU

Address

Compute Address

Data

Memory Access Instruction

Address valid

Write

Read

Next Instruction

AT90CAN32/64/128

4.3 EEPROM Data Memory

The AT90CAN32/64/128 con tains EEPRO M memory (see “ E2 size”). It is organ ized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Registe r.

For a detailed description of SPI, JTAG and Parallel data downloading to the EEPROM, see

“SPI Serial Programming Overview” on page 348, “JTAG Programming Overview” on page 352,

and “Parallel Program mi ng Overv iew ” on page 339 respectively.

4.3.1 EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space. The write access time for the EEPROM is given in Table 4-2. A self-timing function, however,

lets the user software detect when the next byte can be written. If the user code contains instructions that write the EE PROM, some precau tions must be taken. In he avily filtered power supplies, V period of time to run at a vo ltag e lo wer tha n sp ec ifi ed as mi ni mum for the clo ck frequ enc y u se d.

See “Preventing EEPROM Corruption” on page 26.for details on how to avoid problems in these

situations. In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to the description of the EEPROM Control Register for details on this.

is likely to rise or fall slowly on power-up/down. This causes the device for some

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is executed. When the E EPROM is writ ten, the CPU i s halted for tw o clock cycles before t he nex t instruction is execute d.

4.3.2 The EEPROM Address Registers – EEARH and EEARL

Bit 15 14 13 12 11 10 9 8

– – – – EEAR11 EEAR10 EEAR9 EEAR8 EEARH

EEAR7 EEAR6 EEAR5 EEAR4 EEAR3 EEAR2 EEAR1 EEAR0 EEARL

76543 210

Read/Write RRRRR/WR/WR/WR/W

R/W R/W R/W R/W R/W R/W R/W R/W

Initial Value 0 0 0 0 X X X X

XXXXX XXX

• Bits 15..12 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

• Bits 11..0 – EEAR11..0: EEPROM Address

The EEPROM Addre ss Registers – EEARH a nd EEARL specify the EEPR OM address in the EEPROM space (se e “E2 size”). The EEPROM d ata bytes are ad dressed li nearly betw een 0 and “E2 end”. The initial value of EEA R is u ndefine d. A prope r val ue mus t be writte n be fore the EEPROM may be accessed.

– AT90CAN32: EEAR11 & EEAR10 exist as register bit but they are not used for

addressing.

– AT90CAN64: EEAR11 exists as register bit but it is not used for addressing.

7679F–CAN–11/07

4.3.3 The EEPROM Data Register – EEDR

Bit 76543210

EEDR7 EEDR6 EEDR5 EEDR4 EEDR3 EEDR2 EEDR1 EEDR0 EEDR

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W Initial Value00000000

• Bits 7..0 – EEDR7.0: EEPROM Data

For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR.

4.3.4 The EEPROM Control Register – EECR

Bit 76543210

– – – – EERIE EEMWE EEWE EERE EECR

Read/Write R R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 X 0

• Bits 7..4 – Reserved Bits

These bits are reserved bits in the AT90CAN32/64/128 and will always read as zero.

AT90CAN32/64/128

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I bit in SREG is set. Writing EERIE to zero disables the interrup t. The E EPROM Rea dy inter rup t generates a cons tant inte rrupt when EEWE is cleared.

• Bit 2 – EEMWE: EEPROM Master Write Enable

The EEMWE bit determines whether setting EEWE to one causes the EEPROM to be written. When EEMWE is set, setting EEWE within four clock cycles will write data to the EEPROM at the selected address If EEMWE is zero, setting EEWE will have no effect. When EEMWE has been written to on e by soft ware, ha rdwar e cle ars th e bit to z ero aft er fo ur cl ock c ycles . See th e description of the EEWE bit for an EEPROM write procedure.

• Bit 1 – EEWE: EEPROM Write Enable

The EEPROM Write Enable Signa l EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EE WE bit must be written to one to write the value into the EEPROM. The EEMWE bit mu st b e written to one befor e a log ical one is written to E EWE, otherwise no EEPROM write tak es pla ce . Th e follow ing procedure should be foll owe d when writin g the EEPROM (the order of steps 3 and 4 is not essential):

1. Wait until EEWE becomes zero.

2. Wait until SPMEN (Store Program Memory Enable) in SPMCSR (Store Program Memory Control and Status Register) becomes zero.

3. Write new EEPROM address to EEAR (optional).

4. Write new EEPROM data to EEDR (optional).

5. Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

6. Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software must check that the Flash programming is completed before initiating a new EEPROM write. Step 2 is only rele vant if the soft ware cont ains a Boo t Load er allow ing the CPU to progr am the Flash. If the Flash is never being updat ed by the CPU, step 2 ca n be omi tted . See “Bo ot Loa der

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AT90CAN32/64/128

Support – Read-While-Write Self-Programming” on page 321 for details about Boot

programming. Caution: An interrupt between step 5 and step 6 will ma ke the write cycle fail, since the

EEPROM Master Write E nable will time-out. If an i nterrupt routi ne accessi ng the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable S ignal EE RE is the re ad strobe to the EE PROM. Whe n the corr ect address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the EEPROM read. The EEPROM read access takes one instruction, and the requested data is available immediatel y. When the EEPRO M is read, the CPU is halted for four cycles before the next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Osci llat or i s used t o tim e the EEP ROM acce sses. Table 4-2 lists the typi cal programming time for EEPROM access from the CPU.

Table 4-2. EEPROM Programming Time.

Symbol Number of Calibrated RC Oscillator Cycles Typ Programming Time

EEPROM write (from CPU) 67 584 8.5 ms

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AT90CAN32/64/128

The following code examples show one assembly and on e C function for writin g to the EEPROM. The examp les ass ume that int errupt s are contr olled (e.g. by disabl ing inter rupts gl obally) so that no i nterrupt s will occur during exec ution of th ese functi ons. The ex amples al so assume that no Flash Boot Loader is present in the software. If such code is present, the EEPROM write function must also wait for any ongoing SPM command to finish.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_write

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r16) to data register

out EEDR,r16

; Write logical one to EEMWE

sbi EECR,EEMWE

; Start eeprom write by setting EEWE

sbi EECR,EEWE

ret

C Code Example

void EEPROM_write (unsigned int uiAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE));

/* Set up address and data registers */

EEAR = uiAddress;

EEDR = ucData;

/* Write logical one to EEMWE */

EECR |= (1<<EEMWE);

/* Start eeprom write by setting EEWE */

EECR |= (1<<EEWE);

}

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AT90CAN32/64/128

The next code e xampl es sho w ass embly and C funct ions for r eading the EEPR OM. Th e ex amples assume that interrupts are controlled so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEWE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned int uiAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEWE));

/* Set up address register */

EEAR = uiAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

4.3.5 Preventing EEPROM Corruption

During periods of low V too low for the CPU and the EEPROM t o operate prop erly. These is sues are the s ame as for board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First, a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation: Keep the AVR RESET ac tive (low) du ring per iods o f insu ffici ent power supp ly vo ltage. Th is ca n

be done by enabling the internal Brown-ou t Detect or (BOD ). If the de tectio n leve l of the in terna l BOD does not match the needed detection level, an external low V be used. If a reset occurs while a write operation is in progr ess, the write ope ratio n will be completed provided that the power supply voltage is sufficient.

the EEPROM data can be corrupted because the supply v oltage is

CC,

reset Protection circuit can

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4.4 I/O Memory

AT90CAN32/64/128

The I/O space definition of the AT90CAN3 2/64/128 is shown in “Reg ister Summary ” on page

405.

All AT90CAN32/64/128 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose wo rking re gisters and the I/O spa ce. I/O reg isters wi thin the ad dress rang e 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set sect ion for mo r e deta il s. W hen usi ng the I/ O spec ific com man ds IN and OU T, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O registers as data space using LD and ST instructio ns, 0x20 mu st be ad ded to these ad dresses . The AT9 0CAN32/6 4/128 is a complex microcontr ol le r with more peripheral un its t han c an be su ppo rte d within the 64 loca tion reserved in Opcode for the IN and OUT instructi ons. For th e Extended I/O space fr om 0x60 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.

For compatibility with future devices, rese rved bits should be wr itten to zero if acces sed. Reserved I/O memory addresses should never be written.

Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other AVR’s, the CBI and S BI inst ruction s will onl y operate on the spe cified bi t, and ca n theref ore be used on registers con tai nin g s uch s tatus fl ags. T he CBI a nd S BI ins truc ti ons work with re gisters 0x00 to 0x1F only.

The I/O and peripherals control registers are explained in later sections.

4.5 External Memory Interface

With all the features the External Memory Interface provides, it is well suited to operate as an interface to m em ory devi ces s uch as Exte rnal SR AM a nd F lash , a nd p eriph eral s su ch as L CDdisplay, A/D, and D/A. The main features are:

• Four different wait-state settings (including no wait-state).

• Independent wait-state setting for different extErnal Memory sectors (configurable sector

size).

• The number of bits dedicated to address high byte is selectable.

• Bus keepers on data lines to minimize current consumption (optional).

4.5.1 Overview

When the eXternal MEMory (XME M) is enabl ed, address space outs ide the in ternal SRA M becomes available us in g th e d edi ca ted Ex ter na l M emo ry p ins (s ee Fi gu re 1- 2 o n p age 5 or Fig-

ure 1-3 on page 6, Table 9-3 on page 74, Table 9-9 on page 78, and Table 9-21 on page 88).

The memory configuration is shown in Figure 4-4.

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AT90CAN32/64/128

Figure 4-4. External Memory with Sector Select

Internal memory

0x0000

ISRAM end XMem start

Lower sector

SRW01 SRW00

SRL[2..0]

4.5.2 Using the External Memory Interface

The interface consists of:

• AD7:0: Multiplexed low-order address bus and data bus.

• A15:8: High-order address bus (configurable number of bits).

• ALE: Address latch enable.

•RD

: Read strobe.

: Write strobe.

•WR

The control bits for the External Memory Interface are located in two registers, the External Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.

When the XMEM interface is enabled, the XMEM interface will override the setting in the data direction registers that correspon ds to the ports dedic ated to the XMEM in terface. Fo r details about the port override, see the alternate functions in section “I/O-Ports” on page 66. The XMEM interface will aut o-dete ct whet her an acce ss is intern al or exte rnal. If the acces s is e xternal , the XMEM interface will o utput address , data, an d the con trol s ignals o n the p orts acc ording to Fig-

ure 4-6 (this figure shows the wave forms without wait-states). When ALE goes from high-to-low,

there is a valid addr ess on AD7:0. A LE is lo w durin g a data tr ansf er. Wh en the XM EM int erfac e is enabled, also an internal access will cause activity on address, data and ALE ports, but the

and WR strobes will not toggl e during in terna l acce ss. Wh en the Exter nal Mem ory Inter face

RD is disabled, the normal pin and data direction settings are used. Note that when the XMEM interface is disabled, the address space above the internal SRAM boundary is not mapped into the internal SRAM. Figure 4-5 illustrate s how to co nnect an ex terna l SRA M to the AVR u sing an octal latch (typically “74x573” or equivalent) which is transparent when G is high.

External Memory

(0-64K x 8)

Upper sector

SRW11 SRW10

0xFFFF

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4.5.3 Address Latch Requirements

Due to the high-speed operation of the XRAM interface, the address latch must be selected with care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at conditions above these frequencies, the typical old style 74HC series latch becomes inadequate. The External Memory Interface is desi gned in com plianc e to the 74A HC seri es latch. H owever , mos t latches can be used as long they comply with the main timing parameters. The main parameters for the address latch are:

AT90CAN32/64/128

• D to Q propagation delay (t

• Data setup time before G low (t

• Data (address) hold time after G low (

The External Memory Interface is designed to guaranty minimum address hold time after G is asserted low of t

tion 26.9 on page 375. The D-to-Q propagation delay (t

= 5 ns. Refer to t

LAXX_LD

/ t

LLAXX_ST

in Table 26-7 through Table 26- 14 of Sec-

) must be taken into consideration

when calculating the access time requirement of the external component. The data setup time before G low (t

) must not exceed address va lid to AL E low (t

) minus PCB wiring delay

AVLLC

(dependent on the capacitive load).

Figure 4-5. External SRAM Connected to the AVR

D[7:0]

AD7:0

AVR

A15:8

ALE

DQ G

A[7:0]

SRAM

A[15:8] RD

4.5.4 Pull-up and Bus-keeper

The pull-ups on the A D7:0 po rt s may b e ac tiv ate d i f t he co rres po ndi ng Po rt regi s ter i s wr itte n to one. To reduce power consum pti on in sleep mo de, it is recommended to disabl e the pul l-up s by writing the Port register to zero before entering sleep.

The XMEM interface also provides a bus-keeper on the AD7:0 lines. The bus-keeper can be disabled and enabled in softwar e as d escribed i n “Ex tern al Memo ry Co ntrol Regi ster B – XMC RB”

on page 33. When enabled, the bus-keeper will ensure a defined logic level (zero or one) on the

AD7:0 bus when these lines would otherwise be tri-stated by the XMEM interface.

4.5.5 Timing

External Memory devices have different timing requirements. To meet these requirements, the AT90CAN32/64/128 XMEM interface provides four different wait-states as shown in Table 4-4. It is important to co nsider the timin g speci ficat ion of the Ex ternal M emory d evice before se lectin g the wait-state. The most important parameters are the access time for the external memory compared to the set-up requirement of the AT90CAN32/64/128. The access time for the External Memory is defin ed t o be the time from rece iv in g th e c hip se le ct/address until the data of this

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AT90CAN32/64/128

address actual ly is d riven on the bus. The acces s tim e canno t exce ed the t ime from the ALE pulse must be asserted lo w until data is stab le during a read sequence (se e t

LLRL

+ t

RLRH

- t

DVRH

in Table 26-7 th ro ugh Tabl e 26 - 14). T he di fferent wait-states are se t up in so ftwar e. As an add itional feature, it is possible to divide the exter nal memory space in two sectors with individua l wait-state settings. This makes it possible to connect two different memory devices with different timing requirem ents to the same XMEM interface . For XMEM i nterface ti ming deta ils, pleas e refer to Table 26-7 through Table 2 6-14 and Figur e 26-6 to Figure 26-9 in the “External Data

Memory Characteristics” on page 375.

Note that the XMEM interface is asynchronous and that the waveforms in the following figures are related to the internal system clock. The skew between the internal and external clock (XTAL1) is not guarantied (varies betw een device s temperature, and sup ply voltage) . Consequently, the XMEM interface is not suited for synchronous operation.

Figure 4-6. External Data Memory Cycles no Wait-state (SRWn1=0 and SRWn0=0)

System Clock (CLK

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

CPU

ALE

A15:8

DA7:0

T1 T2 T3

)

AddressPrev. addr.

Address DataPrev. data XX

DataPrev. data Address

XXXXX XXXXXXXX

DataPrev. data Address

(1)

Write

Read

Note: 1. SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper secto r) or

SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external).

Figure 4-7. External Data Memory Cycles with SRWn1 = 0 and SRWn0 = 1

System Clock (CLK

CPU

T1 T2 T3

)

(1)

ALE

A15:8

DA7:0

DA7:0 (XMBK = 0)

DA7:0 (XMBK = 1)

Address DataPrev. data XX

AddressPrev. addr.

Write

DataPrev. data Address

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Read

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