ATMEL AT89S4051 User Manual

BDTIC www.bdtic.com/ATMEL

Features

•

Compatible with MCS®51 Products

•

2K/4K Bytes of In-System Programmable (ISP) Flash Program Memory

– Serial Interface for Program Downloading – Endurance: 10,000 Write/Erase Cycles

•

2.7V to 5.5V Operating Range

•

Fully Static Operation: 0 Hz to 24 MHz (x1 and x2 Modes)

•

Two-level Program Memory Lock

•

256 x 8-bit Internal RAM

•

15 Programmable I/O Lines

•

Two 16-bit Timer/Counters

•

Six Interrupt Sources

•

Programmable Serial UART Channel

•

Direct LED Drive Outputs

•

On-chip Analog Comparator with Selectable Interrupt

•

8-bit PWM (Pulse-width Modulation)

•

Low Power Idle and Power-down Modes

•

Brownout Reset

•

Enhanced UART Serial Port with Framing Error Detection and Automatic Address Recognition

•

Internal Power-on Reset

•

Interrupt Recovery from Power-down Mode

•

Programmable and Fuseable x2 Clock Option

•

Four-level Enhanced Interrupt Controller

•

Power-off Flag

•

Flexible Programming (Byte and Page Modes)

– Page Mode: 32 Bytes/Page

•

User Serviceable Signature Page (32 Bytes)

8-bit Microcontroller with 2K/4K Bytes Flash

AT89S2051 AT89S4051

1. Description

The AT89S2051/S4051 is a low-voltage, high-performance CMOS 8-bit microcontroller with 2K/4K bytes of In-System Programmable (ISP) Flash program memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89S2051/S4051 is a powerful microcontroller which provides a highly-flexible and cost-effective solution to many embedded control applications. Moreover, the AT89S2051/S4051 is designed to be function compatible with the AT89C2051/C4051 devices, respectively.

The AT89S2051/S4051 provides the following standard features: 2K/4K bytes of Flash, 256 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a six-vector, fourlevel interrupt architecture, a full duplex enhanced serial port, a precision analog comparator, on-chip and clock circuitry. Hardware support for PWM with 8-bit resolution and 8-bit prescaler is available by reconfiguring the two on-chip timer/counters. In addition, the AT89S2051/S4051 is designed with static logic for operation down to zero frequency and supports two software-selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The power-down mode saves the RAM contents but freezes the disabling all other chip functions until the next external interrupt or hardware reset.

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The on-board Flash program memory is accessible through the ISP serial interface. Holding RST active forces the device into a serial programming interface and allows the program memory to be written to or read from, unless one or more lock bits have been activated.

2. Pin Configuration

2.1 20-lead PDIP/SOIC

3. Block Diagram

RST/VPP

(RXD) P3.0

(TXD) P3.1

XTAL2

XTAL1 (INT0) P3.2 (INT1) P3.3

(T0) P3.4 (T1) P3.5

GND

1 2 3 4 5 6 7 8 9 10

20 19 18 17 16 15 14 13 12 11

VCC P1.7 (SCK) P1.6 (MISO) P1.5 (MOSI) P1.4 P1.3 P1.2 P1.1 (AIN1) P1.0 (AIN0) P3.7

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4. Pin Description

4.1 VCC

Supply voltage.

4.2 GND

Ground.

4.3 Port 1

Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pull-ups. P1.0 and P1.1 require external pull-ups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins, they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (I

Port 1 also receives code data during Flash programming and verification.

) because of the internal pull-ups.

Port Pin Alternate Functions

AT89S2051/S4051

4.4 Port 3

P1.5 MOSI (Master data output, slave data input pin for ISP channel)

P1.6 MISO (Master data input, slave data output pin for ISP channel)

P1.7 SCK (Master clock output, slave clock input pin for ISP channel)

Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pull-ups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general-purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I

) because of the pull-ups.

Port 3 also serves the functions of various special features of the AT89S2051/S4051 as listed below:

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

P3.3 INT1

P3.4 T0 (timer 0 external input)

(external interrupt 0)

(external interrupt 1)

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P3.5 T1 (timer 1 external input)/ PWM output

Port 3 also receives some control signals for Flash programming and verification.

4.5 RST

Reset input. Holding the RST pin high for two machine cycles while the is running resets the device.

Each machine cycle takes 6 or clock cycles.

4.6 XTAL1

Input to the inverting amplifier and input to the internal clock operating circuit.

4.7 XTAL2

Output from the inverting amplifier.

5. Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip , as shown in Figure 5-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 5-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

Figure 5-1. Connections

Note: C1, C2 = 5 pF ± 5 pF for Crystals

= 5 pF ± 5 pF for Ceramic Resonators

Figure 5-2. External Clock Drive Configuration

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6. X2 Mode Description

The clock for the entire circuit and peripherals is normally divided by 2 before being used by the CPU core and peripherals. This allows any cyclic ratio (duty cycle) to be accepted on XTAL1 input. In X2 mode this divider is bypassed. Figure 6-1 shows the clock generation block diagram.

Figure 6-1. Clock Generation Block Diagram

XTAL1

X2 Mode

AT89S2051/S4051

(XTAL1)/2

XTAL

7. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table 7-1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.

OSC

State Machine: 6 Clock Cycles CPU Control

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Table 7-1. AT89S2051/S4051 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

00000000

ACC

00000000

PSW

00000000

X0X00000

11111111

00X00000

SADEN

00000000

SADDR

00000000

IPH

X0X00000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

98H

90H

88H

80H

SCON

00000000

11111111

TCON

00000000

SBUF

XXXXXXXX

TMOD

00000000

00000111

TL0

00000000

DPL

00000000

TL1

00000000

DPH

00000000

TH0

00000000

TH1

00000000

ACSR

XXX00000

CLKREG

XXXXXX0X

PCON

000X0000

9FH

97H

8FH

87H

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8. Restrictions on Certain Instructions

The AT89S2051/S4051 is an economical and cost-effective member of Atmel’s family of microcontrollers. It contains 2K/4K bytes of Flash program memory. It is fully compatible with the MCS-51 architecture, and can be programmed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind when utilizing certain instructions to program this device.

All the instructions related to jumping or branching should be restricted such that the destination address falls within the physical program memory space of the device, which is 2K/4K for the AT89S2051/S4051. This should be the responsibility of the software programmer. For example, LJMP 7E0H would be a valid instruction for the AT89S2051 (with 2K of memory), whereas LJMP 900H would not.

8.1 Branching Instructions

LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching

instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (locations 00H to 7FFH/FFFH for the AT89S2051/S4051). Violating the physical space limits may cause unknown program behavior.

CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ. With these conditional branching instructions, the same rule above applies. Again, violating the memory boundaries may cause erratic execution.

AT89S2051/S4051

For applications involving interrupts, the normal interrupt service routine address locations of the 80C51 family architecture have been preserved.

8.2 MOVX-related Instructions, Data Memory

The AT89S2051/S4051 contains 256 bytes of internal data memory. External DATA memory access is not supported in this device, nor is external PROGRAM memory execution. Therefore, no MOVX [...] instructions should be included in the program.

A typical 80C51 assembler will still assemble instructions, even if they are written in violation of the restrictions mentioned above. It is the responsibility of the user to know the physical features and limitations of the device being used and adjust the instructions used accordingly.

9. Program Memory Lock Bits

On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in Table 9-1:

Table 9-1. Lock Bit Protection Modes

Program Lock Bits

LB1 LB2 Protection Type

1 U U No program lock features.

2 P U Further programming of the Flash is disabled.

3 P P Same as mode 2, also verify is disabled.

(1)

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Note: 1. The Lock Bits can only be erased with the Chip Erase operation.

10. Reset

During reset, all I/O Registers are set to their initial values, the port pins are weakly pulled to V

, and the program starts execution from the Reset Vector, 0000H. The AT89S2051/S4051

has three sources of reset: power-on reset, brown-out reset, and external reset.

10.1 Power-On Reset

A Power-On Reset (POR) is generated by an on-chip detection circuit. The detection level is nominally 1.4V. The POR is activated whenever V cuit can be used to trigger the start-up reset or to detect a supply voltage failure in devices without a brown-out detector. The POR circuit ensures that the device is reset from power-on. When V XTAL Oscillator Bypass fuse is OFF). Only after V detection) level (see Section 10.2 ”Brown-out Reset”), the BOD delay counter starts measuring a 2-ms delay after which the Internal Reset is deasserted and the microcontroller starts executing. The built-in 2-ms delay allows the V ing, thus guaranteeing the maximum operating clock frequency. The POR signal is activated again, without any delay, when V a cold reset) will set the POF flag in PCON. Refer to Figure 10-1 for details on the POR/BOD behavior.

Figure 10-1. Power-up and Brown-out Detection Sequence

reaches the Power-on Reset threshold voltage, the Pierce Oscillator is enabled (if the

is below the detection level. The POR cir-

has also reached the BOD (brown-out

voltage to reach the minimum 2.7V level before execut-

falls below the POR threshold level. A Power-On Reset (i.e.

Level 2.7V

Min V

BOD Level 2.3V POR Level 1.4V

XTAL1

Internal RESET

POR

BOD

2.4V

1.2V

POR

(2 ms)

POR

(2 ms)

POR

(2 ms)

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10.2 Brown-out Reset

The AT89S2051/S4051 has an on-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing it to a fixed trigger level. The trigger level for the BOD is nominally 2.0V. The purpose of the BOD is to ensure that if V speed, the system will gracefully enter reset without the possibility of errors induced by incorrect execution. When V diately activated. When V microcontroller after the timeout period has expired in approximately 2 ms.

10.3 External Reset

The RST pin functions as an active-high reset input. The pin must be held high for at least two machine cycles to trigger the internal reset. RST also serves as the In-System Programming (ISP) enable input. ISP mode is enabled when the external reset pin is held high and the ISP Enable fuse is set.

AT89S2051/S4051

fails or dips while executing at

decreases to a value below the trigger level, the Brown-out Reset is imme-

increases above the trigger level, the BOD delay counter starts the

11. Clock Register

Table 11-1.

CLKREG = 8FH Reset Value = XXXX XX0XB

Not Bit Addressable

––––––PWDEXX2

Bit76543210

Symbol Function

PWDEX

CLKREG

Power-down Exit Mode. When PWDEX = 1, wake up from Power-down is externally controlled. When PWDEX = 0, wake up from Power-down is internally timed.

When X2 = 0, the frequency (at XTAL1 pin) is internally divided by 2 before it is used as the device system frequency. When X2 = 1, the divide by 2 is no longer used and the XTAL1 frequency becomes the device system frequency. This enables the user to use a 6 MHz crystal instead of a 12 MHz crystal in order to reduce EMI. The X2 bit is initialized on power-up with the value of the X2 user fuse and may be changed at runtime by software.

– Clock Register

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12. Power Saving Modes

The AT89S2051/S4051 supports two power-reducing modes: Idle and Power-down. These modes are accessed through the PCON register.

12.1 Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU state is preserved in its entirety, including the RAM, stack pointer, program counter, program status word, and accumulator. The Port pins hold the logical states they had at the time that Idle was activated. Idle mode leaves the peripherals running in order to allow them to wake up the CPU when an interrupt is generated. Timer 0, Timer 1, and the UART will continue to function during Idle mode. The analog comparator is disabled during Idle. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode with an interrupt, the interrupt will immediately be serviced, and following RETI, the next instruction to be executed will be the one following the instruction that put the device into Idle.

P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pullups are used.

12.2 Power-down Mode

Setting the PD bit in PCON enters Power-down mode. Power-down mode stops the and powers down the Flash memory in order to minimize power consumption. Only the power-on circuitry will continue to draw power during Power-down. During Power-down the power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be retained; however, the SFR contents are not guaranteed once V by external reset, power-on reset, or certain interrupts.

has been reduced. Power-down may be exited

The user should not attempt to enter (or re-enter) the power-down mode for a minimum of 4 µs until after one of the following conditions has occurred: Start of code execution (after any type of reset), or Exit from power-down mode.

12.3 Interrupt Recovery from Power-down

Two external interrupts may be configured to terminate Power-down mode. External interrupts INT0

(P3.2) and INT1 (P3.3) may be used to exit Power-down. To wake up by external interrupt

INT0

or INT1, the interrupt must be enabled and configured for level-sensitive operation.

When terminating Power-down by an interrupt, two different wake up modes are available. When PWDEX in CLKREG.2 is zero, the wake up period is internally timed. At the falling edge on the interrupt pin, Power-down is exited, the is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate and the CPU will not resume execution until after the timer has counted for nominally 2 ms. After the timeout period the interrupt service routine will begin. To prevent the interrupt from re-triggering, the ISR should disable the interrupt before returning. The interrupt pin should be held low until the device has timed out and begun executing.

When PWDEX = 1 the wakeup period is controlled externally by the interrupt. Again, at the falling edge on the interrupt pin, Power-down is exited and the is restarted. However, the internal clock will not propagate and CPU will not resume execution until the rising edge of the interrupt pin. After the rising edge on the pin, the interrupt service routine will begin. The interrupt should be held low long enough for the to stabilize.

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12.4 Reset Recovery from Power-down

Wakeup from Power-down through an external reset is similar to the interrupt with PWDEX = 0. At the rising edge of RST, Power-down is exited, the is restarted, and an internal timer begins counting. The internal clock will not be allowed to propagate to the CPU until after the timer has counted for nominally 2 ms. The RST pin must be held high for longer than the timeout period to ensure that the device is reset properly. The device will begin executing once RST is brought low.

It should be noted that when idle is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory.

P1.0 and P1.1 should be set to “0” if no external pull-ups are used, or set to “1” if external pullups are used.

AT89S2051/S4051

Table 12-1.

PCON = 87H Reset Value = 000X 0000B

Not Bit Addressable

SMOD1 SMOD0 PWMEN POF GF1 GF0 PD IDL

Bit76543210

Symbol Function

SMOD1 Double Baud Rate bit. Doubles the baud rate of the UART in modes 1, 2, or 3.

SMOD0

PWMEN

POF

GF1, GF0 General-purpose Flags

PD Power Down bit. Setting this bit activates power down operation.

IDL Idle Mode bit. Setting this bit activates idle mode operation

PCON

– Power Control Register

Frame Error Select. When SMOD0 = 0, SCON.7 is SM0. When SMOD0 = 1, SCON.7 is FE. Note that FE will be set after a frame error regardless of the state of SMOD0.

Pulse Width Modulation Enable. When PWMEN = 1, Timer 0 and Timer 1 are configured as an 8-bit PWM counter with 8-bit auto-reload prescaler. The PWM outputs on T1 (P3.5).

Power Off Flag. POF is set to “1” during power up (i.e. cold reset). It can be set or reset under software control and is not affected by RST or BOD (i.e. warm resets).

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13. Interrupts

The AT89S2051/S4051 provides 6 interrupt sources: two external interrupts, two timer interrupts, a serial port interrupt, and an analog comparator interrupt. These interrupts and the system reset each have a separate program vector at the start of the program memory space. Each interrupt source can be individually enabled or disabled by setting or clearing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA, which disables all interrupts.

Each interrupt source can be individually programmed to one of four priority levels by setting or clearing bits in the interrupt priority registers IP and IPH. An interrupt service routine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of the same or lower priority. The highest priority interrupt cannot be interrupted by any other interrupt source. If two requests of different priority levels are pending at the end of an instruction, the request of higher priority level is serviced. If requests of the same priority level are pending at the end of an instruction, an internal polling sequence determines which request is serviced. The polling sequence is based on the vector address; an interrupt with a lower vector address has higher priority than an interrupt with a higher vector address. Note that the polling sequence is only used to resolve pending requests of the same priority level.

The External Interrupts INT0 depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these interrupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears the flag that generated an external interrupt only if the interrupt was transition-activated. If the interrupt was level activated, then the external requesting source (rather than the on-chip hardware) controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is generated, the on-chip hardware clears the flag that generated it when the service routine is vectored to.

The Serial Port Interrupt is generated by the logical OR of RI and TI in SCON. Neither of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine normally must determine whether RI or TI generated the interrupt, and the bit must be cleared in software.

The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware when the service routine is vectored to and must be cleared by software.

Most of the bits that generate interrupts can be set or cleared by software, with the same result as though they had been set or cleared by hardware. That is, interrupts can be generated and pending interrupts can be canceled in software.

Interrupt Source Vector Address

System Reset RST or POR or BOD 0000H

and INT1 can each be either level-activated or transition-activated,

External Interrupt 0 IE0 0003H

Timer 0 Overflow TF0 000BH

External Interrupt 1 IE1 0013H

Timer 1 Overflow TF1 001BH

Serial Port RI or TI 0023H

Analog Comparator CF 0033H

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14. Interrupt Registers

AT89S2051/S4051

Table 14-1.

IE = A8H Reset Value = 00X0 0000B

Bit Addressable

EA EC – ES ET1 EX1 ET0 EX0

Bit76543210

Symbol Function

EC Comparator Interrupt Enable

ES Serial Port Interrupt Enable

ET1 Timer 1 Interrupt Enable

EX1 External Interrupt 1 Enable

ET0 Timer 0 Interrupt Enable

EX0 External Interrupt 0 Enable

Table 14-2.

IP = B8H Reset Value = X0X0 0000B

Bit Addressable

– PC – PS PT1 PX1 PT0 PX0

Bit76543210

– Interrupt Enable Register

Global enable/disable. All interrupts are disabled when EA = 0. When EA = 1, each interrupt source is enabled/disabled by setting/clearing its own enable bit.

– Interrupt Priority Register

Symbol Function

PC Comparator Interrupt Priority Low

PS Serial Port Interrupt Priority Low

PT1 Timer 1 Interrupt Priority Low

PX1 External Interrupt 1 Priority Low

PT0 Timer 0 Interrupt Priority Low

PX0 External Interrupt 0 Priority Low

Table 14-3.

IPH = B7H Reset Value = X0X0 0000B

Not Bit Addressable

– PCH – PSH PT1H PX1H PT0H PX0H

Bit76543210

Symbol Function

PCH Comparator Interrupt Priority High

PSH Serial Port Interrupt Priority High

PT1H Timer 1 Interrupt Priority High

PX1H External Interrupt 1 Priority High

PT0H Timer 0 Interrupt Priority High

PX0H External Interrupt 0 Priority High

IPH

– Interrupt Priority High Register

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15. Timer/Counters

The AT89S2051/S4051 have two 16-bit Timer/Counters: Timer 0 and Timer 1. The Timer/Counters are identical to those in the AT89C2051/C4051. For more detailed information on the Timer/Counter operation, please click on the document link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

16. Pulse Width Modulation

Timer 0 and Timer 1 may be configured as an 8-bit pulse width modulator by setting the PWMEN bit in PCON. The generated waveform is output on the Timer 1 input pin, T1. In PWM mode Timer 0 acts as an 8-bit prescaler to select the PWM timebase. Timer 0 is forced into Mode 2 (8bit auto-reload) by PWMEN and the value in TH0 will determine the clock division from 0 (FFh) to 256 (00h). Timer 1 acts as the 8-bit PWM counter. TL1 counts once on every overflow from TL0. TH1 stores the 8-bit pulse width value. On the FFh-->00h overflow of TL1, the PWM output is set high. When the count in TL1 matches the value in TH1, the PWM output is set low. Therefore, the output pulse width is proportional to the value in TH1. To prevent glitches, writes to TH1 only take effect on the FFh-->00h overflow of TL1. However, a read from TH1 will read the new value at any time after a write to TH1. See Figure 16-1 for PWM waveform example.

Figure 16-1. Pulse Width Modulation (PWM) Output Waveform

Counter Value (TL1)

Compare Value (TH1)

PWM Output (T1)

Figure 16-2. Timer 0/1 Pulse Width Modulation Mode

TH1

TH0

÷÷

OCR

P3.

PWM

TL0 counts once every machine cycle (1 machine cycle = 12 clocks in X1 mode) and TH0 is the reload value for when TL0 overflows. Every time TL0 overflows TL1 increments by one, with TL0 overflowing after counting 256 minus TH0 machine cycles.

To calculate the pulse width for the PWM output on pin T1, users should use the following formula:

TH1 * (256 - TH0) * (1/clock_freq) * 12 = Pulse Width

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