Atmel AT89LS52 User Manual
Features
• Compatible with MCS-51
• 8K Bytes of In-System Programmable (ISP) Flash Memory
– Endurance: 1000 Write/Erase Cycles
• 2.7V to 4.0V Operating Range
• Fully Static Operation: 0 Hz to 16 MHz
• Three-level Program Memory Lock
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Full Duplex UART Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Flexible ISP Programming (Byte and Page Modes)
®
Products
8-bit
Low-Voltage
Microcontroller
with 8K Bytes
Description
The AT89LS52 is a low-voltage, high-performance CMOS 8-bit microcontroller with 8K
bytes of in-system programmable Flash memory. The device is manufactured using
Atmel’s high-density nonvolatile memory technology and is compatible with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the program
memory to be reprogrammed in-system or by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with in-system programmable Flash on a
monolithic chip, the Atmel AT89LS52 is a powerful microcontroller which provides a
highly-flexible and cost-effective solution to many embedded control applications.
The AT89LS52 provides the following standard features: 8K bytes of Flash, 256 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, three 16-bit timer/counters, a
six-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89LS52 is designed with static logic for operation
down to zero frequency and supports two software selectable power saving modes.
The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and
interrupt system to continue functioning. The Power-down mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external
interrupt or hardware reset.
In-System
Programmable
Flash
AT89LS52
Preliminary
Rev. 2601A–12/01
1
Pin Configurations
PDIP
P1.2
P1.3
P1.4
RST
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
(T2) P1.0
(T2 EX) P1.1
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2
XTAL1
GND
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
PLCC
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)NCVCC
6
5
4
3
2
7
8
9
10
11
12
13
14
15
16
17
1819202122232425262728
GND
XTAL2
XTAL1
(RD) P3.7
(WR) P3.6
P0.0 (AD0)
1
4443424140
NC
(A8) P2.0
(A9) P2.1
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
39
38
37
36
35
34
33
32
31
30
29
(A10) P2.2
(A11) P2.3
(A12) P2.4
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
(MOSI) P1.5
(MISO) P1.6
(SCK) P1.7
RST
(RXD) P3.0
NC
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3
(T0) P3.4
(T1) P3.5
TQFP
P1.4
P1.3
P1.2
P1.1 (T2 EX)
P1.0 (T2)NCVCC
4443424140393837363534
1
2
3
4
5
6
7
8
9
10
11
1213141516171819202122
GND
XTAL1
GND
XTAL2
(RD) P3.7
(WR) P3.6
P0.0 (AD0)
(A8) P2.0
(A9) P2.1
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
(A10) P2.2
(A11) P2.3
(A12) P2.4
33
32
31
30
29
28
27
26
25
24
23
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
2
AT89LS52
2601A–12/01
Block Diagram
AT89LS52
V
CC
GND
B
REGISTER
RAM ADDR.
REGISTER
P0.0 - P0.7
PORT 0 DRIVERS
RAM
ACC
TMP2 TMP1
PORT 0
LATCH
PORT 2 DRIVERS
PORT 2
LATCH
POINTER
P2.0 - P2.7
FLASH
STACK
PROGRAM
ADDRESS
REGISTER
BUFFER
PSEN
ALE/PROG
EA / V
RST
PC
ALU
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PSW
TIMING
AND
PP
CONTROL
OSC
INSTRUCTION
REGISTER
WATCH
DOG
PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
ISP
PORT
INCREMENTER
PROGRAM
COUNTER
DUAL DPTR
PROGRAM
LOGIC
2601A–12/01
3
Pin Description
VCC Supply voltage.
GND Ground.
Port 0 Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight
TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance
inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during
accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes
during program verification. External pull-ups are required during program verification.
Port 1 Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being
pulled low will source current (I
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input
(P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the following table.
Port 1 also receives the low-order address bytes during Flash programming and verification.
) because of the internal pull-ups.
IL
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
P1.5 MOSI (used for In-System Programming)
P1.6 MISO (used for In-System Programming)
P1.7 SCK (used for In-System Programming)
Port 2 Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being
pulled low will source current (I
) because of the internal pull-ups.
IL
Port 2 emits the high-order address byte during fetches from external program memory and
during accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash programming and verification.
Port 3 Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the
internal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (I
) because of the pull-ups.
IL
Port 3 receives some control signals for Flash programming and verification.
4
AT89LS52
2601A–12/01
AT89LS52
Port 3 also serves the functions of various special features of the AT89LS52, as shown in the
following table.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD (external data memory read strobe)
(external interrupt 0)
(external interrupt 1)
(external data memory write strobe)
RST Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state
of bit DISRTO, the RESET HIGH out feature is enabled.
ALE/PROG
Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG
) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may
be used for external timing or clocking purposes. Note, however, that one ALE pulse is
skipped during each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled
high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution
mode.
PSEN
Program Store Enable (PSEN) is the read strobe to external program memory.
When the AT89LS52 is executing code from external program memory, PSEN
twice each machine cycle, except that two PSEN
activations are skipped during each access
is activated
to external data memory.
/VPP External Access Enable. EA must be strapped to GND in order to enable the device to fetch
EA
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA
EA
should be strapped to VCC for internal program executions.
This pin also receives the 12-volt programming enable voltage (V
will be internally latched on reset.
) during Flash
PP
programming.
XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
XTAL2 Output from the inverting oscillator amplifier.
2601A–12/01
5
Table 1. AT89LS52 SFR Map and Reset Values
0F8H 0FFH
0F0H
0E8H 0EFH
0E0H
0D8H 0DFH
0D0H
0C8H
0C0H 0C7H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111SP00000111
T2MOD
XXXXXX00
SBUF
XXXXXXXX
TMOD
00000000
RCAP2L
00000000
AUXR1
XXXXXXX0
TL0
00000000
DP0L
00000000
RCAP2H
00000000
TL1
00000000
DP0H
00000000
TL2
00000000
TH0
00000000
DP1L
00000000
TH2
00000000
TH1
00000000
DP1H
00000000
WDTRST
XXXXXXXX
AUXR
XXX00XX0
PCON
0XXX0000
0F7H
0E7H
0D7H
0CFH
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
6
AT89LS52
2601A–12/01
AT89LS52
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read
accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea-
tures. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 2) and T2MOD (shown in
Table ) for Timer 2. The register pair (RCAP2H, RCAP2L) are the Capture/Reload registers for Timer 2 in 16-bit capture
mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six
interrupt sources in the IP register.
Table 2. T2CON – Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2
76543210
Symbol Function
TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1
or TCLK = 1.
EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.
When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be
cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port
Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port
Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer
2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
CP/RL2 Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When
either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
CP/RL2
2601A–12/01
7
Table 3. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data
Pointer Registers are provided: DP0 at SFR address locations 82H-83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1
selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before
accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power
up. It can be set and rest under software control and is not affected by reset.
Table 4. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
––– – – – –DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
8
AT89LS52
2601A–12/01
AT89LS52
Memory Organization
MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.
Program Memory If the EA pin is connected to GND, all program fetches are directed to external memory.
On the AT89LS52, if EA
1FFFH are directed to internal memory and fetches to addresses 2000H through FFFFH are
directed to external memory.
is connected to VCC, program fetches to addresses 0000H through
Data Memory The AT89LS52 implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel
address space to the Special Function Registers. This means that the upper 128 bytes have
the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode
used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the
SFR space. Instructions which use direct addressing access of the SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H
(which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the
following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at
address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data
RAM are available as stack space.
2601A–12/01
9
Watchdog Timer (One-time Enabled with Reset-out)
The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a
user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H).
When the WDT is enabled, it will increment every machine cycle while the oscillator is running.
The WDT timeout period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST pin.
Using the WDT To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment
every machine cycle while the oscillator is running. This means the user must reset the WDT
at least every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written.
When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET
pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it
should be serviced in those sections of code that will periodically be executed within the time
required to prevent a WDT reset.
WDT During Power-down and Idle
In Power-down mode the oscillator stops, which means the WDT also stops. While in Powerdown mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89LS52 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not
started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down mode.
To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best
to reset the WDT just before entering Power-down mode.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit =
0) as the default state. To prevent the WDT from resetting the AT89LS52 while in IDLE mode,
the user should always set up a timer that will periodically exit IDLE, service the WDT, and
reenter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.
UART The UART in the AT89LS52 operates the same way as the UART in the AT89C51 and
AT89C52. For further information on the UART operation, refer to the ATMEL Web site
(http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash
Microcontroller’, then ‘Product Overview’.
10
AT89LS52
2601A–12/01
AT89LS52
Timer 0 and 1 Timer 0 and Timer 1 in the AT89LS52 operate the same way as Timer 0 and Timer 1 in the
AT89C51 and AT89C52. For further information on the timers’ operation, refer to the ATMEL
Web site (http://www.atmel.com). From the home page, select ‘Products’, then ‘8051-Architecture Flash Microcontroller’, then ‘Product Overview’.
Timer 2 Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The
type of operation is selected by bit C/T2
three operating modes: capture, auto-reload (up or down counting), and baud rate generator.
The modes are selected by bits in T2CON, as shown in Table . Timer 2 consists of two 8-bit
registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine
cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the
oscillator frequency.
Table 5. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
in the SFR T2CON (shown in Table 2). Timer 2 has
X X 0 (Off)
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corresponding external input pin, T2. In this function, the external input is sampled during S5P2 of
every machine cycle. When the samples show a high in one cycle and a low in the next cycle,
the count is incremented. The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24
of the oscillator frequency. To ensure that a given level is sampled at least once before it
changes, the level should be held for at least one full machine cycle.
Capture Mode In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2
is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be
used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to0 transition at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit
EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture
mode is illustrated in Figure 1.
2601A–12/01
11
Figure 1. Timer in Capture Mode
OSC
T2EX PIN
Auto-reload (Up or Down Counter)
T2 PIN
÷12
C/T2 = 0
TRANSITION
DETECTOR
C/T2 = 1
EXEN2
CONTROL
TR2
CAPTURE
CONTROL
TH2 TL2
RCAP2LRCAP2H
EXF2
TF2
OVERFLOW
TIMER 2
INTERRUPT
Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload
mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR
T2MOD (see Table ). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count
up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX
pin.
Figure 2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options
are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then
sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded
with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture ModeRCAP2H
and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by
an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2
bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
12
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 2. In this mode,
the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up.
The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit
value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2,
respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal
the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes
0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit
of resolution. In this operating mode, EXF2 does not flag an interrupt.
AT89LS52
2601A–12/01
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