ATMEL AT89LS51 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• Compatible with MCS

• 4K Bytes of In-System Programmable (ISP) Flash Memory

– Endurance: 1000 Write/Erase Cycles

• 2.7V to 4.0V Operating Range

• Fully Static Operation: 0 Hz to 16 MHz

• Three-level Program Memory Lock

• 128 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Two 16-bit Timer/Counters

• Six Interrupt Sources

• Full Duplex UART Serial Channel

• Low-power Idle and Power-down Modes

• Interrupt Recovery from Power-down Mode

• Watchdog Timer

• Dual Data Pointer

• Power-off Flag

• Flexible ISP Programming (Byte and Page Mode)

• Green (Pb/Halide-free) Packaging Option

®

-51 Products

8-bit
Low-Voltage
Microcontroller
with 4K Bytes
In-System
Programmable

1. Description

The AT89LS51 is a low-voltage, high-performance CMOS 8-bit microcontroller with
4K bytes of in-system programmable Flash memory. The device is manufactured
using Atmel’s high-density nonvolatile memory technology and is compatible with the
industry-standard 80C51 instruction set and pinout. The on-chip Flash allows the pro­gram memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with in-system programma­ble Flash on a monolithic chip, the Atmel AT89LS51 is a powerful microcontroller
which provides a highly-flexible and cost-effective solution to many embedded control
applications.

The AT89LS51 provides the following standard features: 4K bytes of Flash, 128 bytes
of RAM, 32 I/O lines, Watchdog timer, two data pointers, two 16-bit timer/counters, a
five-vector two-level interrupt architecture, a full duplex serial port, on-chip oscillator,
and clock circuitry. In addition, the AT89LS51 is designed with static logic for opera­tion down to zero frequency and supports two software selectable power saving
modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial
port, and interrupt system to continue functioning. The Power-down mode saves the
RAM contents but freezes the oscillator, disabling all other chip functions until the next
external interrupt or hardware reset.

Flash

AT89LS51

3053B–MICRO–3/05

2. Pin Configurations

2.1 40-lead PDIP

P1.0
P1.1

P1.2
P1.3

P1.4
(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

RST

(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2
XTAL1

GND

2.2 44-lead TQFP

P1.4

P1.3

4443424140393837363534

RST

(T0) P3.4
(T1) P3.5

1
2
3
4
5
6

NC

7
8
9
10
11

1213141516171819202122

(RD) P3.7

(WR) P3.6

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20

P1.2

XTAL2

P1.1

P1.0 NCVCC

GND

XTAL1

GND

40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21

P0.0 (AD0)

(A8) P2.0

(A9) P2.1

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

(A10) P2.2

(A11) P2.3

(A12) P2.4

33
32
31
30
29
28
27
26
25
24
23

P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

2.3 44-lead PLCC

P1.4

65432

(MOSI) P1.5
(MISO) P1.6

(SCK) P1.7

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

7
8
9
10

RST

11
12

NC

13
14
15
16
17

1819202122232425262728

(WR) P3.6

2.4 42-lead PDIP

RST
(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(WR) P3.6

(RD) P3.7

XTAL2
XTAL1

GND

PWRGND

(A8) P2.0

(A9) P2.1
(A10) P2.2
(A11) P2.3
(A12) P2.4
(A13) P2.5
(A14) P2.6
(A15) P2.7

P1.3

P1.2

P1.1

XTAL2

XTAL1

(RD) P3.7

1
2

3

4
5
6
7

8

9
10
11
12
13
14
15
16
17
18
19
20
21

P1.0 NCVCC

1

4443424140

NC

GND

(A8) P2.0

42
41
40

39
38
37
36
35
34
33
32
31
30

29
28
27
26
25
24
23
22

P0.0 (AD0)

P0.1 (AD1)

P0.2 (AD2)

(A9) P2.1

(A10) P2.2

(A11) P2.3

P1.7 (SCK)
P1.6 (MISO)
P1.5 (MOSI)
P1.4
P1.3
P1.2
P1.1
P1.0
VDD
PWRVDD
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN

P0.3 (AD3)

39

P0.4 (AD4)

38

P0.5 (AD5)

37

P0.6 (AD6)

36

P0.7 (AD7)

35

EA/VPP

34

NC

33

ALE/PROG

32

PSEN

31

P2.7 (A15)

30

P2.6 (A14)

29

P2.5 (A13)

(A12) P2.4

2

AT89LS51

3053B–MICRO–3/05

3. Block Diagram

AT89LS51

V

CC

GND

B

REGISTER

RAM ADDR.

REGISTER

P0.0 - P0.7

PORT 0 DRIVERS

RAM

ACC

TMP2 TMP1

ALU

PORT 0

LATCH

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PSEN

ALE/PROG

EA / V

RST

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PROGRAM

PSW

TIMING

AND

PP

CONTROL

OSC

INSTRUCTION

REGISTER

WATCH

DOG

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

ISP

PORT

COUNTER

DUAL DPTR

PROGRAM

LOGIC

3053B–MICRO–3/05

3

4. Pin Description

4.1 VCC

Supply voltage.

4.2 GND

Ground.

4.3 Port 0

Port 0 is an 8-bit open drain bidirectional I/O port. As an output port, each pin can sink eight TTL
inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.

Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses
to external program and data memory. In this mode, P0 has internal pull-ups.

Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur­ing program verification. External pull-ups are required during program verification.

4.4 Port 1

Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 1 output buffers can
sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low
will source current (I

Port 1 also receives the low-order address bytes during Flash programming and verification.

) because of the internal pull-ups.

IL

4.5 Port 2

Port Pin Alternate Functions

P1.5 MOSI (used for In-System Programming)

P1.6 MISO (used for In-System Programming)

P1.7 SCK (used for In-System Programming)

Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 2 output buffers can
sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low
will source current (I

Port 2 emits the high-order address byte during fetches from external program memory and dur­ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this
application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external
data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special
Function Register.

Port 2 also receives the high-order address bits and some control signals during Flash program­ming and verification.

) because of the internal pull-ups.

IL

4

AT89LS51

3053B–MICRO–3/05

4.6 Port 3

AT89LS51

Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. The Port 3 output buffers can
sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low
will source current (I

Port 3 receives some control signals for Flash programming and verification.

Port 3 also serves the functions of various special features of the AT89LS51, as shown in the
following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

) because of the pull-ups.

IL

4.7 RST

4.8 ALE/PROG

P3.2 INT0

P3.3 INT1 (external interrupt 1)

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

P3.7 RD

(external interrupt 0)

(external data memory write strobe)

(external data memory read strobe)

Reset input. A high on this pin for two machine cycles while the oscillator is running resets the
device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO
bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit
DISRTO, the RESET HIGH out feature is enabled.

Address Latch Enable (ALE) is an output pulse for latching the low byte of the address during
accesses to external memory. This pin is also the program pulse input (PROG

) during Flash

programming.

In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be
used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur­ing each access to external data memory.

4.9 PSEN

3053B–MICRO–3/05

If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set,
ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high.
Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

Program Store Enable (PSEN) is the read strobe to external program memory.

When the AT89LS51 is executing code from external program memory, PSEN
each machine cycle, except that two PSEN

activations are skipped during each access to exter-

is activated twice

nal data memory.

5

4.10 EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch
code from external program memory locations starting at 0000H up to FFFFH. Note, however,
that if lock bit 1 is programmed, EA

should be strapped to VCC for internal program executions.

EA

will be internally latched on reset.

This pin also receives the 12-volt programming enable voltage (V

4.11 XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

4.12 XTAL2

Output from the inverting oscillator amplifier

5. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in

Table 5-1.

Note that not all of the addresses are occupied, and unoccupied addresses may not be imple­mented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.

) during Flash programming.

PP

6

AT89LS51

3053B–MICRO–3/05

AT89LS51

Table 5-1. AT89LS51 SFR Map and Reset Values

0F8H 0FFH

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H 0CFH

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111SP00000111

SBUF

XXXXXXXX

TMOD

00000000

AUXR1

XXXXXXX0

TL0

00000000

DP0L

00000000

TL1

00000000

DP0H

00000000

TH0

00000000

DP1L

00000000

TH1

00000000

DP1H

00000000

WDTRST

XXXXXXXX

AUXR

XXX00XX0

PCON

0XXX0000

0F7H

0E7H

0D7H

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new fea­tures. In that case, the reset or inactive values of the new bits will always be 0.

Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the five
interrupt sources in the IP register.

7

3053B–MICRO–3/05

Table 5-2. AUXR: Auxiliary Register

AUXR Address = 8EH Reset Value = XXX00XX0B

Not Bit
Addressable

– – – WDIDLE DISRTO – – DISALE

Bit

– Reserved for future expansion

DISALE Disable/Enable ALE

DISRTO Disable/Enable Reset out

WDIDLE Disable/Enable WDT in IDLE mode

765 4 3 2 1 0

DISALE
Operating Mode

0 ALE is emitted at a constant rate of 1/6 the oscillator frequency

1 ALE is active only during a MOVX or MOVC instruction

DISRTO

0 Reset pin is driven High after WDT times out

1 Reset pin is input only

WDIDLE

0 WDT continues to count in IDLE mode

1 WDT halts counting in IDLE mode

Dual Data Pointer Registers: To facilitate accessing both internal and external data memory,
two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H­83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1.
The user should always initialize the DPS bit to the appropriate value before accessing the
respective Data Pointer Register.

Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF
is set to “1” during power up. It can be set and rest under software control and is not affected by
reset.

8

AT89LS51

3053B–MICRO–3/05

Table 5-3. AUXR1: Auxiliary Register 1

AUXR1
Address = A2H

Not Bit
Addressable

––––– – – DPS

Bit 7 6 5 4 3 2 1 0

– Reserved for future expansion

DPS Data Pointer Register Select

DPS

0 Selects DPTR Registers DP0L, DP0H

1 Selects DPTR Registers DP1L, DP1H

6. Memory Organization

MCS-51 devices have a separate address space for Program and Data Memory. Up to 64K
bytes each of external Program and Data Memory can be addressed.

AT89LS51

Reset Value = XXXXXXX0B

6.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.

On the AT89LS51, if EA
FFFH are directed to internal memory and fetches to addresses 1000H through FFFFH are
directed to external memory.

is connected to VCC, program fetches to addresses 0000H through

6.2 Data Memory

The AT89LS51 implements 128 bytes of on-chip RAM. The 128 bytes are accessible via direct
and indirect addressing modes. Stack operations are examples of indirect addressing, so the
128 bytes of data RAM are available as stack space.

7. Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to
software upsets. The WDT consists of a 14-bit counter and the Watchdog Timer Reset
(WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user
must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When
the WDT is enabled, it will increment every machine cycle while the oscillator is running. The
WDT timeout period is dependent on the external clock frequency. There is no way to disable
the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over­flows, it will drive an output RESET HIGH pulse at the RST pin.

3053B–MICRO–3/05

9

7.1 Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register
(SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH
and 0E1H to WDTRST to avoid a WDT overflow. The 14-bit counter overflows when it reaches
16383 (3FFFH), and this will reset the device. When the WDT is enabled, it will increment every
machine cycle while the oscillator is running. This means the user must reset the WDT at least
every 16383 machine cycles. To reset the WDT the user must write 01EH and 0E1H to
WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When
WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse dura­tion is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be
serviced in those sections of code that will periodically be executed within the time required to
prevent a WDT reset.

7.2 WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power­down mode, the user does not need to service the WDT. There are two methods of exiting
Power-down mode: by a hardware reset or via a level-activated external interrupt, which is
enabled prior to entering Power-down mode. When Power-down is exited with hardware reset,
servicing the WDT should occur as it normally does whenever the AT89LS51 is reset. Exiting
Power-down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent
the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until
the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for
the interrupt used to exit Power-down mode.

8. UART

9. Timer 0 and 1

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to
reset the WDT just before entering Power-down mode.

Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether
the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0)
as the default state. To prevent the WDT from resetting the AT89LS51 while in IDLE mode, the
user should always set up a timer that will periodically exit IDLE, service the WDT, and reenter
IDLE mode.

With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count
upon exit from IDLE.

The UART in the AT89LS51 operates the same way as the UART in the AT89C51. For further
information on the UART operation, please click on the document link below:

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

Timer 0 and Timer 1 in the AT89LS51 operate the same way as Timer 0 and Timer 1 in the
AT89C51. For further information on the timers’ operation, please click on the document link
below:

10

http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF

AT89LS51

3053B–MICRO–3/05