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AT89C55WD
User Manual
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ATMEL AT89C55WD User Manual

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Features

• Compatible with MCS
• 20K Bytes of Reprogrammable Flash Memory
• Endurance: 1000 Write/Erase Cycles
• 4V to 5.5V Operating Range
• Fully Static Operation: 0 Hz to 33 MHz
• 256 x 8-bit Internal RAM
• 32 Programmable I/O Lines
• Three 16-bit Timer/Counters
• Eight Interrupt Sources
• Programmable Serial Channel
• Low-power Idle and Power-down Modes
• Interrupt Recovery from Power-down Mode
• Hardware Watchdog Timer
• Dual Data Pointer
• Power-off Flag
• Green (Pb/Halide-free) Packaging Option
®
-51 Products

1. Description

The AT89C55WD is a low-power, high-performance CMOS 8-bit microcontroller with 20K bytes of Flash programmable read only memory and 256 bytes of RAM. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is compatible with the industry standard 80C51 and 80C52 instruction set and pinout. The on-chip Flash allows the program memory to be user programmed by a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C55WD is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications.
8-bit Microcontroller with 20K Bytes Flash
AT89C55WD
The AT89C55WD provides the following standard features: 20K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three 16-bit timer/counters, a six-vector, two-level interrupt architecture, a full-duplex serial port, on-chip oscillator, and clock circuitry. In addition, the AT89C55WD is designed with static logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port, and interrupt system to con­tinue functioning. The Power-down Mode saves the RAM contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset.
1921C–MICRO–3/05

2. Pin Configurations

2.1 44A – 44-lead TQFP
2.2 44J – 44-lead PLCC
(RXD) P3.0
(TXD) P3.1 (INT0) P3.2 (INT1) P3.3
(T0) P3.4 (T1) P3.5
P1.5 P1.6 P1.7 RST
(RXD) P3.0
NC (TXD) P3.1 (INT0) P3.2 (INT1) P3.3
(T0) P3.4 (T1) P3.5
P1.4
P1.3
P1.2
P1.1 (T2 EX)
4443424140393837363534
1
P1.5
2
P1.6
3
P1.7
4
RST
5 6
NC
7 8 9 10 11
1213141516171819202122
XTAL2
XTAL1
(RD) P3.7
(WR) P3.6
P1.4
P1.3
P1.2
P1.1 (T2 EX)
65432
7 8 9 10 11 12 13 14 15 16 17
1819202122232425262728
XTAL2
XTAL1
(RD) P3.7
(WR) P3.6
P1.0 (T2)NCVCC
GND
GND
(A8) P2.0
P1.0 (T2)NCVCC
1
4443424140
NC
GND
(A8) P2.0
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
(A9) P2.1
(A10) P2.2
(A11) P2.3
P0.0 (AD0)
P0.1 (AD1)
(A9) P2.1
(A10) P2.2
P0.3 (AD3)
33 32 31 30 29 28 27 26 25 24 23
(A12) P2.4
P0.2 (AD2)
P0.3 (AD3)
39 38 37 36 35 34 33 32 31 30 29
(A11) P2.3
(A12) P2.4
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP NC ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13)
2.3 40P6 – 40-lead PDIP
2
AT89C55WD
(T2) P1.0
(T2EX) P1.1
P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
RST (RXD) P3.0 (TXD) P3.1 (INT0) P3.2 (INT1) P3.3
(T0) P3.4 (T1) P3.5
(WR) P3.6
(RD) P3.7
XTAL2 XTAL1
GND
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) EA/VPP ALE/PROG PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
1921C–MICRO–3/05

3. Block Diagram

AT89C55WD
V
CC
GND
RAM ADDR.
REGISTER
B
REGISTER
ACC
TMP2
P0.0 - P0.7
PORT 0 DRIVERS
RAM
ALU
PORT 0
LATCH
TMP1
PORT 2 DRIVERS
PORT 2
LATCH
POINTER
P2.0 - P2.7
QUICK FLASH
STACK
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PSEN
ALE/PROG
EA / V
RST
INTERRUPT, SERIAL PORT,
AND TIMER BLOCKS
PROGRAM
PSW
TIMING
AND
PP
CONTROL
OSC
INSTRUCTION
REGISTER
WATCH
DOG
PORT 1
LATCH
PORT 1 DRIVERS
P1.0 - P1.7
PORT 3
LATCH
PORT 3 DRIVERS
P3.0 - P3.7
COUNTER
DUAL DPTR
1921C–MICRO–3/05
3

4. Pin Description

4.1 VCC

Supply voltage.

4.2 GND

Ground.

4.3 Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an output port, each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high-impedance inputs.
Port 0 can also be configured to be the multiplexed low-order address/data bus during accesses to external program and data memory. In this mode, P0 has internal pull-ups.
Port 0 also receives the code bytes during Flash programming and outputs the code bytes dur­ing program verification. External pull-ups are required during program verification.

4.4 Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 1 output buffers can sink/source four TTL inputs. When 1s are written to Port 1 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 1 pins that are externally being pulled low will source current (I
In addition, P1.0 and P1.1 can be configured to be the timer/counter 2 external count input (P1.0/T2) and the timer/counter 2 trigger input (P1.1/T2EX), respectively, as shown in the follow­ing table.
) because of the internal pull-ups.
IL

4.5 Port 2

Port 1 also receives the low-order address bytes during Flash programming and verification.
Port Pin Alternate Functions
P1.0 T2 (external count input to Timer/Counter 2), clock-out
P1.1 T2EX (Timer/Counter 2 capture/reload trigger and direction control)
Port 2 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 2 output buffers can sink/source four TTL inputs. When 1s are written to Port 2 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 2 pins that are externally being pulled low will source current (I
Port 2 emits the high-order address byte during fetches from external program memory and dur­ing accesses to external data memory that use 16-bit addresses (MOVX @ DPTR). In this application, Port 2 uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX @ RI), Port 2 emits the contents of the P2 Special Function Register.
Port 2 also receives the high-order address bits and some control signals during Flash program­ming and verification.
) because of the internal pull-ups.
IL
4
AT89C55WD
1921C–MICRO–3/05

4.6 Port 3

AT89C55WD
Port 3 is an 8-bit bi-directional I/O port with internal pull-ups. The Port 3 output buffers can sink/source four TTL inputs. When 1s are written to Port 3 pins, they are pulled high by the inter­nal pull-ups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (I
Port 3 receives some control signals for Flash programming and verification.
Port 3 also serves the functions of various special features of the AT89C55WD, as shown in the following table.
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
) because of the pull-ups.
IL
(external interrupt 0)

4.7 RST

4.8 ALE/PROG

P3.3 INT1
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
P3.6 WR
P3.7 RD
(external interrupt 1)
(external data memory write strobe)
(external data memory read strobe)
Reset input. A high on this pin for two machine cycles while the oscillator is running resets the device. This pin drives High for 98 oscillator periods after the Watchdog times out. The DISRTO bit in SFR AUXR (address 8EH) can be used to disable this feature. In the default state of bit DISRTO, the RESET HIGH out feature is enabled.
Address Latch Enable is an output pulse for latching the low byte of the address during accesses to external memory. This pin is also the program pulse input (PROG
) during Flash
programming.
In normal operation, ALE is emitted at a constant rate of 1/6 the oscillator frequency and may be used for external timing or clocking purposes. Note, however, that one ALE pulse is skipped dur­ing each access to external data memory.
If desired, ALE operation can be disabled by setting bit 0 of SFR location 8EH. With the bit set, ALE is active only during a MOVX or MOVC instruction. Otherwise, the pin is weakly pulled high. Setting the ALE-disable bit has no effect if the microcontroller is in external execution mode.

4.9 PSEN

1921C–MICRO–3/05
Program Store Enable is the read strobe to external program memory.
When the AT89C55WD is executing code from external program memory, PSEN twice each machine cycle, except that two PSEN
activations are skipped during each access to
external data memory.
is activated
5

4.10 EA/VPP

External Access Enable. EA must be strapped to GND in order to enable the device to fetch code from external program memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA
should be strapped to VCC for internal program executions.
EA
will be internally latched on reset.
This pin also receives the 12V programming enable voltage (V
) during Flash programming.
PP

4.11 XTAL1

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

4.12 XTAL2

Output from the inverting oscillator amplifier.

5. Special Function Registers

A map of the on-chip memory area called the Special Function Register (SFR) space is shown in Table 5-1.
Table 5-1. AT89C55WD SFR Map and Reset Values
0F8H 0FFH
0F0H
0E8H 0EFH
0E0H
0D8H 0DFH
0D0H
0C8H
B
00000000
ACC
00000000
PSW
00000000
T2CON
00000000
T2MOD
XXXXXX00
RCAP2L
00000000
RCAP2H
00000000
TL2
00000000
TH2
00000000
0F7H
0E7H
0D7H
0CFH
0C0H 0C7H
0B8H
0B0H
0A8H
0A0H
98H
90H
88H
80H
6
IP
XX000000
P3
11111111
IE
0X000000
P2
11111111
SCON
00000000
P1
11111111
TCON
00000000
P0
11111111
SBUF
XXXXXXXX
TMOD
00000000
SP
00000111
AT89C55WD
AUXR1
XXXXXXX0
TL0
00000000
DP0L
00000000
TL1
00000000
DP0H
00000000
TH0
00000000
DP1L
00000000
TH1
00000000
DP1H
00000000
WDTRST
XXXXXXXX
AUXR
XXX00XX0
PCON
0XXX0000
1921C–MICRO–3/05
0BFH
0B7H
0AFH
0A7H
9FH
97H
8FH
87H
AT89C55WD
Note that not all of the addresses are occupied, and unoccupied addresses may not be imple­mented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke new features. In that case, the reset or inactive values of the new bits will always be 0.
Timer 2 Registers: Control and status bits are contained in registers T2CON (shown in Table 5-
2) and T2MOD (shown in Table 5-2) for Timer 2. The register pair (RCAP2H, RCAP2L) are the
Capture/Reload registers for Timer 2 in 16-bit capture mode or 16-bit auto-reload mode.
Interrupt Registers: The individual interrupt enable bits are in the IE register. Two priorities can be set for each of the six interrupt sources in the IP register.
Dual Data Pointer Registers: To facilitate accessing both internal and external data memory, two banks of 16-bit Data Pointer Registers are provided: DP0 at SFR address locations 82H­83H and DP1 at 84H-85H. Bit DPS = 0 in SFR AUXR1 selects DP0 and DPS = 1 selects DP1. The user should always initialize the DPS bit to the appropriate value before accessing the respective Data Pointer Register.
Power Off Flag: The Power Off Flag (POF) is located at bit 4 (PCON.4) in the PCON SFR. POF is set to “1” during power up. It can be set and reset under software control and is not affected by reset.
Table 5-2. T2CON—Timer/Counter 2 Control Register
T2CON Address = 0C8H Reset Value = 0000 0000B
Bit Addressable
Bit
Symbol Function
TF2
EXF2
RCLK
TCLK
EXEN2
TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.
C/T2
CP/RL2
TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2
76543210
Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK = 1 or TCLK = 1.
Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).
Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.
Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.
Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.
Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge triggered).
Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 = 0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1. When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.
CP/RL2
1921C–MICRO–3/05
7
Table 5-3. AUXR: Auxiliary Register
AUXR Address = 8EH Reset Value = XXX00XX0B
Not Bit Addressable
– – – WDIDLE DISRTO – – DISALE
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DISALE Disable/Enable ALE
DISALE Operating Mode
0 ALE is emitted at a constant rate of 1/6 the oscillator frequency
1 ALE is active only during a MOVX or MOVC instruction
DISRTO Disable/Enable Reset out
DISRTO Operating Mode
0 Reset pin is driven High after WDT times out
1 Reset pin is input only
WDIDLE Disable/Enable WDT in IDLE mode
WDIDLE Operating Mode
0 WDT continues to count in IDLE mode
1 WDT halts counting in IDLE mode
Table 5-4. AUXR1: Auxiliary Register 1
AUXR1 Address = A2H Reset Value = XXXXXXX0B
Not Bit Addressable
––– – – – –DPS
Bit 7 6 5 4 3 2 1 0
– Reserved for future expansion
DPS Data Pointer Register Select
DPS
0 Selects DPTR Registers DP0L, DP0H
1 Selects DPTR Registers DP1L, DP1H
8
AT89C55WD
1921C–MICRO–3/05

6. Memory Organization

The MCS-51 devices have a separate address space for Program and Data Memory. Up to 64 Kbytes each of external Program and Data Memory can be addressed.

6.1 Program Memory

If the EA pin is connected to GND, all program fetches are directed to external memory.
AT89C55WD

6.2 Data Memory

On the AT89C55WD, if EA 4FFFH are directed to internal memory and fetches to addresses 5000H through FFFFH are to external memory.
The AT89C55WD implements 256 bytes of on-chip RAM. The upper 128 bytes occupy a parallel address space to the Special Function Registers. That means the upper 128 bytes have the same addresses as the SFR space but are physically separate from SFR space.
When an instruction accesses an internal location above address 7FH, the address mode used in the instruction specifies whether the CPU accesses the upper 128 bytes of RAM or the SFR space. Instructions that use direct addressing access SFR space.
For example, the following direct addressing instruction accesses the SFR at location 0A0H (which is P2).
MOV 0A0H, #data
Instructions that use indirect addressing access the upper 128 bytes of RAM. For example, the following indirect addressing instruction, where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).
MOV @R0, #data
Note that stack operations are examples of indirect addressing, so the upper 128 bytes of data RAM are available as stack space.
is connected to VCC, program fetches to addresses 0000H through

7. Hardware Watchdog Timer (One-time Enabled with Reset-out)

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upsets. The WDT consists of a 13-bit counter and the WatchDog Timer Reset (WDTRST) SFR. The WDT is defaulted to disable from exiting reset. To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, it will increment every machine cycle while the oscillator is running. The WDT time-out period is dependent on the external clock frequency. There is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When WDT over­flows, it will drive an output RESET HIGH pulse at the RST pin.
1921C–MICRO–3/05
9

8. Using the WDT

To enable the WDT, a user must write 01EH and 0E1H in sequence to the WDTRST register (SFR location 0A6H). When the WDT is enabled, the user needs to service it by writing 01EH and 0E1H to WDTRST to avoid a WDT overflow. The 13-bit counter overflows when it reaches 8191 (1FFFH), and this will reset the device. When the WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user must re-initialize the WDT at least every 8191 machine cycles. To re-initialize the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write-only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET pulse duration is 98xTOSC, where TOSC=1/FOSC. To make the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within the time required to prevent a WDT reset.

9. WDT During Power-down and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in Power­down mode, the user does not need to service the WDT. There are two methods of exiting Power-down mode: by a hardware reset or via a level-activated external interrupt which is enabled prior to entering Power-down mode. When Power-down is exited with hardware reset, servicing the WDT should occur as it normally does whenever the AT89C55WD is reset. Exiting Power-down with an interrupt is significantly different. The interrupt is held low long enough for the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service for the interrupt used to exit Power-down.

10. UART

11. Timer 0 and 1

To ensure that the WDT does not overflow within a few states of exiting Power-down, it is best to reset the WDT just before entering Power-down.
Before going into the IDLE mode, the WDIDLE bit in SFR AUXR is used to determine whether the WDT continues to count if enabled. The WDT keeps counting during IDLE (WDIDLE bit = 0) as the default state. To prevent the WDT from resetting the AT89C55WD while in IDLE mode, the user should always set up a timer that will periodically exit IDLE, service the WDT, and reen­ter IDLE mode.
With WDIDLE bit enabled, the WDT will stop to count in IDLE mode and resumes the count upon exit from IDLE.
The UART in the AT89C55WD operates the same way as the UART in the AT89C51 and AT89C52. For more detailed information on the UART operation, please click on the document link below:
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
Timer 0 and Timer 1 in the AT89C55WD operate the same way as Timer 0 and Timer 1 in the AT89C51 and AT89C52. For further information on the timers’ operation, please click on the document link below:
10
http://www.atmel.com/dyn/resources/prod_documents/DOC4316.PDF
AT89C55WD
1921C–MICRO–3/05

12. Timer 2

AT89C55WD
Timer 2 is a 16-bit Timer/Counter that can operate as either a timer or an event counter. The type of operation is selected by bit C/T2 three operating modes: capture, auto-reload (up or down counting), and baud rate generator. The modes are selected by bits in T2CON, as shown in Table 5-2.
Timer 2 consists of two 8-bit registers, TH2 and TL2. In the Timer function, the TL2 register is incremented every machine cycle. Since a machine cycle consists of 12 oscillator periods, the count rate is 1/12 of the oscillator frequency.
Table 12-1. Timer 2 Operating Modes
RCLK +TCLK CP/RL2 TR2 MODE
0 0 1 16-bit Auto-Reload
0 1 1 16-bit Capture
1 X 1 Baud Rate Generator
X X 0 (Off)
In the Counter function, the register is incremented in response to a 1-to-0 transition at its corre­sponding external input pin, T2. In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and a low in the next cycle, the count is incremented. The new count value appears in the register during S3P1 of the cycle following the one in which the transition was detected. Since two machine cycles (24 oscillator periods) are required to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the oscillator frequency. To ensure that a given level is sampled at least once before it changes, the level should be held for at least one full machine cycle.
in the SFR T2CON (shown in Table 5-2). Timer 2 has

12.1 Capture Mode

In the capture mode, two options are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or counter which upon overflow sets bit TF2 in T2CON. This bit can then be used to generate an interrupt. If EXEN2 = 1, Timer 2 performs the same operation, but a 1-to-0 transi­tion at external input T2EX also causes the current value in TH2 and TL2 to be captured into RCAP2H and RCAP2L, respectively. In addition, the transition at T2EX causes bit EXF2 in T2CON to be set. The EXF2 bit, like TF2, can generate an interrupt. The capture mode is illus­trated in Figure 12-1.

12.2 Auto-reload (Up or Down Counter)

Timer 2 can be programmed to count up or down when configured in its 16-bit auto-reload mode. This feature is invoked by the DCEN (Down Counter Enable) bit located in the SFR T2MOD (see Table 12-2). Upon reset, the DCEN bit is set to 0 so that timer 2 will default to count up. When DCEN is set, Timer 2 can count up or down, depending on the value of the T2EX pin.
1921C–MICRO–3/05
11
Figure 12-1. Timer in Capture Mode
OSC
T2 PIN
T2EX PIN
÷12
TRANSITION
DETECTOR
C/T2 = 0
C/T2 = 1
EXEN2
CONTROL
TR2
CAPTURE
CONTROL
TH2 TL2
RCAP2LRCAP2H
EXF2
TF2
OVERFLOW
TIMER 2
INTERRUPT
Figure 12-2 shows Timer 2 automatically counting up when DCEN=0. In this mode, two options
are selected by bit EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to 0FFFFH and then sets the TF2 bit upon overflow. The overflow also causes the timer registers to be reloaded with the 16-bit value in RCAP2H and RCAP2L. The values in Timer in Capture Mode RCAP2H and RCAP2L are preset by software. If EXEN2 = 1, a 16-bit reload can be triggered either by an overflow or by a 1-to-0 transition at external input T2EX. This transition also sets the EXF2 bit. Both the TF2 and EXF2 bits can generate an interrupt if enabled.
Setting the DCEN bit enables Timer 2 to count up or down, as shown in Figure 12-2. In this mode, the T2EX pin controls the direction of the count. A logic 1 at T2EX makes Timer 2 count up. The timer will overflow at 0FFFFH and set the TF2 bit. This overflow also causes the 16-bit value in RCAP2H and RCAP2L to be reloaded into the timer registers, TH2 and TL2, respectively.
A logic 0 at T2EX makes Timer 2 count down. The timer underflows when TH2 and TL2 equal the values stored in RCAP2H and RCAP2L. The underflow sets the TF2 bit and causes 0FFFFH to be reloaded into the timer registers.
The EXF2 bit toggles whenever Timer 2 overflows or underflows and can be used as a 17th bit of resolution. In this operating mode, EXF2 does not flag an interrupt.
Figure 12-2. Timer 2 Auto Reload Mode (DCEN = 0)
OSC
T2 PIN
T2EX PIN
÷12
TRANSITION
DETECTOR
C/T2 = 0
C/T2 = 1
EXEN2
CONTR OL
TR2
RELOAD
CONTROL
TH2 TL2
RCAP2LRCAP2H
OVERFLOW
TF2
EXF2
TIMER 2
INTERRUPT
12
AT89C55WD
1921C–MICRO–3/05
AT89C55WD
Table 12-2. T2MOD – Timer 2 Mode Control Register
T2MOD Address = 0C9H Reset Value = XXXX XX00B
Not Bit Addressable
––––––T2OEDCEN
Bit76543210
Symbol Function
– Not implemented, reserved for future
T2OE Timer 2 Output Enable bit
DCEN When set, this bit allows Timer 2 to be configured as an up/down counter
Figure 12-3. Timer 2 Auto Reload Mode (DCEN = 1)
TOGGLE
TF2
OSC
(DOWN COUNTING RELOAD VALUE)
0FFH0FFH
12
÷
C/T2 = 0
TH2 TL2
OVERFLOW
EXF2
T2 PIN
C/T2 = 1
CONTROL
TR2
RCAP2LRCAP2H
(UP COUNTING RELOAD VALUE)
TIMER 2
INTERRUPT
COUNT DIRECTION 1=UP 0=DO
T2EX PIN
1921C–MICRO–3/05
13

13. Baud Rate Generator

Timer 2 is selected as the baud rate generator by setting TCLK and/or RCLK in T2CON (Table
5-2). Note that the baud rates for transmit and receive can be different if Timer 2 is used for the
receiver or transmitter and Timer 1 is used for the other function. Setting RCLK and/or TCLK puts Timer 2 into its baud rate generator mode, as shown in Figure 13-1.
The baud rate generator mode is similar to the auto-reload mode, in that a rollover in TH2 causes the Timer 2 registers to be reloaded with the 16-bit value in registers RCAP2H and RCAP2L, which are preset by software.
The baud rates in Modes 1 and 3 are determined by Timer 2’s overflow rate according to the fol­lowing equation.
Modes 1 and 3 Baud Rates
The Timer can be configured for either timer or counter operation. In most applications, it is con­figured for timer operation (CP/T2 used as a baud rate generator. Normally, as a timer, it increments every machine cycle (at 1/12 the oscillator frequency). As a baud rate generator, however, it increments every state time (at 1/2 the oscillator frequency). The baud rate formula is given below.
Modes 1 and 3
-------------------------------------- -
Baud Rate
where (RCAP2H, RCAP2L) is the content of RCAP2H and RCAP2L taken as a 16-bit unsigned integer.
Timer 2 as a baud rate generator is shown in Figure 13-1. This figure is valid only if RCLK or TCLK = 1 in T2CON. Note that a rollover in TH2 does not set TF2 and will not generate an inter­rupt. Note too, that if EXEN2 is set, a 1-to-0 transition in T2EX will set EXF2 but will not cause a reload from (RCAP2H, RCAP2L) to (TH2, TL2). Thus when Timer 2 is in use as a baud rate gen­erator, T2EX can be used as an extra external interrupt.
Note that when Timer 2 is running (TR2 = 1) as a timer in the baud rate generator mode, TH2 or TL2 should not be read from or written to. Under these conditions, the Timer is incremented every state time, and the results of a read or write may not be accurate. The RCAP2 registers may be read but should not be written to, because a write might overlap a reload and cause write and/or reload errors. The timer should be turned off (clear TR2) before accessing the Timer 2 or RCAP2 registers.
= 0). The timer operation is different for Timer 2 when it is
------------------------------------------------------------------------------------- -=
32 x [65536-RCAP2H,RCAP2L)]
Timer 2 Overflow Rate
----------------------------------------------------------- -=
Oscillator Frequency
16
14
AT89C55WD
1921C–MICRO–3/05
Figure 13-1. Timer 2 in Baud Rate Generator Mode
NOTE: OSC. FREQ. IS DIVIDED BY 2, NOT 12
TIMER 1 OVERFLOW
2
÷
"0"
AT89C55WD
"1"
SMOD1
OSC
T2 PIN
T2EX PIN
2
÷
TRANSITION
DETECTOR
C/T2 = 0
C/T2 = 1

14. Programmable Clock Out

A 50% duty cycle clock can be programmed to come out on P1.0, as shown in Figure 14-1. This pin, besides being a regular I/O pin, has two alternate functions. It can be programmed to input the external clock for Timer/Counter 2 or to output a 50% duty cycle clock ranging from 61 Hz to 4 MHz for a 16 MHz operating frequency.
TR2
EXEN2
CONTROL
CONTROL
TH2 TL2
RCAP2LRCAP2H
EXF2
"1"
"1"
TIMER 2
INTERRUPT
"0"
"0"
RCLK
16
÷
TCLK
÷
16
Rx
CLOCK
Tx
CLOCK
1921C–MICRO–3/05
To configure the Timer/Counter 2 as a clock generator, bit C/T2
(T2CON.1) must be cleared and
bit T2OE (T2MOD.1) must be set. Bit TR2 (T2CON.2) starts and stops the timer.
The clock-out frequency depends on the oscillator frequency and the reload value of Timer 2 capture registers (RCAP2H, RCAP2L), as shown in the following equation.
Clock-Out Frequency
Oscillator Frequency
------------------------------------------------------------------------------------ -=
4 x [65536-(RCAP2H,RCAP2L)]
In the clock-out mode, Timer 2 roll-overs will not generate an interrupt. This behavior is similar to when Timer 2 is used as a baud-rate generator. It is possible to use Timer 2 as a baud-rate gen­erator and a clock generator simultaneously. Note, however, that the baud-rate and clock-out frequencies cannot be determined independently from one another since they both use RCAP2H and RCAP2L.
15
Figure 14-1. Timer 2 in Clock-Out Mode
OSC
P1.0
(T2)
P1.1
(T2EX)

15. Interrupts

TRANSITION DETECTOR
÷2
EXEN2
TR2
C/T2 BIT
EXF2
TL2
(8-BITS)
RCAP2L RCAP2H
÷2
TIMER 2 INTERRUPT
TH2
(8-BITS)
T2OE (T2MOD.1)
The AT89C55WD has a total of six interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts (Timers 0, 1, and 2), and the serial port interrupt. These interrupts are all shown in Figure 15-1.
Each of these interrupt sources can be individually enabled or disabled by setting or clearing a bit in Special Function Register IE. IE also contains a global disable bit, EA, which disables all interrupts at once.
Note that Table 5 shows that bit position IE.6 is unimplemented. User software should not write a ‘1’ to this bit position, since it may be used in future AT89 products.
Timer 2 interrupt is generated by the logical OR of bits TF2 and EXF2 in register T2CON. Nei­ther of these flags is cleared by hardware when the service routine is vectored to. In fact, the service routine may have to determine whether it was TF2 or EXF2 that generated the interrupt, and that bit will have to be cleared in software.
16
AT89C55WD
1921C–MICRO–3/05
AT89C55WD
The Timer 0 and Timer 1 flags, TF0 and TF1, are set at S5P2 of the cycle in which the timers overflow. The values are then polled by the circuitry in the next cycle. However, the Timer 2 flag, TF2, is set at S2P2 and is polled in the same cycle in which the timer overflows.
Table 15-1. Interrupt Enable (IE) Register
(MSB) (LSB)
EA – ET2 ES ET1 EX1 ET0 EX0
Enable Bit = 1 enables the interrupt.
Enable Bit = 0 disables the interrupt.
Symbol Position Function
Disables all interrupts. If EA = 0, no interrupt is acknowledged. If EA
EA IE.7
– IE.6 Reserved.
ET2 IE.5 Timer 2 interrupt enable bit.
ES IE.4 Serial Port interrupt enable bit.
ET1 IE.3 Timer 1 interrupt enable bit.
= 1, each interrupt source is individually enabled or disabled by setting or clearing its enable bit.
EX1 IE.2 External interrupt 1 enable bit.
ET0 IE.1 Timer 0 interrupt enable bit.
EX0 IE.0 External interrupt 0 enable bit.
User software should never write 1s to reserved bits, because they may be used in future AT89 products.
Figure 15-1. Interrupt Sources
0
INT0
TF0
INT1
1
0
1
IE0
IE1
1921C–MICRO–3/05
TF1
TI
RI
TF2
EXF2
17

16. Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier that can be configured for use as an on-chip oscillator, as shown in Figure 18-1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven, as shown in Figure 18-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clock­ing circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifications must be observed.

17. Idle Mode

In idle mode, the CPU puts itself to sleep while all the on-chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the special functions regis­ters remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset.
Note that when idle mode is terminated by a hardware reset, the device normally resumes pro­gram execution from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write to a port pin when idle mode is terminated by a reset, the instruction following the one that invokes idle mode should not write to a port pin or to external memory.

18. Power-down Mode

In the Power-down mode, the oscillator is stopped, and the instruction that invokes Power-down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power-down mode is terminated. Exit from Power-down can be initiated either by a hardware reset or by an enabled external interrupt. Reset redefines the SFRs but does not change the on-chip RAM. The reset should not be activated before V operating level and must be held active long enough to allow the oscillator to restart and stabilize.
is restored to its normal
CC
18
AT89C55WD
1921C–MICRO–3/05
Figure 18-1. Oscillator Connections
C2
C1
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 18-2. External Clock Drive Configuration
AT89C55WD
XTAL2
XTAL1
GND
NC
XTAL2
EXTERNAL
OSCILLATOR
XTAL1
SIGNAL
GND
Table 18-1. Status of External Pins During Idle and Power-down Modes
Program
Mode
Idle Internal 1 1 Data Data Data Data
Idle External 1 1 Float Data Address Data
Power-down Internal 0 0 Data Data Data Data
Power-down External 0 0 Float Data Data Data
Memory ALE PSEN PORT0 PORT1 PORT2 PORT3
1921C–MICRO–3/05
19

19. Program Memory Lock Bits

The AT89C55WD has three lock bits that can be left unprogrammed (U) or can be programmed (P) to obtain the additional features listed in the following table.
Table 19-1. Lock Bit Protection Modes
Program Lock Bits
1 U U U No program lock features.
2PUU
3 P P U Same as mode 2, but verify is also disabled.
4 P P P Same as mode 3, but external execution is also disabled.
Protection TypeLB1 LB2 LB3
MOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA sampled and latched on reset, and further programming of the Flash memory is disabled.
is
When lock bit 1 is programmed, the logic level at the EA If the device is powered up without a reset, the latch initializes to a random value and holds that value until reset is activated. The latched value of EA that pin in order for the device to function properly.

20. Programming the Flash

The AT89C55WD is shipped with the on-chip Flash memory array ready to be programmed. The programming interface needs a high-voltage (12-volt) program enable signal and is compatible with conventional third-party Flash or EPROM programmers.
The AT89C55WD code memory array is programmed byte-by-byte.
Programming Algorithm: Before programming the AT89C55WD, the address, data, and con­trol signals should be set up according to the Flash programming mode table and Figures 21-1 and 21-2. To program the AT89C55WD, take the following steps:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA
5. Pulse ALE/PROG write cycle is self-timed and typically takes no more than 50 µs. Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
pin is sampled and latched during reset.
must agree with the current logic level at
/VPP to 12V.
once to program a byte in the Flash array or the lock bits. The byte-
20
AT89C55WD
1921C–MICRO–3/05
AT89C55WD
Chip Erase Sequence: Before the AT89C55WD can be reprogrammed, a Chip Erase operation
needs to be performed. To erase the contents of the AT89C55WD, follow this sequence:
1. Raise V
2. Pulse ALE/PROG
3. Wait for 150 ms.
4. Power V
5. Pulse ALE/PROG
6. Wait for 150 ms.
7. Power V
Data
Polling: The AT89C55WD features Data Polling to indicate the end of a write cycle. During
a write cycle, an attempted read of the last byte written will result in the complement of the writ­ten data on P0.7. Once the write cycle has been completed, true data is valid on all outputs, and the next cycle may begin. Data
Ready/Busy
signal. P3.0 is pulled low after ALE goes high during programming to indicate BUSY pulled high again when programming is done to indicate READY.
Program Verify: If lock bits LB1 and LB2 have not been programmed, the programmed code data can be read back via the address and data lines for verification. The status of the individual lock bits can be directly verified by reading them back.
Reading the Signature Bytes: The signature bytes are read by the same procedure as a nor­mal verification of locations 000H, 100H, and 200H, except that P3.6 and P3.7 must be pulled to a logic low. The values returned are as follows:
to 6.5V.
CC
once (duration of 200 - 500 ns).
down and up to 6.5V.
CC
once (duration of 200 - 500 ns).
down and up.
CC
Polling may begin any time after a write cycle has been initiated.
: The progress of byte programming can also be monitored by the RDY/BSY output
. P3.0 is
(000H) = 1EH indicates manufactured by Atmel (100H) = 55H (200H) = 06H indicates 89C55WD

21. Programming Interface

Every code byte in the Flash array can be programmed by using the appropriate combination of control signals. The write operation cycle is self-timed and once initiated, will automatically time itself to completion.
Most major worldwide programming vendors offer support for the Atmel AT89 microcontroller series. Please contact your local programming vendor for the appropriate software revision.
1921C–MICRO–3/05
21
Table 21-1. Flash Programming Modes
P3.4 P2.5-0 P1.7-0
IN
A14 A13-8 A7-0
A14 A13-8 A7-0
XX X
Address
Mode V
Write Code Data
Read Code Data
CC
5V H L
5VHL HH/12VL LLHHD
Write Lock Bit 16.5
V
Write Lock Bit 26.5
V
Write Lock Bit 36.5
V
Read Lock Bits
1, 2, 3
Chip Erase
5V H L H H H H L H L
6.5 V
RST PSEN
HL
HL
HL
HL
ALE/
PROG
EA/ V
(1)
P2.6 P2.7 P3.3 P3.6 P3.7
PP
P0.7-0
Data
12V L H H H H D
OUT
(2)
12V H H H H H X X X X
(2)
12V H H H L L X X X X
(2)
12V H L H H L X X X X
P0.2, P0.3,
P0.4
(3)
12V H L H L L X X X X
Read Atmel ID 5V H L H H L L L L L 1EH X XX 0000 00H
Read Device ID
Read Device ID
5V H L H H L L L L L 55H X XX 0001 00H
5V H L H H L L L L L 06H X XX 0010 00H
Notes: 1. Write Code Data requires a 200 ns PROG pulse.
2. Write Lock Bits requires a 100 µs PROG
3. Chip Erase requires a 200 ns - 500 ns PROG
4. RDY/BSY
signal is output on P3.0 during programming.
pulse.
pulse.
22
AT89C55WD
1921C–MICRO–3/05
Figure 21-1. Programming the Flash Memory
ADDR.
0000H/4FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
A0 - A7
A8 - A13
A14*
P1.0 - P1.7
P2.0 - P2.5 P3.4 P2.6
P2.7 P3.3 P3.6
P3.7
XTAL2 EA
AT89C55WD
ALE
V
CC
P0
4.5V to 5.5V
PGM DATA
PROG
V/V
AT89C55WD
IH PP
3 - 33 MHz
Figure 21-2. Verifying the Flash Memory
ADDR.
0000H/4FFFH
SEE FLASH
PROGRAMMING
MODES TABLE
3 - 33 MHz
A0 - A7
A8 - A13
A14*
P3.0
1
XTAL
GND
RST
PSEN
AT89C55WD
P1.0 - P1.7
P2.0 - P2.5 P3.4
P2.6 P2.7
P3.3 P3.6 P3.7
XTAL 2 EA
V
P0
ALE
4.5V to 5.5V
CC
RDY/ BSY
V
IH
PGM DATA (USE 10K PULL-UPS)
V
IH
1921C–MICRO–3/05
XTAL1
GND
RST
PSEN
V
IH
Note: *Programming address line A14 (P3.4) is not the same as the external memory address line A14
(P2.6).
23

22. Flash Programming and Verification Characteristics

TA = 20°C to 30°C, VCC = 4.5V to 5.5V
Symbol Parameter Min Max Units
V
PP
I
PP
I
CC
1/t
t
AVG L
t
GHAX
t
DVGL
t
GHDX
t
EHSH
t
SHGL
t
GHSL
t
GLGH
t
AVQ V
t
ELQV
t
EHQZ
t
GHBL
t
WC
CLCL
Programming Supply Voltage 11.5 12.5 V
Programming Supply Current 10 mA
VCC Supply Current 30 mA
Oscillator Frequency 3 33 MHz
Address Setup to PROG Low 48t
Address Hold After PROG 48t
Data Setup to PROG Low 48t
Data Hold After PROG 48t
P2.7 (ENABLE) High to V
PP
48t
CLCL
CLCL
CLCL
CLCL
CLCL
VPP Setup to PROG Low 10 µs
VPP Hold After PROG 10 µs
PROG Width 0.2 1 µs
Address to Data Valid 48t
ENABLE Low to Data Valid 48t
Data Float After ENABLE 048t
CLCL
CLCL
CLCL
PROG High to BUSY Low 1.0 µs
Byte Write Cycle Time 80 µs
24
AT89C55WD
1921C–MICRO–3/05

23. Flash Programming and Verification Waveforms

P1.0 - P1.7 P2.0 - P2.5
P3.4
PORT 0
ALE/PROG
EA/V
P2.7
(ENABLE)
P3.0
(RDY/BSY)
t
AVGL
t
SHGL
PP
PROGRAMMING
ADDRESS
DATA I N
t
t
DVGL
t
GLGH
V
PP
t
EHSH
t
GHBL
GHDX
t
t
ELQV
GHAX
t
GHSL
LOGIC 1 LOGIC 0
BUSY
t
WC

24. Lock Bit Programming

VERIFICATION
ADDRESS
t
AVQV
DATA O UT
READY
AT89C55WD
t
EHQZ
Test Conditions
Setup
Lockbit_1, 2 or 3
Data Setup
ALE/PROG
V
= 6.5V
CC

25. Parallel Chip Erase Mode

Test Conditions
Setup
ALE/PROG
P3<0>
200 ns
Erase
DC
Erase
100 µs
Test Conditions Setup
200 ns
Erase
V
= 4.5V to 5.5V
CC
Wait 10 ms to reload new lock bit status
DC
Erase
1921C–MICRO–3/05
V
CC
= 6.5V
= 4.5V to 5.5V
V
CC
Wait 10 ms before
10 ms
reprogramming
25

26. Absolute Maximum Ratings*

Operating Temperature.................................. -55°C to +125°C
Storage Temperature ..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground.....................................-1.0V to +7.0V
Maximum Operating Voltage ............................................ 6.6V
DC Output Current...................................................... 15.0 mA
*NOTICE: Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam­age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

27. DC Characteristics

The values shown in this table are valid for TA = -40°C to 85°C and VCC = 4.0V to 5.5V, unless otherwise noted.
Symbol Parameter Condition Min Max Units
V
IL
V
IL1
V
IH
V
IH1
V
OL
V
OL1
V
OH
Input Low Voltage (Except EA)-0.50.2 V
Input Low Voltage (EA)-0.50.2 V
-0.1 V
CC
-0.3 V
CC
Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V
Input High Voltage (XTAL1, RST) 0.7 V
Output Low Voltage
Output Low Voltage
Output High Voltage (Ports 1,2,3, ALE, PSEN
(1)
(Ports 1,2,3) IOL = 1.6 mA 0.45 V
(1)
(Port 0, ALE, PSEN)IOL = 3.2 mA 0.45 V
= -60 µA, VCC = 5V ± 10% 2.4 V
I
OH
I
= -25 µA 0.75 V
)
OH
IOH = -10 µA 0.9 V
CC
CC
CC
VCC+0.5 V
IOH = -800 µA, VCC = 5V ± 10% 2.4 V
V
OH1
I
IL
I
TL
I
LI
Output High Voltage (Port 0 in External Bus Mode)
Logical 0 Input Current (Ports 1,2,3) VIN = 0.45V -50 µA
Logical 1 to 0 Transition Current (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA
Input Leakage Current (Port 0, EA)0.45 < V
I
= -300 µA 0.75 V
OH
IOH = -80 µA 0.9 V
< V
IN
CC
CC
CC
±10 µA
RRST Reset Pulldown Resistor 10 30 kΩ
C
IO
Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF
Active Mode, 12 MHz 25 mA
Power Supply Current
I
CC
Power-down Mode
(1)
Idle Mode, 12 MHz 6.5 mA
VCC = 5.5V 100 µA
Notes: 1. Under steady state (non-transient) conditions, IOL must be externally limited as follows:
Maximum I Maximum I
per port pin: 10 mA
OL
per 8-bit port:
OL
Port 0: 26 mA Ports 1, 2, 3: 15 mA Maximum total IOL for all output pins: 71 mA
exceeds the test condition, V
If I
OL
may exceed the related specification. Pins are not guaranteed to sink current greater
OL
than the listed test conditions.
2. Minimum V
for Power-down is 2V.
CC
V
V
V
V
26
AT89C55WD
1921C–MICRO–3/05
AT89C55WD

28. AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.

28.1 External Program and Data Memory Characteristics

12 MHz Oscillator Variable Oscillator
Symbol Parameter
UnitsMin Max Min Max
1/t
t
LHLL
t
AVL L
t
LLAX
t
LLIV
t
LLPL
t
PLPH
t
PLIV
t
PXIX
t
PXIZ
t
PXAV
t
AVI V
t
PLAZ
t
RLRH
t
WLWH
t
RLDV
t
RHDX
t
RHDZ
t
LLDV
t
AVDV
t
LLWL
t
AVW L
t
QVWX
t
QVWH
t
WHQX
t
RLAZ
t
WHLH
CLCL
Oscillator Frequency 0 33 MHz
ALE Pulse Width 127 2t
Address Valid to ALE Low 43 t
Address Hold After ALE Low 48 t
ALE Low to Valid Instruction In 233 4t
ALE Low to PSEN Low 43 t
PSEN Pulse Width 205 3t
PSEN Low to Valid Instruction In 145 3t
-40 ns
CLCL
-25 ns
CLCL
-25 ns
CLCL
-65 ns
CLCL
-25 ns
CLCL
-45 ns
CLCL
-60 ns
CLCL
Input Instruction Hold After PSEN 00ns
Input Instruction Float After PSEN 59 t
PSEN to Address Valid 75 t
-8 ns
CLCL
Address to Valid Instruction In 312 5t
-25 ns
CLCL
-80 ns
CLCL
PSEN Low to Address Float 10 10 ns
RD Pulse Width 400 6t
WR Pulse Width 400 6t
RD Low to Valid Data In 252 5t
-100 ns
CLCL
-100 ns
CLCL
-90 ns
CLCL
Data Hold After RD 00ns
Data Float After RD 97 2t
ALE Low to Valid Data In 517 8t
Address to Valid Data In 585 9t
ALE Low to RD or WR Low 200 300 3t
Address to RD or WR Low 203 4t
Data Valid to WR Transition 23 t
Data Valid to WR High 433 7t
Data Hold After WR 33 t
-50 3t
CLCL
-75 ns
CLCL
-30 ns
CLCL
-130 ns
CLCL
-25 ns
CLCL
-28 ns
CLCL
-150 ns
CLCL
-165 ns
CLCL
+50 ns
CLCL
RD Low to Address Float 0 0 ns
RD or WR High to ALE High 43 123 t
-25 t
CLCL
+25 ns
CLCL
1921C–MICRO–3/05
27

29. External Program Memory Read Cycle

t
LHLL
ALE
t
AVLL
t
LLPL
PSEN
t
PLAZ
A8 - A15
PORT 0
PORT 2
t
LLAX
A0 - A7 A0 - A7
t
AVIV

30. External Data Memory Read Cycle

t
LHLL
ALE
t
LLIV
t
PLIV
t
PXIZ
t
PXIX
INSTR IN
t
PLPH
t
PXAV
t
A8 - A15
WHLH
PSEN
RD
PORT 0
PORT 2
t
LLDV
t
LLWL
t
LLAX
t
AVLL
A0 - A7 FROM RI OR DPL
t
AVWL
P2.0 - P2.7 OR A8 - A15 FROM DPH
t
AVDV
t
RLAZ
t
RLRH
t
RLDV
DATA IN INSTR IN
t
RHDZ
t
RHDX
A0 - A7 FROM PCL
A8 - A15 FROM PCH
28
AT89C55WD
1921C–MICRO–3/05

31. External Data Memory Write Cycle

t
LHLL
ALE
PSEN
t
LLWL
t
WLWH
t
WHLH
AT89C55WD
WR
PORT 0
PORT 2
t
AVLL
A0 - A7 FROM RI OR DPL
P2.0 - P2.7 OR A8 - A15 FROM DPH
t
AVWL
t
LLAX
t
QVWX

32. External Clock Drive Waveforms

t
0.7 V
CC
CHCX
CC
0.45V
V - 0.5V
CC
0.2 V - 0.1V
t
t
QVWH
DATA OUT INSTR IN
t
CLCH
t
CLCX
WHQX
A0 - A7 FROM PCL
A8 - A15 FROM PCH
t
CHCX
t
CLCL
t
CHCL

33. External Clock Drive

Symbol Parameter Min Max Units
1/t
CLCL
t
CLCL
t
CHCX
t
CLCX
t
CLCH
t
CHCL
1921C–MICRO–3/05
Oscillator Frequency 0 33 MHz
Clock Period 30 ns
High Time 12 ns
Low Time 12 ns
Rise Time 5 ns
Fall Time 5 ns
29

34. Serial Port Timing: Shift Register Mode Test Conditions

The values in this table are valid for V
= 4.0V to 5.5V and Load Capacitance = 80 pF.
CC
12 MHz Osc Variable Oscillator
Symbol Parameter
t
XLXL
t
QVXH
t
XHQX
t
XHDX
t
XHDV
Serial Port Clock Cycle Time 1.0 12t
Output Data Setup to Clock Rising Edge 700 10t
Output Data Hold After Clock Rising Edge 50 2t
Input Data Hold After Clock Rising Edge 0 0 ns
Clock Rising Edge to Input Data Valid 700 10t

35. Shift Register Mode Timing Waveforms

INSTRUCTION
ALE
CLOCK
WRITE TO SBUF
OUTPUT DATA
CLEAR RI
INPUT DATA
0
t
QVXH
1
t
XHDV
2
t
XLXL
t
0
VALID VALIDVALID VALIDVALID VALIDVALID VALID
1
XHQX
3
2
t
XHDX
UnitsMin Max Min Max
CLCL
-133 ns
CLCL
-80 ns
CLCL
-133 ns
CLCL
4
5
3
4
6
5
7
8
6
µs
7
SET TI
SET RI
36. AC Testing Input/Output Waveforms
V - 0.5V
CC
0.45V
Note: 1. AC Inputs during testing are driven at VCC - 0.5V for a logic 1 and 0.45V for a logic 0. Timing
measurements are made at V
37. Float Waveforms
(1)
+ 0.1V
V
LOAD
V
LOAD
V
LOAD
- 0.1V
Timing Reference
Note: 1. For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage
occurs. A port pin begins to float when a 100 mV change from the loaded V occurs.
(1)
0.2 V + 0.9V
CC
TEST POINTS
0.2 V - 0.1V
CC
min. for a logic 1 and VIL max. for a logic 0.
IH
Points
- 0.1V
V
OL
+ 0.1V
V
OL
level
OH/VOL
30
AT89C55WD
1921C–MICRO–3/05

38. Ordering Information

38.1 Standard Package

Speed
(MHz)
24 4.0V to 5.5V
33 4.5V to 5.5V

38.2 Green Package Option (Pb/Halide-free)

Speed
(MHz)
24 4.0V to 5.5V
Power
Supply Ordering Code Package Operation Range
AT89C55WD-24AC AT89C55WD-24JC AT89C55WD-24PC
AT89C55WD-24AI AT89C55WD-24JI AT89C55WD-24PI
AT89C55WD-33AC AT89C55WD-33JC AT89C55WD-33PC
Power
Supply Ordering Code Package Operation Range
AT89C55WD-24AU AT89C55WD-24JU AT89C55WD-24PU
44A 44J 40P6
44A 44J 40P6
44A 44J 40P6
44A 44J 40P6
AT89C55WD
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Commercial
(0°C to 70°C)
Industrial
(-40°C to 85°C)
Package Type
44A 44-lead, Thin Plastic Gull Wing Quad Flatpack (TQFP)
44J 44-lead, Plastic J-leaded Chip Carrier (PLCC)
40P6 40-pin, 0.600" Wide, Plastic Dual Inline Package (PDIP)
1921C–MICRO–3/05
31

39. Package Information

39.1 44A – TQFP
PIN 1
PIN 1 IDENTIFIER
B
e
E1 E
D1
D
C
0˚~7˚
A1
L
Notes: 1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch.
3. Lead coplanarity is 0.10 mm maximum.
A2 A
SYMBOL
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
E 11.75 12.00 12.25
E1 9.90 10.00 10.10 Note 2
B 0.30 – 0.45
C 0.09 – 0.20
L 0.45 – 0.75
e 0.80 TYP
NOM
MAX
NOTE
32
2325 Orchard Parkway
R
San Jose, CA 95131
AT89C55WD
TITLE
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
10/5/2001
DRAWING NO.
44A
1921C–MICRO–3/05
REV.
B
39.2 44J – PLCC
AT89C55WD
1.14(0.045) X 45˚
B
e
0.51(0.020)MAX
45˚ MAX (3X)
Notes: 1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line.
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
PIN NO. 1
IDENTIFIER
D1
D
1.14(0.045) X 45˚
E1 E
0.318(0.0125)
0.191(0.0075)
NOM
D2/E2
MAX
B1
A2
A1
A
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A 4.191 – 4.572
A1 2.286 – 3.048
A2 0.508 – –
D 17.399 – 17.653
D1 16.510 – 16.662 Note 2
E 17.399 – 17.653
E1 16.510 – 16.662 Note 2
D2/E2 14.986 – 16.002
B 0.660 – 0.813
B1 0.330 – 0.533
e 1.270 TYP
MIN
NOTE
2325 Orchard Parkway
R
San Jose, CA 95131
1921C–MICRO–3/05
TITLE
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
DRAWING NO.
44J
10/04/01
REV.
B
33
39.3 40P6 – PDIP
PIN
1
E1
A1
B
REF
E
B1
C
L
SEATING PLANE
A
e
D
0º ~ 15º
eB
Notes: 1. This package conforms to JEDEC reference MS-011, Variation AC.
2. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
TITLE
2325 Orchard Parkway
R
San Jose, CA 95131
40P6, 40-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP)
COMMON DIMENSIONS
(Unit of Measure = mm)
SYMBOL
A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
L 3.048 – 3.556
C 0.203 – 0.381
eB 15.494 – 17.526
e 2.540 TYP
MIN
NOM
MAX
DRAWING NO.
40P6
NOTE
09/28/01
REV.
B
34
AT89C55WD
1921C–MICRO–3/05
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2325 Orchard Parkway San Jose, CA 95131, USA Tel: 1(408) 441-0311 Fax: 1(408) 487-2600
Regional Headquarters
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