Atmel AT89C55 Datasheet

Features

• Compatible with MCS-51

• 20K Bytes of In-System Reprogrammable Flash Memory

– Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 33 MHz

• Three-level Program Memory Lock

• 256 x 8-bit Internal RAM

• 32 Programmable I/O Lines

• Three 16-bit Timer/Counters

• Eight Interrupt Sources

• Low-power Idle and Power-down Modes

™

Products

8-bit

Description

The AT89C55 is a low-power, high-performance CMOS 8-bit microcomputer with 20K
bytes of Flash programmable and erasable read only memory. The device is manu­factured using Atmel’s high-density nonvolatile memory technology and is compatible
with the industry-standard 80C51 instruction set and pinout. The on-chip Flash allows
the program memory to be reprogrammed in-system or by a conventional nonvolatile
memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic
chip, the Atmel AT89C55 is a powerful microcomputer which provides a highly-flexible
and cost-effective solution to many embedded control applications.

Pin Configurations

PQFP/TQFP

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

P0.0 (AD0)

P0.1 (AD1)

4443424140393837363534

1

P1.5

2

P1.6

3

P1.7

4

RST

(T0) P3.4
(T1) P3.5

5
6

NC

7
8
9
10
11

1213141516171819202122

(WR)P3.6

(RD) P3.7

XTAL2

XTAL1

GND

GND

(A8) P2.0

(A9) P2.1

(A10) P2.2

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

P0.2 (AD2)

P0.3 (AD3)

33
32
31
30
29
28
27
26
25
24
23

(A11) P2.3

(A12) P2.4

PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

P1.5
P1.6
P1.7
RST

(RXD) P3.0

(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(T0) P3.4
(T1) P3.5

(T2 EX) P1.1

NC

(RXD) P3.0
(TXD) P3.1
(INT0) P3.2
(INT1) P3.3

(WR) P3.6

(RD) P3.7

7
8
9
10
11
12
13
14
15
16
17

PDIP

1

(T2) P1.0

P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST

(T0) P3.4
(T1) P3.5

XTAL2
XTAL1

GND

40

2

39

3

38

4

37

5

36

6

35

7

34

8

33

9

32

10

31

11

30

12

29

13

28

14

27

15

26

16

25

17

24

18

23

19

22

20

21

PLCC

P1.4

P1.3

P1.2

P1.1 (T2 EX)

P1.0 (T2)NCVCC

XTAL1

GND

1

NC

P0.0 (AD0)

4443424140

(A8) P2.0

(A9) P2.1

65432

1819202122232425262728

XTAL2

(WR)P3.6

(RD) P3.7

VCC
P0.0 (AD0)
P0.1 (AD1)
P0.2 (AD2)
P0.3 (AD3)
P0.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)

P0.1 (AD1)

P0.2 (AD2)

P0.3 (AD3)

39
38
37
36
35
34
33
32
31
30
29

(A10) P2.2

(A11) P2.3

(A12) P2.4

PO.4 (AD4)
P0.5 (AD5)
P0.6 (AD6)
P0.7 (AD7)
EA/VPP
NC
ALE/PROG
PSEN
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)

Microcontroller
with 20K Bytes
Flash

AT89C55

Rev. 0580E–02/00

1

The AT89C55 provides the following standard features:
20K bytes of Flash, 256 bytes of RAM, 32 I/O lines, three
16-bit timer/counters, a six-vector two-level interrupt archi­tecture, a full duplex serial port, on-chip oscillator, and
clock circuitry. In addition, the AT89C55 is designed with
static logic for operation down to zero frequency and sup­ports two software selectable power-saving modes. The

Block Diagram

Idle Mode stops the CPU while allowing the RAM,
timer/counters, serial port, and interrupt system to continue
functioning. Thepower-down mode saves the RAM con­tents but freezes the oscillator, disabling all other chip
functions until the next hardware reset. The low-voltage
option saves power and operates with a 2.7-volt power
supply.

V

GND

PORT 2 DRIVERS

PORT 2

LATCH

POINTER

P2.0 - P2.7

FLASH

STACK

PROGRAM

ADDRESS

REGISTER

BUFFER

PC

INCREMENTER

PROGRAM
COUNTER

P0.0 - P0.7

CC

RAM ADDR.

REGISTER

B

REGISTER

ACC

TMP2 TMP1

PORT 0 DRIVERS

RAM

ALU

PSW

PORT 0

LATCH

INTERRUPT, SERIAL PORT,

AND TIMER BLOCKS

PSEN

ALE/PROG

EA / V

PP

RST

2

TIMING

AND

CONTROL

OSC

INSTRUCTION

REGISTER

AT89C55

PORT 1

LATCH

PORT 1 DRIVERS

P1.0 - P1.7

PORT 3

LATCH

PORT 3 DRIVERS

P3.0 - P3.7

DPTR

AT89C55

Pin Description

VCC

Supply voltage.

GND

Ground.

Port 0

Port 0 is an 8-bit open drain bi-directional I/O port. As an
output port, each pin can sink eight TTL inputs. When 1s
are written to port 0 pins, the pins can be used as high­impedance inputs.

Port 0 can also be configured to be the multiplexed low­order address/data bus during accesses to external pro­gram and data memory. In this mode, P0 has internal
pullups.

Port 0 also receives the code bytes during Flash program­ming and outputs the code bytes during program
verification. External pullups are required during program
verification.

Port 1

Port 1 is an 8-bit bi-directional I/O port with internal pullups.
The Port 1 output buffers can sink/source four TTL inputs.
When 1s are written to Port 1 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 1 pins that are externally being pulled low will source
current (I

In addition, P1.0 and P1.1 can be configured to be the
timer/counter 2 external count input (P1.0/T2) and the
timer/counter 2 trigger input (P1.1/T2EX), respectively, as
shown in the following table.

Port Pin Alternate Functions

P1.0 T2 (external count input to Timer/Counter 2),

P1.1 T2EX (Timer/Counter 2 capture/reload trigger

) because of the internal pullups.

IL

clock-out

and direction control)

Port 2 emits the high-order address byte during fetches
from external program memory and during accesses to
external data memory that use 16-bit addresses (MOVX @
DPTR). In this application, Port 2 uses strong internal pul­lups when emitting 1s. During accesses to external data
memory that use 8-bit addresses (MOVX @ RI), Port 2
emits the contents of the P2 Special Function Register.

Port 2 also receives the high-order address bits and some
control signals during Flash programming and verification.

Port 3

Port 3 is an 8-bit bi-directional I/O port with internal pullups.
The Port 3 output buffers can sink/source four TTL inputs.
When 1s are written to Port 3 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 3 pins that are externally being pulled low will source
current (I

) because of the pullups.

IL

Port 3 also serves the functions of various special features
of the AT89C55, as shown in the following table.

Port Pin Alternate Functions

P3.0 RXD (serial input port)

P3.1 TXD (serial output port)

P3.2 INT0

P3.3 INT1

P3.4 T0 (timer 0 external input)

P3.5 T1 (timer 1 external input)

P3.6 WR

P3.7 RD

(external interrupt 0)

(external interrupt 1)

(external data memory write strobe)

(external data memory read strobe)

Port 3 also receives the highest-order address bit and
some control signals for Flash programming and
verification.

RST

Reset inp1ut. A high on this pin for two machine cycles
while the oscillator is running resets the device.

Port 1 also receives the low-order address bytes during
Flash programming and verification.

Port 2

Port 2 is an 8-bit bi-directional I/O port with internal pullups.
The Port 2 output buffers can sink/source four TTL inputs.
When 1s are written to Port 2 pins, they are pulled high by
the internal pullups and can be used as inputs. As inputs,
Port 2 pins that are externally being pulled low will source
current (I

) because of the internal pullups.

IL

ALE/PROG

Address Latch Enable is an output pulse for latching the
low byte of the address during accesses to external mem­ory. This pin is also the program pulse input (PROG

) during

Flash programming.

In normal operation, ALE is emitted at a constant rate of 1/6
the oscillator frequency and may be used for external tim­ing or clocking purposes. Note, however, that one ALE
pulse is skipped during each access to external data
memory.

3

If desired, ALE operation can be disabled by setting bit 0 of
SFR location 8EH. With the bit set, ALE is active only dur­ing a MOVX or MOVC instruction. Otherwise, the pin is
weakly pulled high. Setting the ALE-disable bit has no
effect if the microcontroller is in external execution mode.

PSEN

Program Store Enable is the read strobe to external pro­gram memory.

When the AT89C55 is executing code from external pro­gram memory, PSEN
cycle, except that two PSEN

is activated twice each machine

activations are skipped during

each access to external data memory.

/VPP

EA

program memory locations starting at 0000H up to FFFFH.
Note, however, that if lock bit 1 is programmed, EA
internally latched on reset.

should be strapped to VCC for internal program

EA
executions.

This pin also receives the 12-volt programming enable volt­age (V

) during 12-volt Flash programming.

PP

XTAL1

Input to the inverting oscillator amplifier and input to the
internal clock operating circuit.

XTAL2

Output from the inverting oscillator amplifier.

External Access Enable. EA must be strapped to GND in
order to enable the device to fetch code from external

Table 1. AT89C55 SFR Map and Reset Values

0F8H 0FFH

will be

0F0H

0E8H 0EFH

0E0H

0D8H 0DFH

0D0H

0C8H

0C0H 0C7H

0B8H

0B0H

0A8H

0A0H

98H

90H

88H

80H

B

00000000

ACC

00000000

PSW

00000000

T2CON

00000000

IP

XX000000

P3

11111111

IE

0X000000

P2

11111111

SCON

00000000

P1

11111111

TCON

00000000

P0

11111111

T2MOD

XXXXXX00

SBUF

XXXXXXXX

TMOD

00000000

SP

00000111

RCAP2L

00000000

TL0

00000000

DPL

00000000

RCAP2H

00000000

TL1

00000000

DPH

00000000

TL2

00000000

TH0

00000000

TH2

00000000

TH1

00000000

PCON

0XXX0000

0F7H

0E7H

0D7H

0CFH

0BFH

0B7H

0AFH

0A7H

9FH

97H

8FH

87H

4

AT89C55

AT89C55

Special Function Registers

A map of the on-chip memory area called the Special Func­tion Register (SFR) space is shown in Table 1.

Note that not all of the addresses are occupied, and unoc­cupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indetermi­nate effect.

User software should not write 1s to these unlisted loca­tions, since they may be used in future products to invoke
new features. In that case, the reset or inactive values of
the new bits will always be 0.

Timer 2 Registers Control and status bits are contained in
registers T2CON (shown in Table 2) and T2MOD (shown in
Table 4) for Timer 2. The register pair (RCAP2H, RCAP2L)
are the Capture/Reload registers for Timer 2 in 16-bit cap­ture mode or 16-bit auto-reload mode.

Interrupt Registers The individual interrupt enable bits are
in the IE register. Two priorities can be set for each of the
six interrupt sources in the IP register.

Data Memory

The AT89C55 implements 256 bytes of on-chip RAM. The
upper 128 bytes occupy a parallel address space to the
Special Function Registers. That means the upper 128
bytes have the same addresses as the SFR space but are
physically separate from SFR space.

When an instruction accesses an internal location above
address 7FH, the address mode used in the instruction
specifies whether the CPU accesses the upper 128 bytes
of RAM or the SFR space. Instructions that use direct
addressing access SFR space.

For example, the following direct addressing instruction
accesses the SFR at location 0A0H (which is P2).

MOV 0A0H, #data

Instructions that use indirect addressing access the upper
128 bytes of RAM. For example, the following indirect
addressing instruction, where R0 contains 0A0H, accesses
the data byte at address 0A0H, rather than P2 (whose
address is 0A0H).

MOV @R0, #data

Note that stack operations are examples of indirect
addressing, so the upper 128 bytes of data RAM are avail­able as stack space.

Table 2. T2CON—Timer/Counter 2 Control Register

T2CON Address = 0C8H Reset Value = 0000 0000B

Bit Addressable

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2

Bit 7 6543210

Symbol Function

TF2 Timer 2 overflow flag set by a Timer 2 overflow and must be cleared by software. TF2 will not be set when either RCLK

EXF2 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1.

RCLK Receive clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its receive clock in serial port

TCLK Transmit clock enable. When set, causes the serial port to use Timer 2 overflow pulses for its transmit clock in serial

EXEN2 Timer 2 external enable. When set, allows a capture or reload to occur as a result of a negative transition on T2EX if

TR2 Start/Stop control for Timer 2. TR2 = 1 starts the timer.

C/T2

= 1 or TCLK = 1.

When Timer 2 interrupt is enabled, EXF2 = 1 will cause the CPU to vector to the Timer 2 interrupt routine. EXF2 must
be cleared by software. EXF2 does not cause an interrupt in up/down counter mode (DCEN = 1).

Modes 1 and 3. RCLK = 0 causes Timer 1 overflow to be used for the receive clock.

port Modes 1 and 3. TCLK = 0 causes Timer 1 overflows to be used for the transmit clock.

Timer 2 is not being used to clock the serial port. EXEN2 = 0 causes Timer 2 to ignore events at T2EX.

Timer or counter select for Timer 2. C/T2 = 0 for timer function. C/T2 = 1 for external event counter (falling edge
triggered).

CP/RL2

CP/RL2

Capture/Reload select. CP/RL2 = 1 causes captures to occur on negative transitions at T2EX if EXEN2 = 1. CP/RL2 =
0 causes automatic reloads to occur when Timer 2 overflows or negative transitions occur at T2EX when EXEN2 = 1.
When either RCLK or TCLK = 1, this bit is ignored and the timer is forced to auto-reload on Timer 2 overflow.

5

Timer 0 and 1

Timer 0 and Timer 1 in the AT89C55 operate the same way
as Timer) and Timer 1 in the AT89C51 and AT89C52. For
further information, see the Microcontroller Data Book, sec­tion titled, “Timer/Counters.”

Timer 2

Timer 2 is a 16-bit Timer/Counter that can operate as either
a timer or an event counter. The type of operation is
selected by bit C/T2
Timer 2 has three operating modes: capture, auto-reload
(up or down counting), and baud rate generator. The
modes are selected by bits in T2CON, as shown in Table 3.

Table 3. Timer 2 Operating Modes

RCLK + TCLK CP/RL2 TR2 MODE

0 0 1 16-bit Auto-reload

0 1 1 16-bit Capture

1 X 1 Baud Rate Generator

XX0(Off)

Timer 2 consists of two 8-bit registers, TH2 and TL2. In the
Timer function, the TL2 register is incremented every
machine cycle. Since a machine cycle consists of 12
oscillator periods, the count rate is 1/12 of the oscillator
frequency.

in the SFR T2CON (shown in Table 2).

In the Counter function, the register is incremented in
response to a 1-to-0 transition at its corresponding external
input pin, T2. In this function, the external input is sampled
during S5P2 of every machine cycle. When the samples
show a high in one cycle and a low in the next cycle, the
count is incremented. The new count value appears in the
register during S3P1 of the cycle following the one in which
the transition was detected. Since two machine cycles (24
oscillator periods) are required to recognize a 1-to-0 transi­tion, the maximum count rate is 1/24 of the oscillator
frequency. To ensure that a given level is sampled at least
once before it changes, the level should be held for at least
one full machine cycle.

Capture Mode

In the capture mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer
or counter which upon overflow sets bit TF2 in T2CON.
This bit can then be used to generate an interrupt. If
EXEN2 = 1, Timer 2 performs the same operation, but a 1­to-0 transition at external input T2EX also causes the cur­rent value in TH2 and TL2 to be captured into RCAP2H and
RCAP2L, respectively. In addition, the transition at T2EX
causes bit EXF2 in T2CON to be set. The EXF2 bit, like
TF2, can generate an interrupt. The capture mode is illus­trated in Figure 1.

Figure 1. Timer 2 in Capture Mode

6

AT89C55

Auto-reload (Up or Down Counter)

AT89C55

Timer 2 can be programmed to count up or down when
configured in its 16-bit auto-reload mode. This feature is
invoked by the DCEN (Down Counter Enable) bit located in
the SFR T2MOD (see Table 4). Upon reset, the DCEN bit
is set to 0 so that timer 2 will default to count up. When
DCEN is set, Timer 2 can count up or down, depending on
the value of the T2EX pin.

Figure 2 shows Timer 2 automatically counting up when
DCEN = 0. In this mode, two options are selected by bit
EXEN2 in T2CON. If EXEN2 = 0, Timer 2 counts up to
0FFFFH and then sets the TF2 bit upon overflow. The
overflow also causes the timer registers to be reloaded with
the 16-bit value in RCAP2H and RCAP2L. The values in
RCAP2H and RCAP2L are preset by software. If EXEN2 =
1, a 16-bit reload can be triggered either by an overflow or
by a 1-to-0 transition at external input T2EX. This transition

Figure 2. Timer 2 Auto Reload Mode (DCEN = 0)

also sets the EXF2 bit. Both the TF2 and EXF2 bits can
generate an interrupt if enabled.

Setting the DCEN bit enables Timer 2 to count up or down,
as shown in Figure 3. In this mode, the T2EX pin controls
the direction of the count. A logic 1 at T2EX makes Timer 2
count up. The timer will overflow at 0FFFFH and set the
TF2 bit. This overflow also causes the 16-bit value in
RCAP2H and RCAP2L to be reloaded into the timer regis­ters, TH2 and TL2, respectively.

A logic 0 at T2EX makes Timer 2 count down. The timer
underflows when TH2 and TL2 equal the values stored in
RCAP2H and RCAP2L. The underflow sets the TF2 bit and
causes 0FFFFH to be reloaded into the timer registers.

The EXF2 bit toggles whenever Timer 2 overflows or
underflows and can be used as a 17th bit of resolution. In
this operating mode, EXF2 does not flag an interrupt.

Table 4. T2MOD—Timer 2 Mode Control Register

T2MOD Address = 0C9H Reset Value = XXXX XX00B

Not Bit Addressable

– – ––––T20E DCEN

Bit 7 6 543210

Symbol Function

– Not implemented, reserved for future use.

T20E Timer 2 Output Enable bit.

DCEN When set, this bit allows Timer 2 to be configured as an up/down counter.

7

Figure 3. Timer 2 Auto Reload Mode (DCEN = 1)

OSC

12

÷

T2 PIN

C/T2 = 0

TR2

C/T2 = 1

Figure 4. Timer 2 in Baud Rate Generator Mode

(DOWN COUNTING RELOAD VALUE)

0FFH0FFH

OVERFLOW

TH2 TL2

CONTROL

RCAP2LRCAP2H

(UP COUNTING RELOAD VALUE)

TOGGLE

EXF2

TF2

TIMER 2

INTERRUPT

COUNT
DIRECTION
1=UP
0=DOWN

T2EX PIN

8

AT89C55