ATMEL AT89C51CC03 User Manual

BDTIC www.bdtic.com/ATMEL

Features

•80C51 Core Architecture

•256 Bytes of On-chip RAM

•2048 Bytes of On-chip ERAM

•64K Bytes of On-chip Flash Memory

–Data Retention: 10 Years at 85°C

–Read/Write Cycle: 100K

•2K Bytes of On-chip Flash for Bootloader

•2K Bytes of On-chip EEPROM Read/Write Cycle: 100K

•Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

•14-sources 4-level Interrupts

•Three 16-bit Timers/Counters

•Full Duplex UART Compatible 80C51

•High-speed Architecture

–In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

•Five Ports: 32 + 4 Digital I/O Lines

•Five-channel 16-bit PCA with

–PWM (8-bit)

–High-speed Output

–Timer and Edge Capture

•Double Data Pointer

•21-bit WatchDog Timer (7 Programmable Bits)

•A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

•SPI Interface, (PLCC52 and VPFP64 packages only)

•Full CAN Controller

–Fully Compliant with CAN Rev 2.0A and 2.0B

–Optimized Structure for Communication Management (Via SFR)

–15 Independent Message Objects

–Each Message Object Programmable on Transmission or Reception

–Individual Tag and Mask Filters up to 29-bit Identifier/Channel

–8-byte Cyclic Data Register (FIFO)/Message Object

–16-bit Status and Control Register/Message Object

–16-bit Time-Stamping Register/Message Object

–CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object

–Access to Message Object Control and Data Registers Via SFR

–Programmable Reception Buffer Length Up To 15 Message Objects

–Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature)

–Priority Management for Transmission

–Message Object Overrun Interrupt

–Supports

–Time Triggered Communication

–Autobaud and Listening Mode

–Programmable Automatic Reply Mode

–1-Mbit/s Maximum Transfer Rate at 8 MHz (1) Crystal Frequency in X2 Mode

–Readable Error Counters

–Programmable Link to On-chip Timer for Time Stamping and Network Synchronization

–Independent Baud Rate Prescaler

–Data, Remote, Error and Overload Frame Handling

1.At BRP = 1 sampling point will be fixed.

Enhanced 8-bit MCU with CAN Controller and Flash Memory

AT89C51CC03

Rev. 4182N–CAN–03/08

•On-chip Emulation Logic (Enhanced Hook System)

•Power Saving Modes

–Idle Mode

–Power-down Mode

•Power Supply: 3 volts to 5.5 volts

•Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C)

•Packages: VQFP44, PLCC44, VQFP64, PLCC52

Description

The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM.

Primary attention is paid to the reduction of the electro-magnetic emission of AT89C51CC03.

Block Diagram

RxD

TxD

Vcc

Vss

ECI

PCA

T2EX

T2

RxDC

TxDC

XTAL1

UART

RAM

Flash

Boot

EE

ERAM

PCA

Timer2

CAN

XTAL2

256x8

64k x 8

loader

PROM

2048

2kx8

2kx8

CONTROLLER

ALE	C51
PSEN	CORE	IB-bus
	CPU
EA

Timer 0

INT

Parallel I/O Ports and Ext. Bus

Watch

Emul

10 bit

SPI

RD

Timer 1

Ctrl

Dog

Unit

ADC

Interface

Port 0

Port 1

Port 2

Port 3

Port 4

WR

P0

P1(1)

P2

P3

P4(2)

MOSI SCK MISO

RESET

T0 T1

INT0

INT1

Notes: 1. 8 analog Inputs/8 Digital I/O 2. 5-Bit I/O Port

2AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

Pin Configuration

			P1.3/AN3/CEX0		P1.2/AN2/ECI		P1.1/AN1/T2EX		P1.0/AN 0/T2		VAREF		VAGND		RESET		VSS		VCC		XTAL1		XTAL2
	6				5		4		3		2		1		44		43		42		41		40
P1.4/AN4/CEX1		7																					39				ALE
P1.5/AN5/CEX2		8																					38				PSEN
P1.6/AN6/CEX3		9																					37				P0.7/AD7
P1.7/AN7/CEX4		10																					36				P0.6/AD6
EA		11																					35				P0.5/AD5
P3.0/RxD		12									PLCC44												34				P0.4/AD4
P3.1/TxD		13																					33				P0.3/AD3
P3.2/INT0		14																					32				P0.2/AD2
P3.3/INT1		15																					31				P0.1/AD1
P3.4/T0		16																					30				P0.0/AD0
P3.5/T1		17																					29				P2.0/A8
		18			19		20		21		22		23		24		25		26		27		28
			P3.6/WR		P3.7/RD		P4.0/ TxDC		P4.1/RxDC		P2.7/A15		P2.6/A14		P2.5/A13		P2.4/A12		P2.3/A11		P2.2/A10		P2.1/A9

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2 VAREF VAGND RESET VSS

VCC

XTAL1

XTAL2

44 43 42 41 40 39 38 37 36 35 34

P1.4/AN4/CEX1

1

33

ALE

P1.5/AN5/CEX2

2

32

PSEN

P1.6/AN6/CEX3

3

31

P0.7/AD7

P1.7/AN7/CEX4

4

30

P0.6/AD6

EA

5

VQFP44

29

P0.5/AD5

P3.0/RxD

6

28

P0.4 /AD4

P3.1/TxD

7

27

P0.3 /AD3

P3.2/INT0

8

26

P0.2 /AD2

P3.3/INT1

9

25

P0.1 /AD1

P3.4/T0

10

24

P0.0 /AD0

P3.5/T1

11

23

P2.0/A8

12 13 14 15 16 17 18 19 20 21 22

P3.6/WR

P3.7/RD

P4.0/TxDC

P4.1/RxDC P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

3

4182N–CAN–03/08

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS TESTI VCC

VCC

XTAL1

XTAL2

7

6

5

4

3

2

1

52 51 50 49 48 47

P1.4/AN4/CEX1

8

46

ALE

P1.5/AN5/CEX2

9

45

PSEN

P1.6/AN6/CEX3

10

44

P0.7/AD7

P1.7/AN7/CEX4

11

43

P0.6/AD6

EA

12

42

NC

NC

13

PLCC52

41

P0.5/AD5

P3.0/RxD

14

40

P0.4 /AD4

P4.3/SCK

15

39

P0.3 /AD3

P3.1/TxD

16

38

P0.2 /AD2

P3.2/INT0

17

37

P0.1 /AD1

P3.3/INT1

18

36

P4.4/MOSI

P0.0 /AD0

P3.4/T0

19

35

P3.5/T1/SS

20

21 22 23 24 25 26 27 28 29 30 31 32 3334

P2.0/A8

P3.6/WR

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

NC

P2.5/A13 P2.4/A12 P2.3/A11

P2.2/A10

P2.1/A9

P4.2/MISO

TESTI must be connected to VSS

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN0/T2

VAREF VAGND

RESET

VSS VSS VSS TESTI VCC

VCC

VCC XTAL1 XTAL2

64

63

62

61

60

59

58

57

56

55

54

53

52

51

50

49

P1.4/AN4/CEX1			1																															48					NC
NC			2																															47					ALE
P1.5/AN5/CEX2			3																															46					PSEN
P1.6/AN6/CEX3			4																															45					P0.7/AD7
P1.7/AN7/CEX4			5																															44					P0.6/AD6
NC			6																															43					NC
EA			7												VQFP64																			42					P0.5/AD5
NC			8																															41					NC
NC			9																															40					NC
P3.0/RxD			10																															39					P0.4/AD4
P4.3/SCK			11																															38					P0.3/AD3
P3.1/TxD			12																															37					P0.2/AD2
P3.2/INT0			13																															36					P0.1/AD1
P3.3/INT1			14																															35					P4.4/MOSI
P3.4/T0			15																															34					P0.0/AD0
P3.5/T1/SS			16																															33					P2.0/A8
			17		18		19		20		21		22		23		24		25		26			27		28		29		30		31		32
			P3.6/WR		P3.7/RD		P4.0/TxDC		P4.1/RxDC		P2.7/A15		P2.6/A14		NC		NC		NC		NC			P2.5/A13		P2.4/A12		P2.3/A11		P2.2/A10		P2.1/A9		P4.2/MISO
										TESTI must be connected to VSS

4AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

Pin Name	Type	Description
VSS	GND	Circuit ground
TESTI	I	Must be connected to VSS
VCC		Supply Voltage
VAREF		Reference Voltage for ADC
VAGND		Reference Ground for ADC
P0.0:7	I/O	Port 0:
		Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as
		high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program
		and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s.
		Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.
P1.0:7	I/O	Port 1:
		Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for
		the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors
		and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current
		(IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog
		inputs via the ADCCF register (in this case the internal pull-ups are disconnected).
		As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and
		the PCA module I/O.
		P1.0/AN0/T2
		Analog input channel 0,
		External clock input for Timer/counter2.
		P1.1/AN1/T2EX
		Analog input channel 1,
		Trigger input for Timer/counter2.
		P1.2/AN2/ECI
		Analog input channel 2,
		PCA external clock input.
		P1.3/AN3/CEX0
		Analog input channel 3,
		PCA module 0 Entry of input/PWM output.
		P1.4/AN4/CEX1
		Analog input channel 4,
		PCA module 1 Entry of input/PWM output.
		P1.5/AN5/CEX2
		Analog input channel 5,
		PCA module 2 Entry of input/PWM output.
		P1.6/AN6/CEX3
		Analog input channel 6,
		PCA module 3 Entry of input/PWM output.
		P1.7/AN7/CEX4
		Analog input channel 7,
		PCA module 4 Entry ot input/PWM output.
		Port 1 receives the low-order address byte during EPROM programming and program verification.
		It can drive CMOS inputs without external pull-ups.
P2.0:7	I/O	Port 2:
		Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal
		pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of
		current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte
		during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses
		(MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data
		Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register.
		It also receives high-order addresses and control signals during program validation.
		It can drive CMOS inputs without external pull-ups.

5

4182N–CAN–03/08

Pin Name	Type	Description
P3.0:7	I/O	Port 3:
		Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal
		pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a
		source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups.
		The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for
		TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:
		P3.0/RxD:
		Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface
		P3.1/TxD:
		Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface
		P3.2/INT0:
		External interrupt 0 input/timer 0 gate control input
		P3.3/INT1:
		External interrupt 1 input/timer 1 gate control input
		P3.4/T0:
		Timer 0 counter input
		P3.5/T1/SS:
		Timer 1 counter input
		SPI Slave Select
		P3.6/WR:
		External Data Memory write strobe; latches the data byte from port 0 into the external data memory
		P3.7/RD:
		External Data Memory read strobe; Enables the external data memory.
		It can drive CMOS inputs without external pull-ups.
P4.0:4	I/O	Port 4:
		Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal
		pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of
		current (IIL, on the datasheet) because of the internal pull-up transistor.
		The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The
		secondary functions are assigned to the two pins of port 4 as follows:
		P4.0/TxDC:
		Transmitter output of CAN controller
		P4.1/RxDC:
		Receiver input of CAN controller.
		P4.2/MISO:
		Master Input Slave Output of SPI controller
		P4.3/SCK:
		Serial Clock of SPI controller
		P4.4/MOSI:
		Master Ouput Slave Input of SPI controller
		It can drive CMOS inputs without external pull-ups.

6AT89C51CC03

4182N–CAN–03/08

								AT89C51CC03
		Pin Name	Type		Description
					Reset:
		RESET	I/O		A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down
					resistor to VSS permits power-on reset using only an external capacitor to VCC.
					ALE:
		ALE	O		An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is
					activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are
					executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.
					PSEN:
					The Program Store Enable output is a control signal that enables the external program memory of the bus during external
		PSEN	O		fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when
					executing from of the external program memory two activations of PSEN are skipped during each access to the external Data
					memory. The PSEN is not activated for internal fetches.
					EA:
		EA	I		When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level,
					AT89C51CC03 fetches all instructions from the external program memory.
					XTAL1:
		XTAL1	I		Input of the inverting oscillator amplifier and input of the internal clock generator circuits.
					To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate
					above a frequency of 16 MHz, a duty cycle of 50% should be maintained.
		XTAL2	O		XTAL2:
					Output from the inverting oscillator amplifier.

I/O Configurations

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructions are referred to as Read-Modify-Write instructions. Each I/O line may be independently programmed as input or output.

Port 1, Port 3 and Port 4 Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Operation" section.

7

4182N–CAN–03/08

Port 0 and Port 2

Figure 1. Port 1, Port 3 and Port 4 Structure

VCC

ALTERNATE

INTERNAL

OUTPUT

READ

FUNCTION

PULL-UP (1)

LATCH

P1.x

P3.x

INTERNAL

P4.x

D P1.X Q

BUS

P3.X

P4.X

WRITE

LATCH

TO

CL

LATCH

READ

PIN

ALTERNATE

INPUT

FUNCTION

Note: The internal pull-up can be disabled on P1 when analog function is selected.

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET.

Figure 2. Port 0 Structure
		ADDRESS LOW/	CONTROL	VDD
		DATA
READ				(2)
LATCH				P0.x (1)
			1
INTERNAL			0
BUS	DP0.X	Q
WRITE	LATCH
TO
LATCH
READ
PIN

Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as address/data bus drivers.

2.Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

8AT89C51CC03

4182N–CAN–03/08

				AT89C51CC03
Figure 3. Port 2 Structure
		ADDRESS HIGH/ CONTROL		VDD
				INTERNAL
READ				PULL-UP (2)
LATCH				P2.x (1)
			1
INTERNAL			0
BUS	DP2.X	Q
WRITE	LATCH
TO
LATCH
READ
PIN

Read-Modify-Write

Instructions

4182N–CAN–03/08

Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus drivers.

2.Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.

Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "Read- Modify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:

Instruction	Description	Example
ANL	logical AND	ANL P1, A
ORL	logical OR	ORL P2, A
XRL	logical EX-OR	XRL P3, A
JBC	jump if bit = 1 and clear bit	JBC P1.1, LABEL
CPL	complement bit	CPL P3.0
INC	increment	INC P2
DEC	decrement	DEC P2
DJNZ	decrement and jump if not zero	DJNZ P3, LABEL
MOV Px.y, C	move carry bit to bit y of Port x	MOV P1.5, C
CLR Px.y	clear bit y of Port x	CLR P2.4
SET Px.y	set bit y of Port x	SET P3.3

It is not obvious the last three instructions in this list are Read-Modify-Write instructions. These instructions read the port (all 8 bits), modify the specifically addressed bit and

9

Quasi-Bidirectional Port

Operation

write the new byte back to the latch. These Read-Modify-Write instructions are directed to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.

Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output buffers (and therefore the pin state) update early in the instruction after Read-Modify- Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pullup (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pullups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

VCC VCC VCC

2 Osc. PERIODS

p1(1)			p2				p3

P1.x

P2.x

P3.x

P4.x

OUTPUT DATA				n

INPUT DATA

READ PIN

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

10 AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

SFR Mapping

The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following categories:

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
ACC	E0h	Accumulator	–	–	–	–	–	–	–	–
B	F0h	B Register	–	–	–	–	–	–	–	–
PSW	D0h	Program Status Word	CY	AC	F0	RS1	RS0	OV	F1	P
SP	81h	Stack Pointer	–	–	–	–	–	–	–	–
		Data Pointer Low
DPL	82h	byte	–	–	–	–	–	–	–	–
		LSB of DPTR
		Data Pointer High
DPH	83h	byte	–	–	–	–	–	–	–	–
		MSB of DPTR

	Mnemonic	Add	Name	7	6	5	4	3	2	1	0
	P0	80h	Port 0	–	–	–	–	–	–	–	–
	P1	90h	Port 1	–	–	–	–	–	–	–	–
	P2	A0h	Port 2	–	–	–	–	–	–	–	–
	P3	B0h	Port 3	–	–	–	–	–	–	–	–
	P4	C0h	Port 4 (x5)	–	–	–	P4.4 /	P4.3 /	P4.2 /	P4.1 /	P4.0 /
							MOSI	SCK	MISO	RxDC	TxDC

	Mnemonic	Add	Name	7	6	5	4	3	2	1	0
	TH0	8Ch	Timer/Counter 0 High	–	–	–	–	–	–	–	–
			byte
	TL0	8Ah	Timer/Counter 0 Low	–	–	–	–	–	–	–	–
			byte
	TH1	8Dh	Timer/Counter 1 High	–	–	–	–	–	–	–	–
			byte
	TL1	8Bh	Timer/Counter 1 Low	–	–	–	–	–	–	–	–
			byte
	TH2	CDh	Timer/Counter 2 High	–	–	–	–	–	–	–	–
			byte
	TL2	CCh	Timer/Counter 2 Low	–	–	–	–	–	–	–	–
			byte
	TCON	88h	Timer/Counter 0 and	TF1	TR1	TF0	TR0	IE1	IT1	IE0	IT0
			1 control
	TMOD	89h	Timer/Counter 0 and	GATE1	C/T1#	M11	M01	GATE0	C/T0#	M10	M00
			1 Modes

11

4182N–CAN–03/08

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

T2CON

C8h

Timer/Counter 2

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

control

T2MOD

C9h

Timer/Counter 2

–

–

–

–

–

–

T2OE

DCEN

Mode

Timer/Counter 2

RCAP2H

CBh

Reload/Capture High

–

–

–

–

–

–

–

–

byte

Timer/Counter 2

RCAP2L

CAh

Reload/Capture Low

–

–

–

–

–

–

–

–

byte

WDTRST

A6h

WatchDog Timer

–

–

–

–

–

–

–

–

Reset

WDTPRG

A7h

WatchDog Timer

–

–

–

–

–

S2

S1

S0

Program

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
SCON	98h	Serial Control	FE/SM0	SM1	SM2	REN	TB8	RB8	TI	RI
SBUF	99h	Serial Data Buffer	–	–	–	–	–	–	–	–
SADEN	B9h	Slave Address Mask	–	–	–	–	–	–	–	–
SADDR	A9h	Slave Address	–	–	–	–	–	–	–	–

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
CCON	D8h	PCA Timer/Counter Control	CF	CR	–	CCF4	CCF3	CCF2	CCF1	CCF0
CMOD	D9h	PCA Timer/Counter Mode	CIDL	WDTE	–	–	–	CPS1	CPS0	ECF
CL	E9h	PCA Timer/Counter Low byte	–	–	–	–	–	–	–	–
CH	F9h	PCA Timer/Counter High byte	–	–	–	–	–	–	–	–
CCAPM0	DAh	PCA Timer/Counter Mode 0		ECOM0	CAPP0	CAPN0	MAT0	TOG0	PWM0	ECCF0
CCAPM1	DBh	PCA Timer/Counter Mode 1		ECOM1	CAPP1	CAPN1	MAT1	TOG1	PWM1	ECCF1
CCAPM2	DCh	PCA Timer/Counter Mode 2	–	ECOM2	CAPP2	CAPN2	MAT2	TOG2	PWM2	ECCF2
CCAPM3	DDh	PCA Timer/Counter Mode 3		ECOM3	CAPP3	CAPN3	MAT3	TOG3	PWM3	ECCF3
CCAPM4	DEh	PCA Timer/Counter Mode 4		ECOM4	CAPP4	CAPN4	MAT4	TOG4	PWM4	ECCF4
CCAP0H	FAh	PCA Compare Capture Module 0 H	CCAP0H7	CCAP0H6	CCAP0H5	CCAP0H4	CCAP0H3	CCAP0H2	CCAP0H1	CCAP0H0
CCAP1H	FBh	PCA Compare Capture Module 1 H	CCAP1H7	CCAP1H6	CCAP1H5	CCAP1H4	CCAP1H3	CCAP1H2	CCAP1H1	CCAP1H0
CCAP2H	FCh	PCA Compare Capture Module 2 H	CCAP2H7	CCAP2H6	CCAP2H5	CCAP2H4	CCAP2H3	CCAP2H2	CCAP2H1	CCAP2H0
CCAP3H	FDh	PCA Compare Capture Module 3 H	CCAP3H7	CCAP3H6	CCAP3H5	CCAP3H4	CCAP3H3	CCAP3H2	CCAP3H1	CCAP3H0
CCAP4H	FEh	PCA Compare Capture Module 4 H	CCAP4H7	CCAP4H6	CCAP4H5	CCAP4H4	CCAP4H3	CCAP4H2	CCAP4H1	CCAP4H0
CCAP0L	EAh	PCA Compare Capture Module 0 L	CCAP0L7	CCAP0L6	CCAP0L5	CCAP0L4	CCAP0L3	CCAP0L2	CCAP0L1	CCAP0L0
CCAP1L	EBh	PCA Compare Capture Module 1 L	CCAP1L7	CCAP1L6	CCAP1L5	CCAP1L4	CCAP1L3	CCAP1L2	CCAP1L1	CCAP1L0
CCAP2L	ECh	PCA Compare Capture Module 2 L	CCAP2L7	CCAP2L6	CCAP2L5	CCAP2L4	CCAP2L3	CCAP2L2	CCAP2L1	CCAP2L0
CCAP3L	EDh	PCA Compare Capture Module 3 L	CCAP3L7	CCAP3L6	CCAP3L5	CCAP3L4	CCAP3L3	CCAP3L2	CCAP3L1	CCAP3L0
CCAP4L	EEh	PCA Compare Capture Module 4 L	CCAP4L7	CCAP4L6	CCAP4L5	CCAP4L4	CCAP4L3	CCAP4L2	CCAP4L1	CCAP4L0

12 AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

	Mnemonic	Add	Name	7	6	5	4	3	2	1	0
	IEN0	A8h	Interrupt Enable	EA	EC	ET2	ES	ET1	EX1	ET0	EX0
			Control 0
	IEN1	E8h	Interrupt Enable	–	–	–	–	ESPI	ETIM	EADC	ECAN
			Control 1
	IPL0	B8h	Interrupt Priority	–	PPC	PT2	PS	PT1	PX1	PT0	PX0
			Control Low 0
	IPH0	B7h	Interrupt Priority	–	PPCH	PT2H	PSH	PT1H	PX1H	PT0H	PX0H
			Control High 0
	IPL1	F8h	Interrupt Priority	–	–	–	–	SPIL	POVRL	PADCL	PCANL
			Control Low 1
	IPH1	F7h	Interrupt Priority	–	–	–	–	SPIH	POVRH	PADCH	PCANH
			Control High1

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
ADCON	F3h	ADC Control	–	PSIDLE	ADEN	ADEOC	ADSST	SCH2	SCH1	SCH0
ADCF	F6h	ADC Configuration	CH7	CH6	CH5	CH4	CH3	CH2	CH1	CH0
ADCLK	F2h	ADC Clock	–	–	–	PRS4	PRS3	PRS2	PRS1	PRS0
ADDH	F5h	ADC Data High byte	ADAT9	ADAT8	ADAT7	ADAT6	ADAT5	ADAT4	ADAT3	ADAT2
ADDL	F4h	ADC Data Low byte	–	–	–	–	–	–	ADAT1	ADAT0

	Mnemonic	Add	Name	7	6	5	4	3	2	1	0
	CANGCON	ABh	CAN General	ABRQ	OVRQ	TTC	SYNCTTC	AUT–	TEST	ENA	GRES
			Control					BAUD
	CANGSTA	AAh	CAN General	–	OVFG	–	TBSY	RBSY	ENFG	BOFF	ERRP
			Status
	CANGIT	9Bh	CAN General	CANIT	–	OVRTIM	OVRBUF	SERG	CERG	FERG	AERG
			Interrupt
	CANBT1	B4h	CAN Bit Timing 1	–	BRP5	BRP4	BRP3	BRP2	BRP1	BRP0	–
	CANBT2	B5h	CAN Bit Timing 2	–	SJW1	SJW0	–	PRS2	PRS1	PRS0	–
	CANBT3	B6h	CAN Bit Timing 3	–	PHS22	PHS21	PHS20	PHS12	PHS11	PHS10	SMP
	CANEN1	CEh	CAN Enable	–	ENCH14	ENCH13	ENCH12	ENCH11	ENCH10	ENCH9	ENCH8
			Channel byte 1
	CANEN2	CFh	CAN Enable	ENCH7	ENCH6	ENCH5	ENCH4	ENCH3	ENCH2	ENCH1	ENCH0
			Channel byte 2
	CANGIE	C1h	CAN General	–	–	ENRX	ENTX	ENERCH	ENBUF	ENERG	–
			Interrupt Enable
			CAN Interrupt
	CANIE1	C2h	Enable Channel	–	IECH14	IECH13	IECH12	IECH11	IECH10	IECH9	IECH8
			byte 1

13

4182N–CAN–03/08

Mnemonic

Add

Name

7

6

5

4

3

2

1

0

CAN Interrupt

CANIE2

C3h

Enable Channel

IECH7

IECH6

IECH5

IECH4

IECH3

IECH2

IECH1

IECH0

byte 2

CAN Status

CANSIT1

BAh

Interrupt Channel

–

SIT14

SIT13

SIT12

SIT11

SIT10

SIT9

SIT8

byte1

CAN Status

CANSIT2

BBh

Interrupt Channel

SIT7

SIT6

SIT5

SIT4

SIT3

SIT2

SIT1

SIT0

byte2

CANTCON

A1h

CAN Timer

TPRESC 7

TPRESC 6

TPRESC 5

TPRESC 4

TPRESC 3

TPRESC 2

TPRESC 1

TPRESC 0

Control

CANTIMH

ADh

CAN Timer high

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM

CANTIM 9

CANTIM 8

15

14

13

12

11

10

CANTIML

ACh

CAN Timer low

CANTIM 7

CANTIM 6

CANTIM 5

CANTIM 4

CANTIM 3

CANTIM 2

CANTIM 1

CANTIM 0

CANSTMP

AFh

CAN Timer Stamp

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

H

high

15

14

13

12

11

10

9

8

CANSTMP

AEh

CAN Timer Stamp

TIMSTMP7

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

TIMSTMP

L

low

6

5

4

3

2

1

0

CANTTCH

A5h

CAN Timer TTC

TIMTTC 15

TIMTTC 14

TIMTTC 13

TIMTTC 12

TIMTTC 11

TIMTTC 10

TIMTTC

TIMTTC

high

9

8

CANTTCL

A4h

CAN Timer TTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

TIMTTC

low

7

6

5

4

3

2

1

0

CANTEC

9Ch

CAN Transmit

TEC7

TEC6

TEC5

TEC4

TEC3

TEC2

TEC1

TEC0

Error Counter

CANREC

9Dh

CAN Receive

REC7

REC6

REC5

REC4

REC3

REC2

REC1

REC0

Error Counter

CANPAGE

B1h

CAN Page

CHNB3

CHNB2

CHNB1

CHNB0

AINC

INDX2

INDX1

INDX0

CANSTCH

B2h

CAN Status

DLCW

TXOK

RXOK

BERR

SERR

CERR

FERR

AERR

Channel

CANCONC

B3h

CAN Control

CONCH1

CONCH0

RPLV

IDE

DLC3

DLC2

DLC1

DLC0

H

Channel

CANMSG

A3h

CAN Message

MSG7

MSG6

MSG5

MSG4

MSG3

MSG2

MSG1

MSG0

Data

CAN Identifier Tag

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

IDT4

IDT3

byte 1(Part A)

CANIDT1

BCh

CAN Identifier Tag

IDT28

IDT27

IDT26

IDT25

IDT24

IDT23

IDT22

IDT21

byte 1(PartB)

CAN Identifier Tag

IDT2

IDT1

IDT0

–

–

–

–

–

byte 2 (PartA)

CANIDT2

BDh

CAN Identifier Tag

IDT20

IDT19

IDT18

IDT17

IDT16

IDT15

IDT14

IDT13

byte 2 (PartB)

CAN Identifier Tag

–

–

–

–

–

–

–

–

byte 3(PartA)

CANIDT3

BEh

CAN Identifier Tag

IDT12

IDT11

IDT10

IDT9

IDT8

IDT7

IDT6

IDT5

byte 3(PartB)

14 AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
		CAN Identifier Tag	–	–	–	–	–		–
		byte 4(PartA)
CANIDT4	BFh							RTRTAG		RB0TAF
		CAN Identifier Tag
			IDT4	IDT3	IDT2	IDT1	IDT0		RB1TAG
		byte 4(PartB)
		CAN Identifier
		Mask byte	IDMSK10	IDMSK9	IDMSK8	IDMSK7	IDMSK6	IDMSK5	IDMSK4	IDMSK3
		1(PartA)
CANIDM1	C4h
		CAN Identifier
			IDMSK28	IDMSK27	IDMSK26	IDMSK25	IDMSK24	IDMSK23	IDMSK22	IDMSK21
		Mask byte
		1(PartB)
		CAN Identifier
		Mask byte	IDMSK2	IDMSK1	IDMSK0	–	–	–	–	–
		2(PartA)
CANIDM2	C5h
		CAN Identifier
			IDMSK20	IDMSK19	IDMSK18	IDMSK17	IDMSK16	IDMSK15	IDMSK14	IDMSK13
		Mask byte
		2(PartB)
		CAN Identifier
		Mask byte	–	–	–	–	–	–	–	–
		3(PartA)
CANIDM3	C6h
		CAN Identifier
			IDMSK12	IDMSK11	IDMSK10	IDMSK9	IDMSK8	IDMSK7	IDMSK6	IDMSK5
		Mask byte
		3(PartB)
		CAN Identifier
		Mask byte	–	–	–	–	–
		4(PartA)
CANIDM4	C7h							RTRMSK	–	IDEMSK
		CAN Identifier
			IDMSK4	IDMSK3	IDMSK2	IDMSK1	IDMSK0
		Mask byte
		4(PartB)

	Mnemonic	Add	Name	7	6	5	4	3	2	1	0
	SPCON	D4h	SPI Control	SPR2	SPEN	SSDIS	MSTR	CPOL	CPHA	SPR1	SPR0
	SPSCR	D5h	SPI Status and	SPIF	-	OVR	MODF	SPTE	UARTM	SPTEIE	MOFIE
			Control
	SPDAT	D6h	SPI Data	-	-	-	-	-	-	-	-

Mnemonic	Add	Name	7	6	5	4	3	2	1	0
PCON	87h	Power Control	SMOD1	SMOD0	–	POF	GF1	GF0	PD	IDL
AUXR	8Eh	Auxiliary Register 0	DPU	VPFDP	M0	XRS2	XRS1	XRS0	EXTRAM	A0
AUXR1	A2h	Auxiliary Register 1	–	–	ENBOOT	–	GF3	0	–	DPS
CKCON0	8Fh	Clock Control 0	CANX2	WDX2	PCAX2	SIX2	T2X2	T1X2	T0X2	X2
CKCON1	9Fh	Clock Control 1	-	-	-	-	-	-	-	SPIX2
FCON	D1h	Flash Control	FPL3	FPL2	FPL1	FPL0	FPS	FMOD1	FMOD0	FBUSY
EECON	D2h	EEPROM Contol	EEPL3	EEPL2	EEPL1	EEPL0	–	–	EEE	EEBUSY
FSTA	D3	Flash Status	-	-	-	-	-	-	SEQERR	FLOAD

15

4182N–CAN–03/08

Table 1. SFR Mapping

		0/8(2)	1/9	2/A	3/B	4/C	5/D	6/E	7/F
	F8h	IPL1	CH	CCAP0H	CCAP1H	CCAP2H	CCAP3H	CCAP4H
		xxxx x000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000
	F0h	B		ADCLK	ADCON	ADDL	ADDH	ADCF	IPH1
		0000 0000		xxx0 0000	x000 0000	0000 0000	0000 0000	0000 0000	xxxx x000
	E8h	IEN1	CL	CCAP0L	CCAP1L	CCAP2L	CCAP3L	CCAP4L
		xxxx x000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000
	E0h	ACC
		0000 0000
	D8h	CCON	CMOD	CCAPM0	CCAPM1	CCAPM2	CCAPM3	CCAPM4
		0000 0000	00xx x000	x000 0000	x000 0000	x000 0000	x000 0000	x000 0000
	D0h	PSW	FCON	EECON	FSTA	SPCON	SPSCR	SPDAT
		0000 0000	0000 0000	xxxx xx00	xxxx xx00	0001 0100	0000 0000	xxxx xxxx
	C8h	T2CON	T2MOD	RCAP2L	RCAP2H	TL2	TH2	CANEN1	CANEN2
		0000 0000	xxxx xx00	0000 0000	0000 0000	0000 0000	0000 0000	x000 0000	0000 0000
	C0h	P4	CANGIE	CANIE1	CANIE2	CANIDM1	CANIDM2	CANIDM3	CANIDM4
		xxx1 1111	xx00 000x	x000 0000	0000 0000	xxxx xxxx	xxxx xxxx	xxxx xxxx	xxxx xxxx
	B8h	IPL0	SADEN	CANSIT1	CANSIT2	CANIDT1	CANIDT2	CANIDT3	CANIDT4
		x000 0000	0000 0000	0000 0000	0000 0000	xxxx xxxx	xxxx xxxx	xxxx xxxx	xxxx xxxx
	B0h	P3	CANPAGE	CANSTCH	CANCONCH	CANBT1	CANBT2	CANBT3	IPH0
		1111 1111	0000 0000	xxxx xxxx	xxxx xxxx	xxxx xxxx	xxxx xxxx	xxxx xxxx	x000 0000
	A8h	IEN0	SADDR	CANGSTA	CANGCON	CANTIML	CANTIMH	CANSTMPL	CANSTMPH
		0000 0000	0000 0000	x0x0 0000	0000 0x00	0000 0000	0000 0000	0000 0000	0000 0000
	A0h	P2	CANTCON	AUXR1	CANMSG	CANTTCL	CANTTCH	WDTRST	WDTPRG
		1111 1111	0000 0000	xxxx 00x0	xxxx xxxx	0000 0000	0000 0000	1111 1111	xxxx x000
	98h	SCON	SBUF		CANGIT	CANTEC	CANREC		CKCON1
		0000 0000	0000 0000		0x00 0000	0000 0000	0000 0000		xxxx xxx0
	90h	P1
		1111 1111
	88h	TCON	TMOD	TL0	TL1	TH0	TH1	AUXR	CKCON0
		0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	0000 0000	x001 0100	0000 0000
	80h	P0	SP	DPL	DPH				PCON
		1111 1111	0000 0111	0000 0000	0000 0000				00x1 0000
		0/8(2)	1/9	2/A	3/B	4/C	5/D	6/E	7/F

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

Reserved

Note: 1.	Do not read or write Reserved Registers
2.	These registers are bit–addressable.
	Sixteen addresses in the SFR space are both byte–addressable and bit–addressable. The bit–addressable SFR’s are those
	whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

16 AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

Clock

The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages:

•Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.

•Saves power consumption while keeping the same CPU power (oscillator power saving).

•Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.

•Increases CPU power by 2 while keeping the same crystal frequency.

	In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
	XTAL1 signal and the main clock input of the core (phase generator). This divider may
	be disabled by the software.
	An extra feature is available to start after Reset in the X2 mode. This feature can be
	enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section
	"In-System Programming".
Description	The X2 bit in the CKCON register (see Table 2) allows switching from 12 clock cycles
	per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
	(STD mode).
	Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure
	5.).
	The Timers 0, 1 and 2, Uart, PCA, WatchDog or CAN switch in X2 mode only if the cor-
	responding bit is cleared in the CKCON register.
	The clock for the whole circuit and peripheral is first divided by two before being used by
	the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
	input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
	ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2
	bit is validated on the XTAL1 2 rising edge to avoid glitches when switching from the X2
	to the STD mode. Figure 6 shows the mode switching waveforms.

17

4182N–CAN–03/08

Figure 5. Clock CPU Generation Diagram

		X2B			PCON.0
	Hardware byte			On RESET
					IDL

	X2
	CKCON.0
XTAL1	2	0
		1
XTAL2
	PD
	PCON.1

CPU Core

Clock

CPU

CLOCK

CPU Core Clock Symbol

and ADC

2	1
	FT0 Clock
	0

																																																																		2										1															FT1 Clock
																																																																												0
																																																							2											1																									FT2 Clock
																																																																		0
																																												2											1																																				FUart Clock
																																																							0
																																	2											1																																															FPca Clock
																																												0
																						2											1																																																										FWd Clock
																																	0
										2												1																																																																					FCan Clock
																						0
			2							1																																																																																	FSPIClock
										0
		X2																																																																																									PERIPH
		CKCON.0
																																																																																											CLOCK
																																																																																							Peripheral
									SPIX2											CANX2												WDX2										PCAX2												SIX2											T2X2										T1X2									T0X2
																																																																																							Clock Symbol
							CKCON1.0 CKCON0.7 CKCON0.6 CKCON0.5																																													CKCON0.4 CKCON0.3 CKCON0.2 CKCON0.1

18 AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

Figure 6. Mode Switching Waveforms

XTAL1
XTAL1/2
X2 bit
CPU clock
STD Mode	X2 Mode	STD Mode

Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.

19

4182N–CAN–03/08

Registers

Table 2. CKCON0 Register

CKCON0 (S:8Fh)

Clock Control Register

7

6

5

4

3

2

1

0

CANX2

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Bit

Number

Mnemonic

Description

CAN clock (1)

7

CANX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

WatchDog clock (1)

6

WDX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock (1)

5

PCAX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2) (1)

4

SIX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock (1)

3

T2X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer1 clock (1)

2

T1X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer0 clock (1)

1

T0X2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

0

X2

the peripherals.

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2"bits.

Note:

1.

This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

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AT89C51CC03

Table 3. CKCON1 Register

CKCON1 (S:9Fh)

Clock Control Register 1

7	6	5	4	3	2		1		0
									SPIX2
Bit	Bit
Number	Mnemonic	Description
7-1	-	Reserved
		The value read from these bits is indeterminate. Do not set these bits.
		SPI clock (1)
0	SPIX2	Clear to select 6 clock periods per peripheral clock cycle.
		Set to select 12 clock periods per peripheral clock cycle.
Note: 1.	This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit
	has no effect.

Reset Value = 0000 0000b

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Data Memory

The AT89C51CC03 provides data memory access in two different spaces:

1.The internal space mapped in three separate segments:

• the lower 128 Bytes RAM segment.

• the upper 128 Bytes RAM segment.

• the expanded 2048 Bytes RAM segment (ERAM).

2.The external space.

A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 8 shows the internal and external data memory spaces organization.

Figure 7. Internal Memory - RAM

FFh	Upper	FFh	Special
	128 Bytes		Function
	Internal RAM		Registers
	indirect addressing		direct addressing
80h		80h
7Fh
	Lower
	128 Bytes
	Internal RAM
	direct or indirect
00h	addressing

Figure 8. Internal and External Data Memory Organization ERAM-XRAM

FFFFh

64K Bytes

External XRAM

		FFh or		7FFh
	256 up to 2048 Bytes
	Internal ERAM				EXTRAM = 1
00h	EXTRAM = 0			0000h
	Internal				External

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								AT89C51CC03
	Internal Space
	Lower 128 Bytes RAM	The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh
		using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4
		banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6)
		select which bank is in use according to Table 4. This allows more efficient use of code
		space, since register instructions are shorter than instructions that use direct address-
		ing, and can be used for context switching in interrupt service routines.
		Table 4. Register Bank Selection
		RS1	RS0		Description
		0	0		Register bank 0 from 00h to 07h
		0	1		Register bank 0 from 08h to 0Fh
		1	0		Register bank 0 from 10h to 17h
		1	1		Register bank 0 from 18h to 1Fh
		The next 16 Bytes above the register banks form a block of bit-addressable memory
		space. The C51 instruction set includes a wide selection of single-bit instructions, and
		the 128 bits in this area can be directly addressed by these instructions. The bit
		addresses in this area are 00h to 7Fh.
		Figure 9. Lower 128 Bytes Internal RAM Organization
					7Fh
				30h
					2Fh		Bit-Addressable Space
				20h			(Bit Addresses 0-7Fh)
				18h	1Fh
				10h	17h		4 Banks of
							8 Registers
					0Fh
				08h			R0-R7
				00h	07h
	Upper 128 Bytes RAM
		The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect
		addressing mode.
	Expanded RAM	The on-chip 2048 Bytes of expanded RAM (ERAM) are accessible from address 0000h
		to 07FFh using indirect addressing mode through MOVX instructions. In this address
		range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the
		XRAM. As shown in Figure 8 when EXTRAM = 0, the ERAM is selected and when
		EXTRAM = 1, the XRAM is selected.

The size of ERAM can be configured by XRS2-0 bit in AUXR register (default size is 2048 Bytes).

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.

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External Space

Memory Interface

The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (RD#, WR#, and ALE).

Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5 describes the external memory interface signals.

Figure 10. External Data Memory Interface Structure

AT89C51CC03		RAM
		PERIPHERAL
P2	A15:8	A15:8
ALE
AD7:0	Latch	A7:0
P0		A7:0
		D7:0
RD#		OE
WR#		WR

Table 5. External Data Memory Interface Signals

	Signal			Alternative
	Name	Type	Description	Function
	A15:8	O	Address Lines	P2.7:0
			Upper address lines for the external bus.
			Address/Data Lines
	AD7:0	I/O	Multiplexed lower address lines and data for the external	P0.7:0
			memory.
			Address Latch Enable
	ALE	O	ALE signals indicates that valid address information are available	-
			on lines AD7:0.
	RD#	O	Read	P3.7
			Read signal output to external data memory.
	WR#	O	Write	P3.6
			Write signal output to external memory.
External Bus Cycles
	This section describes the bus cycles the AT89C51CC03 executes to read (see
	Figure 11), and write data (see Figure 12) in the external data memory.
	External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator
	clock period in standard mode or 6 oscillator clock periods in X2 mode. For further infor-
	mation on X2 mode.

Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and WR# signals from 3 to 15 CPU clock periods.

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics” of the AT89C51CC03 datasheet.

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AT89C51CC03

Figure 11. External Data Read Waveforms

CPU Clock
ALE
RD#1
P0	DPL or Ri	D7:0
P2		DPH or P22

Notes: 1.

RD# signal may be stretched using M0 bit in AUXR register.

2.

When executing MOVX @Ri instruction, P2 outputs SFR content.

Figure 12. External Data Write Waveforms

CPU Clock

ALE

WR#1

P0

DPL or Ri

D7:0

P2

DPH or P22

Notes: 1.

WR# signal may be stretched using M0 bit in AUXR register.

2.

When executing MOVX @Ri instruction, P2 outputs SFR content.

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Dual Data Pointer

Description

The AT89C51CC03 implements a second data pointer for speeding up code execution

and reducing code size in case of intensive usage of external memory accesses.

DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data

pointer 1 (see Figure 13).

Figure 13. Dual Data Pointer Implementation

DPL0

0

DPL

DPL1

1

DPTR0

DPS

AUXR1.0

DPTR

DPTR1

DPH0

0

DPH

Application

DPH1

1

Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.

;ASCII block move using dual data pointers

;Modifies DPTR0, DPTR1, A and PSW

;Ends when encountering NULL character

;Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator

end_move:

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Registers

Table 6.

PSW Register

PSW (S:8Eh)

Program Status Word Register

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

F1

P

Bit

Bit

Number

Mnemonic

Description

7

CY

Carry Flag

Carry out from bit 1 of ALU operands.

6

AC

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

5

F0

User Definable Flag 0.

4-3

RS1:0

Register Bank Select Bits

Refer to Table 4 for bits description.

2

OV

Overflow Flag

Overflow set by arithmetic operations.

1

F1

User Definable Flag 1

Parity Bit

0

P

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

Reset Value = 0000 0000b

Table 7.

AUXR Register

AUXR (S:8Eh)

Auxiliary Register

7

6

5

4

3

2

1

0

-

-

M0

XRS2

XRS1

XRS0

EXTRAM

A0

Bit

Bit

Number

Mnemonic

Description

7-6

-

Reserved

The value read from these bits are indeterminate. Do not set this bit.

Stretch MOVX control:

the RD/ and the WR/ pulse length is increased according to the value of M0.

5

M0

M0

Pulse length in clock period

0

6

1

30

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Bit

Bit

Number

Mnemonic

Description

ERAM size:

Accessible size of the ERAM

XRS 2:0 ERAM size

000

256 Bytes

001

512 Bytes

4-2

XRS1-0

010

768 Bytes

011

1024 Bytes

100

1792 Bytes

101

2048 Bytes (default configuration after reset)

110

Reserved

111

Reserved

Internal/External RAM (00h - FFh)

1

EXTRAM

access using MOVX @ Ri/@ DPTR

0 - Internal ERAM access using MOVX @ Ri/@ DPTR.

1 - External data memory access.

Disable/Enable ALE)

0

A0

0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2

mode is used)

1 - ALE is active only during a MOVX or MOVC instruction.

Reset Value = X001 0100b

Not bit addressable

Table 8.

AUXR1 Register

AUXR1 (S:A2h)

Auxiliary Control Register 1

7

6

5

4

3

2

1

0

-

-

ENBOOT

-

GF3

0

-

DPS

Bit

Bit

Number

Mnemonic

Description

7-6

-

Reserved

The value read from these bits is indeterminate. Do not set these bits.

Enable Boot Flash

5

ENBOOT

Set this bit for map the boot Flash between F800h -FFFFh

Clear this bit for disable boot Flash.

4

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

3

GF3

General-purpose Flag 3

Always Zero

2

0

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

1

-

Reserved for Data Pointer Extension.

Data Pointer Select Bit

0

DPS

Set to select second dual data pointer: DPTR1.

Clear to select first dual data pointer: DPTR0.

Reset Value = XXXX 00X0b

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Power Monitor

Description

The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them.

By generating the Reset the Power Monitor insures a correct start up when AT89C51CC03 is powered up.

In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation and power going down. See Figure 14.

Figure 14. Power Monitor Block Diagram

VCC

Regulated

CPU core

Power On Reset

Supply

Memories

Power Fail Detect

Voltage Regulator

XTAL1

Peripherals

(1)

Internal Reset

RST pin

PCA

Hardware

Watchdog

Watchdog

Note: 1. Once XTAL1 high and low levels reach above and below VIH/VIL a 1024 clock period delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect thresthold level, the reset will be applied immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.

The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 15.

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Figure 15. Power Fail Detect

Vcc

t

Reset

Vcc

When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

.

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