ATMEL AT89C51CC03 User Manual

BDTIC www.bdtic.com/ATMEL

Features

• 80C51 Core Architecture

• 256 Bytes of On-chip RAM

• 2048 Bytes of On-chip ERAM

• 64K Bytes of On-chip Flash Memory

– Data Retention: 10 Years at 85°C – Read/Write Cycle: 100K

• 2K Bytes of On-chip Flash for Bootloader

• 2K Bytes of On-chip EEPROM

Read/Write Cycle: 100K

• Integrated Power Monitor (POR: PFD) To Supervise Internal Power Supply

• 14-sources 4-level Interrupts

• Three 16-bit Timers/Counters

• Full Duplex UART Compatible 80C51

• High-speed Architecture

– In Standard Mode:

40 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 60 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

– In X2 mode (6 Clocks/machine cycle)

20 MHz (Vcc 3V to 5.5V, both Internal and external code execution) 30 MHz (Vcc 4.5V to 5.5V and Internal Code execution only)

• Five Ports: 32 + 4 Digital I/O Lines

• Five-channel 16-bit PCA with

– PWM (8-bit) – High-speed Output – Timer and Edge Capture

• Double Data Pointer

• 21-bit WatchDog Timer (7 Programmable Bits)

• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

• SPI Interface, (PLCC52 and VPFP64 packages only)

• Full CAN Controller

– Fully Compliant with CAN Rev 2.0A and 2.0B – Optimized Structure for Communication Management (Via SFR) – 15 Independent Message Objects

– Each Message Object Programmable on Transmission or Reception – Individual Tag and Mask Filters up to 29-bit Identifier/Channel – 8-byte Cyclic Data Register (FIFO)/Message Object – 16-bit Status and Control Register/Message Object – 16-bit Time-Stamping Register/Message Object – CAN Specification 2.0 Part A or 2.0 Part B Programmable for Each Message Object – Access to Message Object Control and Data Registers Via SFR – Programmable Reception Buffer Length Up To 15 Message Objects – Priority Management of Reception of Hits on Several Message Objects at the Same Time (Basic CAN Feature) – Priority Management for Transmission – Message Object Overrun Interrupt

– Supports

– Time Triggered Communication – Autobaud and Listening Mode

– Programmable Automatic Reply Mode – 1-Mbit/s Maximum Transfer Rate at 8 MHz – Readable Error Counters – Programmable Link to On-chip Timer for Time Stamping and Network

Synchronization – Independent Baud Rate Prescaler – Data, Remote, Error and Overload Frame Handling

1. At BRP = 1 sampling point will be fixed.

(1)

Crystal Frequency in X2 Mode

Enhanced 8-bit MCU with CAN Controller and Flash Memory

AT89C51CC03

Rev. 4182N–CAN–03/08

AT89C51CC03

•

Timer 0

INT

RAM

256x8

RxD

TxD

PSEN

ALE

XTAL2

XTAL1

UART

CPU

Timer 1

INT1

Ctrl

INT0

C51

CORE

Port 0P0Port 1

Port 2

Port 3

Parallel I/O Ports and Ext. Bus

P1(1)

ERAM

2048

IB-bus

PCA

RESET

Watch

Dog

PCA

ECI

Vss

Vcc

Timer2

T2EX

Port 4

P4(2)

Emul

Unit

10 bit

ADC

Flash

64k x

Boot

loader

2kx8

PROM

2kx8

CAN

CONTROLLER

TxDC

RxDC

SPI

Interface

MOSI

SCK

MISO

On-chip Emulation Logic (Enhanced Hook System)

•

Power Saving Modes

– Idle Mode – Power-down Mode

•

Power Supply: 3 volts to 5.5 volts

•

Temperature Range: Industrial (-40° to +85°C), Automotive (-40°C to +125°C)

•

Packages: VQFP44, PLCC44, VQFP64, PLCC52

Description

Block Diagram

The AT89C51CC03 is a member of the family of 8-bit microcontrollers dedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Besides the full CAN controller AT89C51CC03 provides 64K Bytes of Flash memory including In-System Programming (ISP), 2K Bytes Boot Flash Memory, 2K Bytes EEPROM and 2048 byte ERAM.

Primary attenti o n i s pai d to th e red u ction of the electro- magnetic emission o f AT89C51CC03.

Notes: 1. 8 analog Inputs/8 Digital I/O

2. 5-Bit I/O Port

4182N–CAN–03/08

Pin Configuration

PLCC44

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7/RD

P4.0/ TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

39 38 37 36 35 34 33 32

7 8 9 10 11 12 13 14

1819202122232425262728

65432

4443424140

ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.1/AD1 P0.0/AD0 P2.0/A8

P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD P3.2/INT0 P3.3/INT1

P3.4/T0 P3.5/T1

43 42 41 40 3944

38 37 36 35 34

12 13 17161514 201918 21 22

33 32

26 25

VQFP44

P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD P3.2/INT0 P3.3/INT1

P3.4/T0 P3.5/T1

ALE PSEN P0.7/AD7 P0.6/AD6 P0.5/AD5

P0.2 /AD2

P0.3 /AD3

P0.4 /AD4

P0.1 /AD1 P0.0 /AD0 P2.0/A8

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

AT89C51CC03

4182N–CAN–03/08

AT89C51CC03

21 22 26252423 292827 30 31

5 4 3 2 1 6

52 51 50 49 48

40 39

PLCC52

7 47

32 33

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN 0/T2

VAREF

VAGND

RESET

VSS

VCC

XTAL1

XTAL2

TESTI

P1.4/AN4/CEX1 P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4

P3.0/RxD

P3.1/TxD P3.2/INT0 P3.3/INT1

P3.4/T0

P3.5/T1/SS

P4.3/SCK

ALE PSEN P0.7/AD7 P0.6/AD6

P0.5/AD5

P0.2 /AD2

P0.3 /AD3

P0.4 /AD4

P0.1 /AD1

P0.0 /AD0

P2.0/A8

P4.4/MOSI

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P3.6/WR

P4.2/MISO

TESTI must be connected to VSS

VCC

5453525150

VQFP64

P1.3/AN3/CEX0

P1.2/AN2/ECI

P1.1/AN1/T2EX

P1.0/AN0/T2

VAREF

VAGND

RESET

VSS

P3.7/RD

P4.0/TxDC

P4.1/RxDC

P2.7/A15

P2.6/A14

NCNCNC

P3.6/WR

48 47 46 45 44 43 42 41

1 2 3 4 5 6 7 8

171819202122232425

646362616059585756

NC ALE PSEN P0.7/AD7 P0.6/AD6

P0.5/AD5

NC P0.4/AD4

P1.4/AN4/CEX1

NC P1.5/AN5/CEX2 P1.6/AN6/CEX3 P1.7/AN7/CEX4

P3.0/RxD

11 12 13

P4.3/SCK

P3.1/TxD P3.2/INT0 P3.3/INT1

P3.4/T0

P3.5/T1/SS

38 37 36

P0.1/AD1

P0.2/AD2

P0.3/AD3

P4.4/MOSI P0.0/AD0 P2.0/A8

P2.5/A13

P2.4/A12

P2.3/A11

P2.2/A10

P2.1/A9

P4.2/MISO

2728293031

TESTI

VCC

XTAL1

XTAL2

VCC

TESTI must be connected to VSS

4182N–CAN–03/08

Pin Name Type Description

VSS GND Circuit ground

TESTI I Must be connected to VSS

VCC Supply Voltage

VAREF Reference Voltage for ADC

VAGND Reference Ground for ADC

P0.0:7 I/O Port 0:

Is an 8-bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in this state can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory. In this application it uses strong internal pull-ups when emitting 1’s. Port 0 also outputs the code Bytes during program validation. External pull-ups are required during program verification.

AT89C51CC03

P1.0:7 I/O Port 1:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled low externally will be the source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 1 pins are assigned to be used as analog inputs via the ADCCF register (in this case the internal pull-ups are disconnected). As a secondary digital function, port 1 contains the Timer 2 external trigger and clock input; the PCA external clock input and the PCA module I/O.

P1.0/AN0/T2 Analog input channel 0, External clock input for Timer/counter2.

P1.1/AN1/T2EX Analog input channel 1, Trigger input for Timer/counter2.

P1.2/AN2/ECI Analog input channel 2, PCA external clock input.

P1.3/AN3/CEX0 Analog input channel 3, PCA module 0 Entry of input/PWM output.

P1.4/AN4/CEX1 Analog input channel 4, PCA module 1 Entry of input/PWM output.

P1.5/AN5/CEX2 Analog input channel 5, PCA module 2 Entry of input/PWM output.

P1.6/AN6/CEX3 Analog input channel 6, PCA module 3 Entry of input/PWM output.

P1.7/AN7/CEX4 Analog input channel 7, PCA module 4 Entry ot input/PWM output. Port 1 receives the low-order address byte during EPROM programming and program verification. It can drive CMOS inputs without external pull-ups.

P2.0:7 I/O Port 2:

4182N–CAN–03/08

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 2 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. Port 2 emits the high-order address byte during accesses to the external Program Memory and during accesses to external Data Memory that uses 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1’s. During accesses to external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 transmits the contents of the P2 special function register. It also receives high-order addresses and control signals during program validation. It can drive CMOS inputs without external pull-ups.

AT89C51CC03

Pin Name Type Description

P3.0:7 I/O Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s written to them are pulled high by the internal pull-up transistors and can be used as inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a source of current (IIL, see section "Electrical Characteristic") because of the internal pull-ups. The output latch corresponding to a secondary function must be programmed to one for that function to operate (except for TxD and WR). The secondary functions are assigned to the pins of port 3 as follows:

P3.0/RxD: Receiver data input (asynchronous) or data input/output (synchronous) of the serial interface

P3.1/TxD: Transmitter data output (asynchronous) or clock output (synchronous) of the serial interface

P3.2/INT0: External interrupt 0 input/timer 0 gate control input

P3.3/INT1: External interrupt 1 input/timer 1 gate control input

P3.4/T0: Timer 0 counter input

P3.5/T1/SS: Timer 1 counter input

SPI Slave Select

P3.6/WR: External Data Memory write strobe; latches the data byte from port 0 into the external data memory

P3.7/RD: External Data Memory read strobe; Enables the external data memory. It can drive CMOS inputs without external pull-ups.

P4.0:4 I/O Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s written to them are pulled high by the internal pull-ups and can be used as inputs in this state. As inputs, Port 4 pins that are being pulled low externally will be a source of current (IIL, on the datasheet) because of the internal pull-up transistor. The output latch corresponding to a secondary function RxDC must be programmed to one for that function to operate. The secondary functions are assigned to the two pins of port 4 as follows:

P4.0/TxDC: Transmitter output of CAN controller

P4.1/RxDC: Receiver input of CAN controller.

P4.2/MISO:

Master Input Slave Output of SPI controller P4.3/SCK:

Serial Clock of SPI controller P4.4/MOSI: Master Ouput Slave Input of SPI controller

It can drive CMOS inputs without external pull-ups.

4182N–CAN–03/08

Pin Name Type Description

Reset:

RESET I/O

ALE O

PSEN O

EA I

XTAL1 I

A high level on this pin during two machine cycles while the oscillator is running resets the device. An internal pull-down resistor to VSS permits power-on reset using only an external capacitor to VCC.

ALE:

An Address Latch Enable output for latching the low byte of the address during accesses to the external memory. The ALE is activated every 1/6 oscillator periods (1/3 in X2 mode) except during an external data memory access. When instructions are executed from an internal Flash (EA = 1), ALE generation can be disabled by the software.

PSEN:

The Program Store Enable output is a control signal that enables the external program memory of the bus during external fetch operations. It is activated twice each machine cycle during fetches from the external program memory. However, when executing from of the external program memory two activations of PSEN are skipped during each access to the external Data memory. The PSEN is not activated for internal fetches.

EA:

When External Access is held at the high level, instructions are fetched from the internal Flash. When held at the low level, AT89C51CC03 fetches all instructions from the external program memory

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator circuits. To drive the device from an external clock source, XTAL1 should be driven, while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty cycle of 50% should be maintained.

AT89C51CC03

XTAL2 O

XTAL2:

Output from the inverting oscillator amplifier.

I/O Configurations

Port 1, Port 3 and Port 4

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a "read pin" signal transfers the logical level of the Port pin. Some Port data instructions activate the "read latch" signal while others activate the "read pin" signal. Latch instructi ons are referr e d to a s Re a d-Modif y -Write inst ructions . E ach I/O line may be independently programmed as input or output.

Figure 1 shows the structure of Ports 1 and 3, which have internal pull-ups. An external source can pull the pin low. Each Port pin can be configured either for general-purpose I/O or for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 1,3 or 4). To use a pin for general-purpose input, set the bit in the Px register. This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch is set, the "alternate output function" signal controls the output level (see Figure 1). The operation of Ports 1, 3 and 4 is discussed further in the "quasi-Bidirectional Port Operation" section.

4182N–CAN–03/08

AT89C51CC03

Figure 1. Port 1, Port 3 and Port 4 Structure

QP1.X

LATCH

INTERNAL

WRITE TO LATCH

READ PIN

READ LATCH

P1.x

P3.X P4.X

ALTERNATE OUTPUT FUNCTION

VCC

INTERNAL PULL-UP (1)

ALTERNATE INPUT FUNCTION

P3.x P4.x

BUS

P0.X

LATCH

INTERNAL

WRITE TO LATCH

READ PIN

READ LATCH

P0.x (1)

ADDRESS LOW/ DATA

CONTROL

VDD

BUS

(2)

Note: The internal pull-up can be disabled on P1 when analog function is selected.

Port 0 and Port 2

Ports 0 and 2 are used for general-purpose I/O or as the external address/data bus. Port 0, shown in Figure 3, differs from the other Ports in not having internal pull-ups. Figure 3 shows the structure of Port 2. An external source can pull a Port 2 pin low.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px register (x = 0 or 2). To use a pin for general-purpose input, set the bit in the Px register to turn off the output driver FET.

Figure 2. Port 0 Structure

Notes: 1. Port 0 is precluded from use as general-purpose I/O Ports when used as

address/data bus drivers.

2. Port 0 internal strong pull-ups assist the logic-one output for memory bus cycles only. Except for these bus cycles, the pull-up FET is off, Port 0 outputs are open-drain.

4182N–CAN–03/08

AT89C51CC03

P2.X

LATCH

INTERNAL

WRITE TO LATCH

READ PIN

READ LATCH

P2.x (1)

ADDRESS HIGH/

CONTROL

BUS

VDD

INTERNAL PULL-UP (2)

Figure 3. Port 2 Structure

Notes: 1. Port 2 is precluded from use as general-purpose I/O Ports when as address/data bus

drivers.

2. Port 2 internal strong pull-ups FET (P1 in FiGURE) assist the logic-one output for memory bus cycle.

Read-Modify-Write Instructions

When Port 0 and Port 2 are used for an external memory cycle, an internal control signal switches the output-driver input from the latch output to the internal address/data line.

Some instructions read the latch data rather than the pin data. The latch based instructions read the data, modify the data and then rewrite the latch. These are called "ReadModify-Write" instructions. Below is a complete list of these special instructions (see Table ). When the destination operand is a Port or a Port bit, these instructions read the latch rather than the pin:

Instruction Description Example

ANL logical AND ANL P1, A

ORL logical OR ORL P2, A

XRL logical EX-OR XRL P3, A

JBC jump if bit = 1 and clear bit JBC P1.1, LABEL

CPL complement bit CPL P3.0

INC increment INC P2

DEC decrement DEC P2

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

DJNZ decrement and jump if not zero DJNZ P3, LABEL

MOV Px.y, C move carry bit to bit y of Port x MOV P1.5, C

CLR Px.y clear bit y of Port x CLR P2.4

SET Px.y set bit y of Port x SET P3.3

These instructions read the port (all 8 bits), modify the specifically addressed bit and

4182N–CAN–03/08

AT89C51CC03

write the new byte back to the latch. These Read-Modify-Write instructions are directed

READ PIN

INPUT DATA

P1.x

OUTPUT DATA

2 Osc. PERIODS

p1(1)

VCCVCCVCC

P2.x P3.x P4.x

to the latch rather than the pin in order to avoid possible misinterpretation of voltage (and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of an external bipolar transistor can not rise above the transistor’s base-emitter junction voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather than the pins returns the correct logic-one value.

Quasi-Bidirectional Port Operation

Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as logic one and sources current in response to an external logic zero condition. Port 0 is a "true bidirectional" pin. The pins float when configured as input. Resets write logic one to all Port latches. If logical zero is subsequently written to a Port latch, it can be returned to input conditions by a logical one written to the latch.

Note: Port latch values change near the end of Read-Modify-Write instruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-ModifyWrite instruction cycle.

Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pullup (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pullups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the associated nFET is switched off. This is traditional CMOS switch convention. Current strengths are 1/10 that of pFET #3.

Figure 4. Internal Pull-Up Configurations

Note: Port 2 p1 assists the logic-one output for memory bus cycles.

4182N–CAN–03/08

AT89C51CC03

SFR Mapping

The Special Function Registers (SFRs) of the AT89C51CC03 fall into the following categories:

Mnemonic Add Name 7 6 5 4 3 2 1 0

ACC E0h Accumulator – – – – – – – –

B F0h B Register – – – – – – – –

PSW D0h Program Status Word CY AC F0 RS1 RS0 OV F1 P

SP 81h Stack Pointer – – – – – – – –

Data Pointer Low

DPL 82h

DPH 83h

Mnemonic Add Name 7 6 5 4 3 2 1 0

P0 80h Port 0 – – – – – – – –

P1 90h Port 1 – – – – – – – –

byte

LSB of DPTR

Data Pointer High byte

MSB of DPTR

– – – – – – – –

P2 A0h Port 2 – – – – – – – –

P3 B0h Port 3 – – – – – – – –

P4 C0h Port 4 (x5) – – –

Mnemonic Add Name 7 6 5 4 3 2 1 0

TH0 8Ch

TL0 8Ah

TH1 8Dh

TL1 8Bh

TH2 CDh

TL2 CCh

TCON 88h

Timer/Counter 0 High byte

Timer/Counter 0 Low byte

Timer/Counter 1 High byte

Timer/Counter 1 Low byte

Timer/Counter 2 High byte

Timer/Counter 2 Low byte

Timer/Counter 0 and 1 control

– – – – – – – –

TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0

P4.4 / MOSI

P4.3 /

SCK

P4.2 / MISO

P4.1 / RxDC

P4.0 / TxDC

TMOD 89h

4182N–CAN–03/08

Timer/Counter 0 and 1 Modes

GATE1 C/T1# M11 M01 GATE0 C/T0# M10 M00

AT89C51CC03

Mnemonic Add Name 7 6 5 4 3 2 1 0

T2CON C8h

T2MOD C9h

RCAP2H CBh

RCAP2L CAh

WDTRST A6h

WDTPRG A7h

Mnemonic Add Name 7 6 5 4 3 2 1 0

SCON 98h Serial Control FE/SM0 SM1 SM2 REN TB8 RB8 TI RI

SBUF 99h Serial Data Buffer – – – – – – – –

SADEN B9h Slave Address Mask – – – – – – – –

SADDR A9h Slave Address – – – – – – – –

Timer/Counter 2 control

Timer/Counter 2 Mode

Timer/Counter 2 Reload/Capture High byte

Timer/Counter 2 Reload/Capture Low byte

WatchDog Timer Reset

WatchDog Timer Program

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/T2# CP/RL2#

– – – – – – T2OE DCEN

– – – – – – – –

– – – – – S2 S1 S0

Mnemonic

CCON D8h PCA Timer/Counter Control CF CR – CCF4 CCF3 CCF2 CCF1 CCF0

CMOD D9h PCA Timer/Counter Mode CIDL WDTE – – – CPS1 CPS0 ECF

CL E9h PCA Timer/Counter Low byte – – – – – – – –

CH F9h PCA Timer/Counter High byte – – – – – – – –

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

Add Name 7 6 5 4 3 2 1 0

DAh

PCA Timer/Counter Mode 0

DBh

PCA Timer/Counter Mode 1

DCh

PCA Timer/Counter Mode 2

DDh

PCA Timer/Counter Mode 3

DEh

PCA Timer/Counter Mode 4

FAh

PCA Compare Capture Module 0 H

FBh

PCA Compare Capture Module 1 H

FCh

PCA Compare Capture Module 2 H

FDh

PCA Compare Capture Module 3 H

FEh

PCA Compare Capture Module 4 H

EAh

PCA Compare Capture Module 0 L

EBh

PCA Compare Capture Module 1 L

ECh

PCA Compare Capture Module 2 L

EDh

PCA Compare Capture Module 3 L

EEh

PCA Compare Capture Module 4 L

CCAP0H7

CCAP1H7

CCAP2H7

CCAP3H7

CCAP4H7

CCAP0L7

CCAP1L7

CCAP2L7

CCAP3L7

CCAP4L7

–

ECOM0

ECOM1

ECOM2

ECOM3

ECOM4

CCAP0H6

CCAP1H6

CCAP2H6

CCAP3H6

CCAP4H6

CCAP0L6

CCAP1L6

CCAP2L6

CCAP3L6

CCAP4L6

CAPP0

CAPP1

CAPP2

CAPP3

CAPP4

CCAP0H5

CCAP1H5

CCAP2H5

CCAP3H5

CCAP4H5

CCAP0L5

CCAP1L5

CCAP2L5

CCAP3L5

CCAP4L5

CAPN0

CAPN1

CAPN2

CAPN3

CAPN4

CCAP0H4

CCAP1H4

CCAP2H4

CCAP3H4

CCAP4H4

CCAP0L4

CCAP1L4

CCAP2L4

CCAP3L4

CCAP4L4

MAT0

MAT1

MAT2

MAT3

MAT4

CCAP0H3

CCAP1H3

CCAP2H3

CCAP3H3

CCAP4H3

CCAP0L3

CCAP1L3

CCAP2L3

CCAP3L3

CCAP4L3

TOG0

TOG1

TOG2

TOG3

TOG4

CCAP0H2

CCAP1H2

CCAP2H2

CCAP3H2

CCAP4H2

CCAP0L2

CCAP1L2

CCAP2L2

CCAP3L2

CCAP4L2

PWM0

PWM1

PWM2

PWM3

PWM4

CCAP0H1

CCAP1H1

CCAP2H1

CCAP3H1

CCAP4H1

CCAP0L1

CCAP1L1

CCAP2L1

CCAP3L1

CCAP4L1

ECCF0

ECCF1

ECCF2

ECCF3

ECCF4

CCAP0H0

CCAP1H0

CCAP2H0

CCAP3H0

CCAP4H0

CCAP0L0

CCAP1L0

CCAP2L0

CCAP3L0

CCAP4L0

4182N–CAN–03/08

AT89C51CC03

Mnemonic Add Name 7 6 5 4 3 2 1 0

IEN0 A8h

IEN1 E8h

IPL0 B8h

IPH0 B7h

IPL1 F8h

IPH1 F7h

Mnemonic Add Name 7 6 5 4 3 2 1 0

ADCON F3h ADC Control – PSIDLE ADEN ADEOC ADSST SCH2 SCH1 SCH0

ADCF F6h ADC Configuration CH7 CH6 CH5 CH4 CH3 CH2 CH1 CH0

ADCLK F2h ADC Clock – – – PRS4 PRS3 PRS2 PRS1 PRS0

ADDH F5h ADC Data High byte ADAT9 ADAT8 ADAT7 ADAT6 ADAT5 ADAT4 ADAT3 ADAT2

ADDL F4h ADC Data Low byte – – – – – – ADAT1 ADAT0

Interrupt Enable Control 0

Interrupt Enable Control 1

Interrupt Priority Control Low 0

Interrupt Priority Control High 0

Interrupt Priority Control Low 1

Interrupt Priority Control High1

EA EC ET2 ES ET1 EX1 ET0 EX0

– – – – ESPI ETIM EADC ECAN

– PPC PT2 PS PT1 PX1 PT0 PX0

– PPCH PT2H PSH PT1H PX1H PT0H PX0H

– – – – SPIL POVRL PADCL PCANL

– – – – SPIH POVRH PADCH PCANH

Mnemonic Add Name 7 6 5 4 3 2 1 0

CANGCON ABh

CANGSTA AAh

CANGIT 9Bh

CANBT1 B4h CAN Bit Timing 1 – BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 –

CANBT2 B5h CAN Bit Timing 2 – SJW1 SJW0 – PRS2 PRS1 PRS0 –

CANBT3 B6h CAN Bit Timing 3 – PHS22 PHS21 PHS20 PHS12 PHS11 PHS10 SMP

CANEN1 CEh

CANEN2 CFh

CANGIE C1h

CANIE1 C2h

CAN General Control

CAN General Status

CAN General Interrupt

CAN Enable Channel byte 1

CAN Enable Channel byte 2

CAN General Interrupt Enable

CAN Interrupt Enable Channel byte 1

ABRQ OVRQ TTC SYNCTTC

– OVFG – TBSY RBSY ENFG BOFF ERRP

CANIT – OVRTIM OVRBUF SERG CERG FERG AERG

– ENCH14 ENCH13 ENCH12 ENCH11 ENCH10 ENCH9 ENCH8

ENCH7 ENCH6 ENCH5 ENCH4 ENCH3 ENCH2 ENCH1 ENCH0

– – ENRX ENTX ENERCH ENBUF ENERG –

– IECH14 IECH13 IECH12 IECH11 IECH10 IECH9 IECH8

AUT– BAUD

TEST ENA GRES

4182N–CAN–03/08

AT89C51CC03

Mnemonic Add Name 7 6 5 4 3 2 1 0

CAN Interrupt

CANIE2 C3h

Enable Channel byte 2

IECH7 IECH6 IECH5 IECH4 IECH3 IECH2 IECH1 IECH0

CANSIT1 BAh

CANSIT2 BBh

CANTCON A1h

CANTIMH ADh CAN Timer high

CANTIML ACh CAN Timer low CANTIM 7 CANTIM 6 CANTIM 5 CANTIM 4 CANTIM 3 CANTIM 2 CANTIM 1 CANTIM 0

CANSTMP H

CANSTMP L

CANTTCH A5h

CANTTCL A4h

CANTEC 9Ch

CAN Status Interrupt Channel byte1

CAN Status Interrupt Channel byte2

CAN Timer Control

CAN Timer Stamp

AFh

high

CAN Timer Stamp

AEh

low

CAN Timer TTC high

CAN Timer TTC low

CAN Transmit Error Counter

– SIT14 SIT13 SIT12 SIT11 SIT10 SIT9 SIT8

SIT7 SIT6 SIT5 SIT4 SIT3 SIT2 SIT1 SIT0

TPRESC 7 TPRESC 6 TPRESC 5 TPRESC 4 TPRESC 3 TPRESC 2 TPRESC 1 TPRESC 0

CANTIM 15CANTIM 14CANTIM 13CANTIM 12CANTIM 11CANTIM

TIMSTMP 15TIMSTMP 14TIMSTMP 13TIMSTMP 12TIMSTMP 11TIMSTMP 10TIMSTMP 9TIMSTMP

TIMSTMP7

TIMTTC 15 TIMTTC 14 TIMTTC 13 TIMTTC 12 TIMTTC 11 TIMTTC 10

TIMTTC7TIMTTC

TEC7 TEC6 TEC5 TEC4 TEC3 TEC2 TEC1 TEC0

TIMSTMP 6TIMSTMP 5TIMSTMP 4TIMSTMP 3TIMSTMP 2TIMSTMP 1TIMSTMP

TIMTTC5TIMTTC

TIMTTC

CANTIM 9 CANTIM 8

TIMTTC

CANREC 9Dh

CANPAGE B1h CAN Page CHNB3 CHNB2 CHNB1 CHNB0 AINC INDX2 INDX1 INDX0

CANSTCH B2h

CANCONC H

CANMSG A3h

CANIDT1 BCh

CANIDT2 BDh

CANIDT3 BEh

CAN Receive Error Counter

CAN Status Channel

CAN Control

B3h

Channel

CAN Message Data

CAN Identifier Tag byte 1(Part A)

CAN Identifier Tag byte 1(PartB)

CAN Identifier Tag byte 2 (PartA)

CAN Identifier Tag byte 2 (PartB)

CAN Identifier Tag byte 3(PartA)

CAN Identifier Tag byte 3(PartB)

REC7 REC6 REC5 REC4 REC3 REC2 REC1 REC0

DLCW TXOK RXOK BERR SERR CERR FERR AERR

CONCH1 CONCH0 RPLV IDE DLC3 DLC2 DLC1 DLC0

MSG7 MSG6 MSG5 MSG4 MSG3 MSG2 MSG1 MSG0

IDT10 IDT9 IDT8 IDT7 IDT6 IDT5 IDT4 IDT3

IDT28 IDT27 IDT26 IDT25 IDT24 IDT23 IDT22 IDT21

IDT2

IDT20

–

IDT12

IDT1

IDT19

–

IDT11

IDT0

IDT18

–

IDT10

–

IDT17

–

IDT9

–

IDT16

–

IDT8

–

IDT15

–

IDT7

–

IDT14

–

IDT6

–

IDT13

–

IDT5

4182N–CAN–03/08

AT89C51CC03

Mnemonic Add Name 7 6 5 4 3 2 1 0

CANIDT4 BFh

CANIDM1 C4h

CANIDM2 C5h

CANIDM3 C6h

CANIDM4 C7h

CAN Identifier Tag byte 4(PartA)

CAN Identifier Tag byte 4(PartB)

CAN Identifier Mask byte 1(PartA)

CAN Identifier Mask byte 1(PartB)

CAN Identifier Mask byte 2(PartA)

CAN Identifier Mask byte 2(PartB)

CAN Identifier Mask byte 3(PartA)

CAN Identifier Mask byte 3(PartB)

CAN Identifier Mask byte 4(PartA)

CAN Identifier Mask byte 4(PartB)

–

IDT4

IDMSK10

IDMSK28

IDMSK2

IDMSK20

–

IDMSK12–IDMSK11–IDMSK10–IDMSK9

–

IDMSK4–IDMSK3–IDMSK2–IDMSK1

–

IDT3

IDMSK9

IDMSK27

IDMSK1

IDMSK19

–

IDT2

IDMSK8

IDMSK26

IDMSK0

IDMSK18–IDMSK17–IDMSK16–IDMSK15–IDMSK14–IDMSK13

–

IDT1

IDMSK7

IDMSK25

–

RTRTAG

IDT0

IDMSK6

IDMSK24

–

IDMSK8–IDMSK7–IDMSK6

–

IDMSK0

IDMSK5

IDMSK23

RTRMSK – IDEMSK

–

RB1TAG

IDMSK4

IDMSK22

RB0TAF

IDMSK3

IDMSK21

–

IDMSK5

Mnemonic Add Name 7 6 5 4 3 2 1 0

SPCON D4h SPI Control SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPSCR D5h

SPDAT D6h SPI Data - - - - - - - -

Mnemonic Add Name 7 6 5 4 3 2 1 0

PCON 87h Power Control SMOD1 SMOD0 – POF GF1 GF0 PD IDL

AUXR 8Eh Auxiliary Register 0 DPU VPFDP M0 XRS2 XRS1 XRS0 EXTRAM A0

AUXR1 A2h Auxiliary Register 1 – – ENBOOT – GF3 0 – DPS

CKCON0 8Fh Clock Control 0 CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

CKCON1 9Fh Clock Control 1 - - - - - - - SPIX2

FCON D1h Flash Control FPL3 FPL2 FPL1 FPL0 FPS FMOD1 FMOD0 FBUSY

EECON D2h EEPROM Contol EEPL3 EEPL2 EEPL1 EEPL0 – – EEE EEBUSY

FSTA D3 Flash Status - - - - - - SEQERR FLOAD

4182N–CAN–03/08

SPI Status and Control

SPIF - OVR MODF SPTE UARTM SPTEIE MOFIE

AT89C51CC03

Table 1. SFR Mapping

(2)

0/8

1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

IPL1

xxxx x000

0000 0000

IEN1

xxxx x000

ACC

0000 0000

CCON

0000 0000

PSW

0000 0000

T2CON

0000 0000

xxx1 1111

IPL0

x000 0000

1111 1111

IEN0

0000 0000

CMOD

00xx x000

FCON

0000 0000

T2MOD

xxxx xx00

CANGIE

xx00 000x

SADEN

0000 0000

CANPAGE 0000 0000

SADDR

0000 0000

CCAP0H

0000 0000

ADCLK

xxx0 0000

CCAP0L

0000 0000

CCAPM0

x000 0000

EECON

xxxx xx00

RCAP2L

0000 0000

CANIE1

x000 0000

CANSIT1

0000 0000

CANSTCH

xxxx xxxx

CANGSTA x0x0 0000

CCAP1H

0000 0000

ADCON

x000 0000

CCAP1L

0000 0000

CCAPM1

x000 0000

FSTA

xxxx xx00

RCAP2H

0000 0000

CANIE2

0000 0000

CANSIT2

0000 0000

CANCONCH

xxxx xxxx

CANGCON

0000 0x00

CCAP2H

0000 0000

ADDL

0000 0000

CCAP2L

0000 0000

CCAPM2

x000 0000

SPCON

0001 0100

TL2

0000 0000

CANIDM1

xxxx xxxx

CANIDT1 xxxx xxxx

CANBT1

xxxx xxxx

CANTIML

0000 0000

CCAP3H

0000 0000

ADDH

0000 0000

CCAP3L

0000 0000

CCAPM3

x000 0000

SPSCR

0000 0000

TH2

0000 0000

CANIDM2

xxxx xxxx

CANIDT2 xxxx xxxx

CANBT2

xxxx xxxx

CANTIMH

0000 0000

CCAP4H

0000 0000

ADCF

0000 0000

CCAP4L

0000 0000

CCAPM4

x000 0000

SPDAT

xxxx xxxx

CANEN1

x000 0000

CANIDM3

xxxx xxxx

CANIDT3 xxxx xxxx

CANBT3

xxxx xxxx

CANSTMPL

0000 0000

IPH1

xxxx x000

CANEN2

0000 0000

CANIDM4

xxxx xxxx

CANIDT4 xxxx xxxx

IPH0

x000 0000

CANSTMPH

0000 0000

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A0h

98h

90h

88h

80h

1111 1111

SCON

0000 0000

1111 1111

TCON

0000 0000

1111 1111

(2)

0/8

CANTCON 0000 0000

SBUF

0000 0000

TMOD

0000 0000

0000 0111

1/9 2/A 3/B 4/C 5/D 6/E 7/F

AUXR1

xxxx 00x0

TL0

0000 0000

DPL

0000 0000

Reserved

Note: 1. Do not read or write Reserved Registers

2. These registers are bit–addressable. Sixteen addresses in the SFR space are both byte–addressable and bit–addressable. The bit–addressable SFR’s are those whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

CANMSG xxxx xxxx

CANGIT

0x00 0000

TL1

0000 0000

DPH

0000 0000

CANTTCL 0000 0000

CANTEC

0000 0000

TH0

0000 0000

CANTTCH 0000 0000

CANREC

0000 0000

TH1

0000 0000

WDTRST 1111 1111

AUXR

x001 0100

WDTPRG xxxx x000

CKCON1

xxxx xxx0

CKCON0

0000 0000

PCON

00x1 0000

A7h

9Fh

97h

8Fh

87h

4182N–CAN–03/08

AT89C51CC03

Clock

Description

The AT89C51CC03 core needs only 6 clock periods per machine cycle. This feature, called”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU power.

• Saves power consumption while keeping the same CPU power (oscillator power saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section "In-System Programming".

The X2 bit in the CKCON register (see Table 2) allows switching from 12 clock cycles per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD mode).

Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure

5.).

The Timers 0, 1 and 2, Uart, PCA, WatchDog or CAN switch in X2 mode only if the corresponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1 input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 5. shows the clock generation block diagram. The X2 bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2 to the STD mode. Figure 6 shows the mode switching waveforms.

4182N–CAN–03/08

AT89C51CC03

Figure 5. Clock CPU Generation Diagram

XTAL1

XTAL2

PCON.1

CPU Core

PERIPH

CLOCK

Clock

Peripheral

CPU

CLOCK

CPU Core Clock Symbol

CKCON.0

X2B

Hardware byte

CANX2

CKCON0.7

WDX2

CKCON0.6

PCAX2

CKCON0.5

SIX2

CKCON0.4

T2X2

CKCON0.3

T1X2

CKCON0.2

T0X2

CKCON0.1

IDL

PCON.0

CKCON.0

FCan Clock

FWd Clock

FPca Clock

FUart Clock

FT2 Clock

FT1 Clock

FT0 Clock

and ADC

On RESET

FSPIClock

SPIX2

CKCON1.0

Clock Symbol

4182N–CAN–03/08

AT89C51CC03

XTAL1/2

XTAL1

CPU clock

X2 bit

X2 ModeSTD Mode STD Mode

Figure 6. Mode Switching Waveforms

Note: In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the

clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have a 9600 baud rate.

4182N–CAN–03/08

AT89C51CC03

Registers

Table 2. CKCON0 Register

CKCON0 (S:8Fh) Clock Control Register

7 6 5 4 3 2 1 0

CANX2 WDX2 PCAX2 SIX2 T2X2 T1X2 T0X2 X2

Bit

Number

7 CANX2

6 WDX2

5 PCAX2

4 SIX2

3 T2X2

2 T1X2

1 T0X2

Bit

Mnemonic Description

CAN clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

WatchDog clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2)

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer1 clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

Timer0 clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

(1)

CPU clock

0 X2

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals. Set to select 6 clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2"bits.

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

4182N–CAN–03/08

AT89C51CC03

Table 3. CKCON1 Register

CKCON1 (S:9Fh) Clock Control Register 1

7 6 5 4 3 2 1 0

SPIX2

Bit

Number

7-1 -

0 SPIX2

Bit

Mnemonic Description

Reserved

The value read from these bits is indeterminate. Do not set these bits.

SPI clock

Clear to select 6 clock periods per peripheral clock cycle. Set to select 12 clock periods per peripheral clock cycle.

(1)

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = 0000 0000b

4182N–CAN–03/08

AT89C51CC03

Data Memory

Upper

128 Bytes

Internal RAM

Lower

128 Bytes

Internal RAM

Special

Function

Registers

80h

00h

FFh

direct addressing

addressing

7Fh

direct or indirect

indirect addressing

256 up to 2048 Bytes

00h

64K Bytes

External XRAM

0000h

FFFFh

Internal ERAM

EXTRAM = 0

EXTRAM = 1

FFh or 7FFh

Internal

External

The AT89C51CC03 provides data memory access in two different spaces:

1. The internal space mapped in three separate segments:

• the lower 128 Bytes RAM segment.

• the upper 128 Bytes RAM segment.

• the expanded 2048 Bytes RAM segment (ERAM).

2. The external space.

A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to

FFh

) accessible by direct addressing mode.

Figure 8 shows the internal and external data memory spaces organization.

Figure 7. Internal Memory - RAM

Figure 8. Internal and External Data Memory Organization ERAM-XRAM

4182N–CAN–03/08

AT89C51CC03

Bit-Addressable Space

4 Banks of 8 Registers R0-R7

30h

7Fh

(Bit Addresses 0-7Fh)

20h

2Fh

18h

1Fh

10h

17h

08h

0Fh

00h

07h

Internal Space

Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Figure 8) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 Bytes are grouped into 4 banks of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 6) select which bank is in use according to Table 4. This allows more efficient use of code space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines.

Table 4. Register Bank Selection

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

0 1 Register bank 0 from 08h to 0Fh

1 0 Register bank 0 from 10h to 17h

1 1 Register bank 0 from 18h to 1Fh

The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.

Figure 9. Lower 128 Bytes Internal RAM Organization

Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

Expanded RAM The on-chip 2048 Bytes of expanded RAM (ERAM) are accessible from address 0000h

to 07FFh using indirect addressing mode through MOVX instructions. In this address range, the bit EXTRAM in AUXR register is used to select the ERAM (default) or the XRAM. As shown in Figure 8 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is selected.

The size of ERAM can be configured by XRS2-0 bit in AUXR register (default size is 2048 Bytes).

4182N–CAN–03/08

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.

AT89C51CC03

External Space

RAM

PERIPHERAL

AT89C51CC03

AD7:0

A15:8

A7:0

A15:8

D7:0

A7:0

ALE

OERD#

WR#

Latch

Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD#, WR#, and ALE).

Figure 10 shows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 5 describes the external memory interface signals.

Figure 10. External Data Memory Interface Structure

Table 5. External Data Memory Interface Signals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

RD# O

WR# O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

Read

Read signal output to external data memory.

Write

Write signal output to external memory.

Alternative

Function

P2.7:0

P0.7:0

P3.7

P3.6

External Bus Cycles This section describes the bus cycles the AT89C51CC03 executes to read (see

Figure 11), and write data (see Figure 12) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode.

Slow peripherals can be accessed by stretching the read and write cycles. This is done using the M0 bit in AUXR register. Setting this bit changes the width of the RD# and WR# signals from 3 to 15 CPU clock periods.

For simplicity, the accompanying figures depict the bus cycle waveforms in idealized form and do not provide precise timing information. For bus cycle timing parameters refer to the Section “AC Characteristics” of the AT89C51CC03 datasheet.

4182N–CAN–03/08

AT89C51CC03

ALE

RD#1

DPL or Ri D7:0

DPH or P22

CPU Clock

ALE

WR#1

DPL or Ri D7:0

CPU Clock

DPH or P22

Figure 11. External Data Read Waveforms

Notes: 1. RD# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

Figure 12. External Data Write Waveforms

4182N–CAN–03/08

Notes: 1. WR# signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

AT89C51CC03

Dual Data Pointer

DPH0

DPH1

DPL0

DPS

AUXR1.0

DPH

DPL

DPL1

DPTR

DPTR0

DPTR1

Description The AT89C51CC03 implements a second data pointer for speeding up code execution

and reducing code size in case of intensive usage of external memory accesses. DPTR 0 and DPTR 1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Figure 8) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 13).

Figure 13. Dual Data Pointer Implementation

Application Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by using one data pointer as a “source” pointer and the other one as a “destination” pointer. Hereafter is an example of block move implementation using the two pointers and coded in assembler. The latest C compiler takes also advantage of this feature by providing enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 machine cycle) way to manipulate the DPS bit in the AUXR1 register. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE incDPTR; increment SOURCE address incAUXR1; switch data pointers movx@DPTR,A; write the byte to DEST incDPTR; increment DEST address jnzmv_loop; check for NULL terminator

end_move:

4182N–CAN–03/08

AT89C51CC03

Registers

Table 6. PSW Register

PSW (S:8Eh) Program Status Word Register

7 6 5 4 3 2 1 0

CY AC F0 RS1 RS0 OV F1 P

Bit

Number

7 CY

6 AC

5 F0

4-3 RS1:0

2 OV

1 F1

0 P

Bit

Mnemonic Description

Carry Flag

Carry out from bit 1 of ALU operands.

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

User Definable Flag 0.

Refer to Table 4 for bits description.

Overflow Flag

Overflow set by arithmetic operations.

User Definable Flag 1

Parity Bit

Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

Reset Value = 0000 0000b

Table 7. AUXR Register

AUXR (S:8Eh) Auxiliary Register

7 6 5 4 3 2 1 0

- - M0 XRS2 XRS1 XRS0 EXTRAM A0

Bit

Number

7-6 -

5 M0

Bit

Mnemonic Description

Reserved

The value read from these bits are indeterminate. Do not set this bit.

Stretch MOVX control:

the RD/ and the WR/ pulse length is increased according to the value of M0.

M0 Pulse length in clock period

0 6 1 30

4182N–CAN–03/08

AT89C51CC03

Bit

Number

4-2 XRS1-0

1 EXTRAM

0 A0

Bit

Mnemonic Description

ERAM size:

Accessible size of the ERAM

XRS 2:0 ERAM size

000 256 Bytes 001 512 Bytes 010 768 Bytes 011 1024 Bytes

100 1792 Bytes

101 2048 Bytes (default configuration after reset)

110 Reserved

111 Reserved

Internal/External RAM (00h - FFh)

access using MOVX @ Ri/@ DPTR 0 - Internal ERAM access using MOVX @ Ri/@ DPTR. 1 - External data memory access.

Disable/Enable ALE)

0 - ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used) 1 - ALE is active only during a MOVX or MOVC instruction.

Reset Value = X001 0100b Not bit addressable

Table 8. AUXR1 Register

AUXR1 (S:A2h) Auxiliary Control Register 1

7 6 5 4 3 2 1 0

- - ENBOOT - GF3 0 - DPS

Bit

Number

7-6 -

5 ENBOOT

4 -

3 GF3

2 0

1 -

0 DPS

Bit

Mnemonic Description

Reserved

The value read from these bits is indeterminate. Do not set these bits.

Enable Boot Flash

Set this bit for map the boot Flash between F800h -FFFFh Clear this bit for disable boot Flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

General-purpose Flag 3

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.

Reserved for Data Pointer Extension.

Data Pointer Select Bit

Set to select second dual data pointer: DPTR1. Clear to select first dual data pointer: DPTR0.

Reset Value = XXXX 00X0b

4182N–CAN–03/08

AT89C51CC03

VCC

Power On Reset Power Fail Detect Voltage Regulator

XTAL1

(1)

CPU core

Memories

Peripherals

Regulated Supply

RST pin

Hardware Watchdog

PCA Watchdog

Internal Reset

Power Monitor

The POR/PFD function monitors the internal power-supply of the CPU core memories and the peripherals, and if needed, suspends their activity when the internal power supply falls below a safety threshold. This is achieved by applying an internal reset to them.

By ge n e rating t h e R e s e t the Power Monitor insures a c o r r e ct st a r t up when AT89C51CC03 is powered up.

Description

In order to startup and maintain the microcontroller in correct operating mode, VCC has to be stabilized in the VCC operating range and the oscillator has to be stabilized with a nominal amplitude compatible with logic level VIH/VIL.

These parameters are controlled during the three phases: power-up, normal operation and power going down. See Figure 14.

Figure 14. Power Monitor Block Diagram

Note: 1. Once XTAL1 high and low levels reach above and below VIH/VIL a 1024 clock period

delay will extend the reset coming from the Power Fail Detect. If the power falls below the Power Fail Detect thresthold level, the reset will be applied immediately.

The Voltage regulator generates a regulated internal supply for the CPU core the memories and the peripherals. Spikes on the external Vcc are smoothed by the voltage regulator.

The Power fail detect monitor the supply generated by the voltage regulator and generate a reset if this supply falls below a safety threshold as illustrated in the Figure 15.

4182N–CAN–03/08

AT89C51CC03

Figure 15. Power Fail Detect

Vcc

Reset

Vcc

When the power is applied, the Power Monitor immediately asserts a reset. Once the internal supply after the voltage regulator reach a safety level, the power monitor then looks at the XTAL clock input. The internal reset will remain asserted until the Xtal1 levels are above and below VIH and VIL. Further more. An internal counter will count 1024 clock periods before the reset is de-asserted.

If the internal power supply falls below a safety level, a reset is immediately asserted.

4182N–CAN–03/08

+ 166 hidden pages