ATMEL AT89C4051 User Manual
BDTIC www.bdtic.com/ATMEL
Features
• Compatible with MCS
• 4K Bytes of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
• 2.7V to 6V Operating Range
• Fully Static Operation: 0 Hz to 24 MHz
• Two-level Program Memory Lock
• 128 x 8-bit Internal RAM
• 15 Programmable I/O Lines
• Two 16-bit Timer/Counters
• Six Interrupt Sources
• Programmable Serial UART Channel
• Direct LED Drive Outputs
• On-chip Analog Comparator
• Low-power Idle and Power-down Modes
• Brown-out Detection
• Power-On Reset (POR)
• Green (Pb/Halide-free/RoHS Compliant) Packaging
®
51 Products
8-bit
Microcontroller
with 4K Bytes
Flash
AT89C4051
1. Description
The AT89C4051 is a low-voltage, high-performance CMOS 8-bit microcontroller with
4K bytes of Flash programmable and erasable read-only memory. The device is manufactured using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C4051 is a powerful
microcontroller which provides a highly-flexible and cost-effective solution to many
embedded control applications.
The AT89C4051 provides the following standard features: 4K bytes of Flash,
128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five-vector, two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip
oscillator and clock circuitry. In addition, the AT89C4051 is designed with static logic
for operation down to zero frequency and supports two software-selectable power
saving modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters,
serial port and interrupt system to continue functioning. The power-down mode saves
the RAM contents but freezes the oscillator disabling all other chip functions until the
next hardware reset.
1001E–MICRO–6/05
2. Pin Configuration
2.1 PDIP/SOIC
3. Block Diagram
RST/VPP
(RXD) P3.0
(TXD) P3.1
XTAL2
XTAL1
(INT0) P3.2
(INT1) P3.3
(TO) P3.4
(T1) P3.5
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
P1.7
P1.6
P1.5
P1.4
P1.3
P1.2
P1.1 (AIN1)
P1.0 (AIN0)
P3.7
2
AT89C4051
1001E–MICRO–6/05
4. Pin Description
4.1 VCC
Supply voltage.
4.2 GND
Ground.
4.3 Port 1
Port 1 is an 8-bit bi-directional I/O port. Port pins P1.2 to P1.7 provide internal pullups. P1.0 and
P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly. When 1s are written to Port 1 pins,
they can be used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled
low, they will source current (I
Port 1 also receives code data during Flash programming and verification.
4.4 Port 3
Port 3 pins P3.0 to P3.5, P3.7 are seven bi-directional I/O pins with internal pullups. P3.6 is
hard-wired as an input to the output of the on-chip comparator and is not accessible as a general-purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3
pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins
that are externally being pulled low will source current (I
Port 3 also serves the functions of various special features of the AT89C4051 as listed below:
) because of the internal pullups.
IL
) because of the pullups.
IL
AT89C4051
4.5 RST
4.6 XTAL1
Port Pin Alternate Functions
P3.0 RXD (serial input port)
P3.1 TXD (serial output port)
P3.2 INT0
P3.3 INT1 (external interrupt 1)
P3.4 T0 (timer 0 external input)
P3.5 T1 (timer 1 external input)
Port 3 also receives some control signals for Flash programming and verification.
Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for
two machine cycles while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
Input to the inverting oscillator amplifier and input to the internal clock operating circuit.
(external interrupt 0)
1001E–MICRO–6/05
3
4.7 XTAL2
Output from the inverting oscillator amplifier.
5. Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be
configured for use as an on-chip oscillator, as shown in Figure 5-1. Either a quartz crystal or
ceramic resonator may be used. To drive the device from an external clock source, XTAL2
should be left unconnected while XTAL1 is driven as shown in Figure 5-2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking
circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Figure 5-1. Oscillator Connections
Note: C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Figure 5-2. External Clock Drive Configuration
4
AT89C4051
1001E–MICRO–6/05
AT89C4051
6. Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in
the Table 6-1.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and
write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future
products to invoke new features. In that case, the reset or inactive values of the new bits will
always be 0.
Table 6-1. AT89C4051 SFR Map and Reset Values
0F8H 0FFH
0F0H
0E8H 0EFH
0E0H
0D8H 0DFH
0D0H
0C8H
0C0H 0C7H
0B8H
0B0H
0A8H
0A0H
B
00000000
ACC
00000000
PSW
00000000
IP
XXX00000
P3
11111111
IE
0XX00000
0F7H
0E7H
0D7H
0CFH
0BFH
0B7H
0AFH
0A7H
98H
90H
88H
80H
1001E–MICRO–6/05
SCON
00000000
11111111
TCON
00000000
P1
SBUF
XXXXXXXX
TMOD
00000000
SP
00000111
TL0
00000000
DPL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
TH1
00000000
PCON
0XXX0000
9FH
97H
8FH
87H
5
7. Restrictions on Certain Instructions
The AT89C4051 is an economical and cost-effective member of Atmel’s growing family of microcontrollers. It contains 4K bytes of Flash program memory. It is fully compatible with the MCS-51
architecture, and can be programmed using the MCS-51 instruction set. However, there are a
few considerations one must keep in mind when utilizing certain instructions to program this
device.
All the instructions related to jumping or branching should be restricted such that the destination
address falls within the physical program memory space of the device, which is 4K for the
AT89C4051. This should be the responsibility of the software programmer. For example, LJMP
0FE0H would be a valid instruction for the AT89C4051 (with 4K of memory), whereas LJMP
1000H would not.
7.1 Branching Instructions
LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR. These unconditional branching instruc-
tions will execute correctly as long as the programmer keeps in mind that the destination
branching address must fall within the physical boundaries of the program memory size (locations 00H to FFFH for the 89C4051). Violating the physical space limits may cause unknown
program behavior.
CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ. With these conditional branching
instructions the same rule above applies. Again, violating the memory boundaries may cause
erratic execution.
For applications involving interrupts, the normal interrupt service routine address locations of the
80C51 family architecture have been preserved.
7.2 MOVX-related Instructions, Data Memory
The AT89C4051 contains 128 bytes of internal data memory. Thus, in the AT89C4051 the stack
depth is limited to 128 bytes, the amount of available RAM. External DATA memory access is
not supported in this device, nor is external Program memory execution. Therefore, no MOVX
[...] instructions should be included in the program.
A typical 80C51 assembler will still assemble instructions, even if they are written in violation of
the restrictions mentioned above. It is the responsibility of the controller user to know the physical features and limitations of the device being used and adjust the instructions used
correspondingly.
8. Program Memory Lock Bits
On the chip are two lock bits which can be left unprogrammed (U) or can be programmed (P) to
obtain the additional features listed in the Table 8-1.
Table 8-1. Lock Bit Protection Modes
Program Lock Bits
1 U U No program lock features
(1)
Protection TypeLB1 LB2
2 P U Further programming of the Flash is disabled
3 P P Same as mode 2, also verify is disabled
Note: 1. The Lock Bits can only be erased with the Chip Erase operation.
6
AT89C4051
1001E–MICRO–6/05
Loading...