ATMEL AT89C1051-24PI, AT89C1051-24PC, AT89C1051-12SI, AT89C1051-12SC, AT89C1051-12SA Datasheet
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Features
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Compatible with MCS-51™ Products
•
1K Byte of Reprogrammable Flash Memory
– Endurance: 1,000 Write/Erase Cycles
•
2.7V to 6V Operating Range
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Fully Static Operation: 0 Hz to 24 MHz
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T wo-Level Pro gr am Me mory Loc k
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64 bytes SRAM
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15 Programmable I/O Lines
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One 16-Bit Timer/Counter
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Three Interrupt Sources
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Direct LED Drive Outputs
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On-Chip Analog Comparator
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Low Power Idle and Power Down Modes
8-Bit
Microcontroller
Description
The AT89C1051 is a low-vo ltage, high-pe rformanc e CMOS 8 -bit micr ocompu ter with
1K byte of Flash programmable and erasable read only memory (PERO M). The
device is manufactured using Atmel’s high density nonvolatile memory technology
and is compatibl e with the in dustry standard MCS-51™ instru ctio n set. By comb ining
a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C1051 is a powerful microcomputer which provides a highly flexible and c ost effective solutio n to
many embedded control applications.
The AT89C1051 provides the following standard features: 1K Byte of Flash, 64 bytes
of RAM, 15 I/O lines, one 16-bi t ti mer /c oun ter, a three vector two-level inte r ru pt arc hi tecture, a precision analog comparator, on-chip oscillator and clock circuitry. In addition, the AT89C1051 is designed with static logic for operation down to zero frequency
and supports two software selectable power saving modes. The Idle Mode stops the
CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the
oscillator disabling all other chip functions until the next hardware reset.
Pin Configuration
PDIP/SOIC
with 1K Byte
Flash
AT89C1051
0366D-A–12/97
4-3
Block Diagram
V
CC
GND
RAM ADDR.
REGISTER
RAM
FLASH
RST
B
REGISTER
TIMING
AND
CONTROL
OSC
ACC
INSTRUCTION
REGISTER
ANALOG
COMPARATOR
+
-
TMP2 TMP1
ALU
PSW
PORT 1
LATCH
PORT 1 DRIVERS
STACK
POINTER
INTERRUPT,
AND TIMER BLOCKS
PORT 3
LATCH
PORT 3 DRIVERS
PROGRAM
ADDRESS
REGISTER
BUFFER
PC
INCREMENTER
PROGRAM
COUNTER
DPTR
4-4
AT89C1051
P1.0 - P1.7
P3.0 - P3.5
P3.7
AT89C1051
Pin Description
V
CC
Supply voltage.
GND
Ground.
Port 1
Port 1 is an 8-bit bidi rectional I/O por t. Port pins P1 .2 to
P1.7 provide internal pullups. P1.0 and P1.1 require external pullups. P1.0 and P1.1 also serve as the positive input
(AIN0) and the negative input (AIN1), respectively, of the
on-chip precision analog comparator. The Port 1 output
buffers can sink 20 mA and can drive LED displays directly.
When 1s are written to Port 1 pins, they can be used as
inputs. When pins P 1.2 to P 1.7 are used a s inp uts an d are
externally pulled low, they will source current (I
of the internal pullups.
Port 1 also receives code data during Fla sh programming
and verification.
Port 3
Port 3 pins P3.0 to P3 .5, P3.7 are sev en bidirect ional I/O
pins with internal pull ups. P3.6 is ha rd-wire d as an input to
the output of the on-chip comparator and is not accessible
as a general purpose I/O pin. The Port 3 output buffers can
sink 20 mA. When 1s are writt en to Port 3 pins they are
pulled high by the in ternal pullups an d can be used as
inputs. As inputs, Port 3 pins that are externally being
pulled low will source current (I
Port 3 also se rves the fun ctions of v arious spe cial f eatu res
of the AT89C1051 as listed below:
Port Pin Alternate Functions
P3.2
P3.3
P3.4
(external interrupt 0)
INT0
INT1 (external interrupt 1)
T0 (timer 0 external input)
) because of the pullups.
IL
) because
IL
Oscillator Characteristics
XTAL1 and XTAL2 are the input and output, respectiv ely,
of an inverting amplifier which can be con fig ured for us e as
an on-chip oscillator, as shown in Figure 1. Either a quartz
crystal or ceramic resonator may be used. To drive the
device from an external clock source, XTAL2 should be left
unconnected while XTAL1 is driven as shown in Figure 2.
There are no requirements on the duty cycle of the external
clock signal, since the input to the internal clocking circuitry
is through a di vide- by-two fli p-flop , but mini mum and maxi mum voltage high and low time specificat ions must be
observed.
Figure 1.
Note: C1, C2 = 30 pF ± 10 pF for Cry s tals
Figure 2.
Oscillator Connections
= 40 pF ± 10 pF for Ceramic Resonators
External Clock Drive Configuration
Port 3 also receives some control signals for Flash programming and verification.
RST
Reset input. All I/O pins are reset to 1s as soon as RST
goes high. Holding the RST pin high for two machine cycles
while the oscillator is running resets the device.
Each machine cycle takes 12 oscillator or clock cycles.
XTAL1
Input to the inverting os cillator ampli fier and input to the
internal clock operating circuit.
XTAL2
Output from the inverting oscillator amplifier.
4-5
Special Function Registers
A map of the on-chip memory area called the Special Function Register (SFR) space is shown in the table below.
Note that not all of the addresses are occupied, and unoccupied addresses may not be implemented on the chip.
Read accesses to these addresses will in general return
random data, and write accesses will have an indeterminate effect.
User software should not write 1s to these unlisted locations, since they may be used in future products to invoke
new features. In th at case, th e reset or i nactive va lues of
the new bits will always be 0.
Restrictions on Certain Instructions
The AT89C1051 is a n e conomical and cost-eff ectiv e mem ber of Atmel’s growing family of microcontrollers. It contains 1K byte of flash program memory. It is fully compatible with the MCS-51 arch itectu re, and can be p rogramm ed
using the MCS-51 instruction set. However, there ar e a
few considerations one must keep in mind when utilizing
certain instructions to program this device.
All the instructions related to jumping or branching should
be restricted such that the destination ad dress falls within
the physical program memory space of the device, which is
1K for the AT89C1051. This should be the responsibility of
the software pr ogrammer. For example, LJM P 3FEH
would be a valid ins tructio n for the AT89C105 1 (with 1K of
memory), whereas LJMP 410H would not.
Table 1.
AT89C1051 SFR Map and Reset Values
0F8H 0FFH
0F0H B
00000000
0E8H 0EFH
0E0H ACC
00000000
0D8H 0DFH
0D0H PSW
00000000
0C8H 0CFH
0C0H 0C7H
0B8H IP
XXX00000
0B0H P3
11111111
0F7H
0E7H
0D7H
0BFH
0B7H
0A8H IE
0XX00000
0A0H 0A7H
98H 9FH
90H P1
11111111
88H TCON
00000000
80H SP
4-6
TMOD
00000000
00000111
TL0
00000000
DPL
00000000
AT89C1051
DPH
00000000
TH0
00000000
PCON
0XXX0000
0AFH
97H
8FH
87H
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