ATMEL AT88SC1616C User Manual
VCC = C1
RST = C2
SCL/CLK = C3
NC = C4
C5 = GND
C6 = NC
C7 = SDA/IO
C8 = NC
1
2
3
4
8
7
6
5
NC
NC
NC
GND
VCC
NC
SCL
SDA
Smart Card Module
8-lead SOIC, PDIP
BDTIC www.BDTIC.com/ATMEL
Features
• One of a Family of 9 Devices with User Memories from 1 Kbit to 256-Kbit
• 16-Kbit (2-Kbyte) EEPROM User Memory
– Sixteen 128-byte (1-Kbit) Zones
– Self-timed Write Cycle
– Single Byte or 16-byte Page Write Mode
– Programmable Access Rights for Each Zone
• 2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
• High Security Features
– 64-bit Mutual Authentication Protocol (Under License of ELVA)
– Encrypted Checksum
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-tearing Function
– Voltage and Frequency Monitor
• Smart Card Features
– ISO 7816 Class A (5V) or Class B (3V) Operation
– ISO 7816-3 Asynchronous T = 0 Protocol (Gemplus
– Multiple Zones, Key Sets and Passwords for Multi-application Use
– Synchronous 2-wire Serial Interface for Faster Device Initialization
– Programmable 8-byte Answer-To-Reset Register
– ISO 7816-2 Compliant Modules
• Embedded Application Features
– Low Voltage Operation: 2.7V to 5.5V
– Secure Nonvolatile Storage for Sensitive System or User Information
– 2-wire Serial Interface
– 1.0 MHz Compatibility for Fast Operation
– Standard 8-lead Plastic Packages, Green Compliant (exceeds RoHS)
– Same Pinout as 2-wire Serial EEPROMs
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 4,000V min
®
Patent)
CryptoMemory
16 Kbit
AT88SC1616C
Summary
®
Table 1. Pin Configuration
Pad Description ISO Module Contact Standard Package Pin
VCC Supply Voltage C1 8
GND Ground C5 4
SCL/CLK Serial Clock Input C3 6
SDA/IO Serial Data Input/Output C7 5
RST Reset Input C2 NC
Figure 1. Package Options
Rev. 2030KS–SMIC–3/09
Note: This is a summary document. A complete document is
available under NDA. For more information, please contact your
local Atmel sales office.
Description The AT88SC1616C member of the CryptoMemory
Random
Generator
Authentication,
Encryption and
Certification Unit
EEPROM
Answer to Reset
Data Transfer
Password
Verification
Reset Block
Asynchronous
ISO Interface
Synchronous
Interface
Power
Management
VCC
GND
SCL/CLK
SDA/IO
RST
ory providing 16 Kbits of user memory with advanced security and cryptographic features built
in. The user memory is divided into 16 128-byte zones, each of which may be individually set
with different security access rights or effectively combined together to provide space for 1 to 16
data files.
®
family is a high-performance secure mem-
Smart Card
Applications
Embedded
Applications
The AT88SC1616C provides high security, low cost, and ease of implementation without the
need for a microprocessor operating system. The embedded cryptographic engine provides for
dynamic and symmetric mutual authentication between the device and host, as well as performing stream encryption for all data and passwords exchanged between the device and host. Up to
four unique key sets may be used for these operations. The AT88SC1616C offers the ability to
communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus patent) defined in ISO 7816-3.
Through dynamic and symmetric mutual authentication, data encryption, and the use of
encrypted checksums, the AT88SC1616C provides a secure place for storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even
under attack. A 2-wire serial interface running at 1.0 MHz is used for fast and efficient communications with up to 15 devices that may be individually addressed. The AT88SC1616C is
available in industry standard 8-lead packages with the same familiar pinout as 2-wire serial
EEPROMs.
Figure 2. Block Diagram
Pin
Descriptions
Supply Voltage (VCC) The VCC input is a 2.7V to 5.5V positive voltage supplied by the host.
Clock (SCL/CLK) In the asynchronous T = 0 protocol, the SCL/CLK input is used to provide the device with a car-
2
AT88SC1616C
rier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary time
unit” (ETU) and is equal to 372/f. When the synchronous protocol is used, the SCL/CLK input is
used to positive edge clock data into the device and negative edge clock data out of the device.
2030KS–SMIC–3/09
AT88SC1616C
Reset (RST) The AT88SC1616C provides an ISO 7816-3 compliant asynchronous answer to reset
sequence. When the reset sequence is activated, the device will output the data programmed
into the 64-bit answer-to-reset register. An internal pull-up on the RST input pad allows the
device to be used in synchronous mode without bonding RST. The AT88SC1616C does not
support the synchronous answer-to-reset sequence.
Serial Data (SDA/IO) The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wired with any number of other open drain or open collector devices. An external pull-up resistor
should be connected between SDA and V
tance loading the SDA bus will determine the rise time of SDA. This rise time will determine the
maximum frequency during read operations. Low value pull-up resistors will allow higher frequency operations while drawing higher average power. SDA/IO information applies to both
asynchronous and synchronous protocols.
When the synchronous protocol is used, the SCL/CLK input is used to positive edge clock data
into the device and negative edge clock data out of the device.
Table 2. DC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V, TAC = -40oC to +85oC (unless otherwise noted)
Symbol Parameter Test Condition Min Typ Max Units
(2)
V
CC
I
CC
I
CC
I
CC
I
CC
I
SB
(1)
V
IL
(1)
V
IL
(1)
V
IL
(1)(2)
V
IH
(1)(2)
V
IH
(1)(2)
V
IH
I
IL
I
IL
I
IL
I
IH
I
IH
I
IH
V
OH
V
OL
I
OH
Notes: 1. VIL min and VIH max are reference only and are not tested.
Supply Voltage 2.7 5.5 V
Supply Current (VCC = 5.5V) Async READ at 3.57MHz 5 mA
Supply Current (VCC = 5.5V) Async WRITE at 3.57MHz 5 mA
Supply Current (VCC = 5.5V) Synch READ at 1MHz 5 mA
Supply Current (VCC = 5.5V) Synch WRITE at 1MHz 5 mA
Standby Current (VCC = 5.5V) VIN = VCC or GND 100 uA
SDA/IO Input Low Threshold 0 VCC x 0.2 V
SCL/CLK Input Low Threshold 0 VCC x 0.2 V
RST Input Low Threshold 0 VCC x 0.2 V
SDA/IO Input High Threshold VCC x 0.7 V
SCL/CLK Input High Threshold VCC x 0.7 V
RST Input High Threshold VCC x 0.7 V
SDA/IO Input Low Current 0 < V
SCL/CLK Input Low Current 0 < V
RST Input Low Current 0 < V
SDA/IO Input High Current VCC x 0.7 < VIH < V
SCL/CLK Input High Current VCC x 0.7 < VIH < V
RST Input High Current VCC x 0.7 < VIH < V
< VCC x 0.15 15 uA
IL
< VCC x 0.15 15 uA
IL
< VCC x 0.15 50 uA
IL
CC
CC
CC
SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7 V
SDA/IO Output Low Voltage IOL = 1mA 0 VCC x 0.15 V
SDA/IO Output High Current V
OH
2. To prevent Latch Up Conditions from occurring during Power Up of the AT88SCxxxxC, Vcc must be turned on before applying Vih. For Powering Down, Vih must be removed before turning Vcc off.
. The value of this resistor and the system capaci-
CC
CC
CC
CC
V
V
V
20 uA
100 uA
150 uA
CC
V
20 uA
2030KS–SMIC–3/09
3
Table 3. AC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 5.5V,
= -40oC to +85oC, CL = 30pF (unless otherwise noted)
T
AC
Symbol Parameter Min Max Units
f
CLK
f
CLK
f
CLK
t
t
t
t
t
AA
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
WR
t
WR
Async Clock Frequency (VCC Range: +4.5 - 5.5V) 1 5 MHz
Async Clock Frequency (VCC Range: +2.7 - 3.3V) 1 4 MHz
Synch Clock Frequency 0 1 MHz
Clock Duty cycle 40 60 %
Rise Time - I/O, RST 1 uS
R
Fall Time - I/O, RST 1 uS
F
Rise Time - CLK 9% x period uS
R
Fall Time - CLK 9% x period uS
F
Clock Low to Data Out Valid 35 nS
Start Hold Time 200 nS
Start Set-up Time 200 nS
Data In Hold Time 10 nS
Data In Set-up Time 100 nS
Stop Set-up Time 200 nS
Data Out Hold Time 20 nS
Write Cycle Time (at 25⋅C) 5 mS
Write Cycle Time (-40o to +85oC) 7 mS
Device
Operation For
Synchronous
Protocols
4
AT88SC1616C
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (see Figure 5 on
page 5). Data changes during SCL high periods will indicate a start or stop condition as defined
below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (see Figure 6 on page 6).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (see Fig-
ure 6 on page 6).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero to acknowledge that it has received each
word. This happens during the ninth clock cycle.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part
can be reset by following these steps:
1. Clock up to 9 cycles.
2. Look for SDA high in each cycle while SCL is high.
3. Create a start condition.
2030KS–SMIC–3/09
Figure 3. Bus Timing for 2 wire communications
CONDITION
S
S
DATA
CHANGE
ALLOWED
SCL: Serial Clock, SDA: Serial Data I/O
Figure 4. Write Cycle Timing:
SCL: Serial Clock, SDA: Serial Data I/O
CL
AT88SC1616C
DA
Figure 5. Data Validity
8th BIT
WORDn
Note: The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of
the internal clear/write cycle.
ACK
STOP
(1)
t
WR
START
CONDITION
5
2030KS–SMIC–3/09
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