ATMEL AT88SC0808CA User Manual
BDTIC www.BDTIC.com/ATMEL
1. Features
• One of a Family of Devices with User Memories from 1-Kbit to 8-Kbits
• 8-Kbit (1-Kbyte) EEPROM User Memory
– Eight 1-Kbit (128-byte) Zones
– Self-timed Write Cycle
– Single Byte or 16-byte Page Write Mode
– Programmable Access Rights for Each Zone
• 2-Kbit Configuration Zone
– 37-byte OTP Area for User-defined Codes
– 160-byte Area for User-defined Keys and Passwords
• High Security Features
– 64-bit Mutual Authentication Protocol (Under License of ELVA)
– Cryptographic Message Authentication Codes (MAC)
– Stream Encryption
– Four Key Sets for Authentication and Encryption
– Eight Sets of Two 24-bit Passwords
– Anti-Tearing Function
– Voltage and Frequency Monitors
• Smart Card Features
– ISO 7816 Class B (3V) Operation
– ISO 7816-3 Asynchronous T=0 Protocol (Gemplus® Patent)
– Multiple Zones, Key Sets and Passwords for Multi-application Use
– Synchronous 2-wire Serial Interface for Faster Device Initialization
– Programmable 8-byte Answer-To-Reset Register
– ISO 7816-2 Compliant Modules
• Embedded Application Features
– Low Voltage Supply: 2.7V – 3.6V
– Secure Nonvolatile Storage for Sensitive System or User Information
– 2-wire Serial Interface (TWI, 5V Compatible)
– 1.0 MHz Compatibility for Fast Operation
– Standard 8-lead Plastic Packages, Green compliant (exceeds RoHS)
– Same Pin Configuration as AT24CXXX Serial EEPROM in SOIC and PDIP Packages
• High Reliability
– Endurance: 100,000 Cycles
– Data Retention: 10 years
– ESD Protection: 2,000V min
CryptoMemory
AT88SC0808CA
Summary
Table 1-1. Pads
Pad Description ISO Module “SOIC, PDIP” TSSOP
VCC Supply Voltage C1 8 8
GND Ground C5 4 1
SCL/CLK Serial Clock Input C3 6 6
SDA/IO Serial Data Input/Output C7 5 3
RST Reset Input C2 NC NC
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2. Description
1
2
3
4
8
7
6
5
Smart Card Module
VCC=C1
RST=C2
SCL/CLK=C3
NC=C4
C5=GND
C6=NC
C7=SDA/IO
C8=NC
8-lead SOIC, PDIP
NC
NC
NC
GND
VCC
NC
SCL
SDA
8-lead TSSOP
NC
1 8 VCC
NC
27NC
8-Lead TSSOP
NC
3 6 SCL
GND
45
SDA
The AT88SC0808CA member of the CryptoMemory® family is a high-performance secure
memory providing 8 Kbit of user memory with advanced security and cryptographic features built
in. The user memory is divided into eight 128-byte zones, each of which may be individually set
with different security access rights or effectively combined together to provide space for 1 to 8
data files. The AT88SC0808CA features an enhanced command set that allows direct communication with microcontroller hardware 2-Wire interface thereby allowing for faster firmware
development with reduced code space requirements.
3. Smart Card Applications
The AT88SC0808CA provides high security, low cost, and ease of implementation without the
need for a microprocessor operating system. The embedded cryptographic engine provides for
dynamic, symmetric-mutual authentication between the device and host, as well as performing
stream encryption for all data and passwords exchanged between the device and host. Up to
four unique key sets may be used for these operations. The AT88SC0808CA offers the ability to
communicate with virtually any smart card reader using the asynchronous T = 0 protocol (Gemplus Patent) defined in ISO 7816-3.
4. Embedded Applications
Through dynamic, symmetric-mutual authentication, data encryption, and the use of cryptographic Message Authentication Codes (MAC), the AT88SC0808CA provides a secure place for
storage of sensitive information within a system. With its tamper detection circuits, this information remains safe even under attack. A 2-wire serial interface running at speeds up to 1.0 MHz
provides fast and efficient communications with up to 15 individually addressable devices. The
AT88SC0808CA is available in industry standard 8-lead packages with the same familiar pin
configuration as AT24CXXX serial EEPROM devices.
2
Note: Does not apply to TSSOP Pinout.
AT88SC0808CA
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Figure 4-1. Block Diagram
Random
Generator
Authentication,
Encryption and
Certification Unit
EEPROM
Answer to Reset
Data Transf er
Password
Verification
Reset Block
Asynchronous
ISO Interface
Synchronous
Interface
Power
Management
VCC
GND
SCL/CLK
SDA/IO
RST
5. Connection Diagram
AT88SC0808CA
Figure 5-1. Connection Diagram
Microprocessor CryptoMemory
2.7v - 5.5v
2.7v - 3.6v
SDA
SCL
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6. Pin Descriptions
6.1 Supply Voltage (VCC)
The VCC input is a 2.7V to 3.6V positive voltage supplied by the host.
6.2 Clock (SCL/CLK)
When using the asynchronous T = 0 protocol, the CLK (SCL) input provides the device with a
carrier frequency f. The nominal length of one bit emitted on I/O is defined as an “elementary
time unit” (ETU) and is equal to 372/f.
When using the synchronous protocol, data clocking is done on the positive edge of the clock
when writing to the device and on the negative edge of the clock when reading from the device.
6.3 Reset (RST)
The AT88SC0808CA provides an ISO 7816-3 compliant asynchronous Answer-To-Reset (ATR)
sequence. Upon activation of the reset sequence, the device outputs bytes contained in the 64bit Answer-To-Reset register. An internal pull-up on the RST input pad allows the device to operate in synchronous mode without bonding RST. The AT88SC0808CA does not support an
Answer-To-Reset sequence in the synchronous mode of operation.
6.4 Serial Data (SDA/IO)
The SDA/IO pin is bidirectional for serial data transfer. This pin is open-drain driven and may be
wired with any number of other open-drain or open-collector devices. An external pull-up resistor
should be connected between SDA/IO and VCC. The value of this resistor and the system
capacitance loading the SDA/IO bus will determine the rise time of SDA/IO. This rise time will
determine the maximum frequency during read operations. Low value pull-up resistors will allow
higher frequency operations while drawing higher average power supply current. SDA/IO information applies to both asynchronous and synchronous protocols.
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AT88SC0808CA
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AT88SC0808CA
7. Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of
time may affect device reliability.
Absolute Maximum Ratings
Operating Temperature..................................... -40⋅C to +85⋅C
Storage Temperature .......................................... −65
⋅C to +150⋅C
Voltage on Any Pin
with Respect to Ground.................................... −0.7 to Vcc +0.7V
Maximum Operating Voltage............................................. 6.0V
DC Output Current........................................................ 5.0 mA
Table 7-1. DC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 3.6V, T
= -40⋅C to +85⋅C (unless otherwise noted)
AC
Symbol Parameter Test Condition Min Typ Max Units
(1)
V
CC
I
CC
I
CC
I
CC
I
CC
I
SB
V
IL
V
IL
V
IL
(1)
V
IH
(1)
V
IH
(1)
V
IH
I
IL
I
IL
I
IL
I
IH
I
IH
I
IH
V
OH
V
OL
Supply Voltage 2.7 3.6 V
Supply Current Async READ at 3.57MHz 5 mA
Supply Current Async WRITE at 3.57MHz 5 mA
Supply Current Synch READ at 1MHz 5 mA
Supply Current Synch WRITE at 1MHz 5 mA
Standby Current VIN = VCC or GND 100 uA
SDA/IO Input Low Voltage 0 VCC x 0.2 V
CLK Input Low Voltage 0 VCC x 0.2 V
RST Input Low Voltage 0 VCC x 0.2 V
SDA/IO Input High Voltage VCC x 0.7 5.5 V
SCL/CLK Input High Voltage VCC x 0.7 5.5 V
RST Input High Voltage VCC x 0.7 5.5 V
SDA/IO Input Low Current 0 < VIL < VCC x 0.15 15 uA
SCL/CLK Input Low Current 0 < VIL < VCC x 0.15 15 uA
RST Input Low Current 0 < VIL < VCC x 0.15 50 uA
SDA/IO Input High Current VCC x 0.7 < VIH < VCC 20 uA
SCL/CLK Input High Current VCC x 0.7 < VIH < VCC 100 uA
RST Input High Current VCC x 0.7 < VIH < VCC 150 uA
SDA/IO Output High Voltage 20K ohm external pull-up VCC x 0.7 VCC V
SDA/IO Output Low Voltage IOL = 1mA 0 VCC x 0.15 V
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Table 7-1. DC Characteristics (Continued)
Applicable over recommended operating range from VCC = +2.7 to 3.6V, T
= -40⋅C to +85⋅C (unless otherwise noted)
AC
Symbol Parameter Test Condition Min Typ Max Units
I
OH
I
OL
Note: 1. To prevent Latch Up Conditions from occurring during Power Up of the AT88SC0808CA, V
SDA/IO Output High Current VOH 20 uA
SDA/IO Output Low Current VOL 10 mA
must be turned on before
applying V
. For Powering Down, VIH must be removed before turning VCC off.
IH
CC
Table 7-2. AC Characteristics
Applicable over recommended operating range from VCC = +2.7 to 3.6V, TAC = -40°C to +85°C, CL = 30pF (unless otherwise noted)
Parameter Min Max Units
f
Async Clock Frequency 1 4 MHz
CLK
Synch Clock Frequency 0 1 MHz
f
CLK
Clock Duty cycle 40 60 %
tR “Rise Time - SDA/IO, RST” 1 uS
t
F
t
Rise Time - SCL/CLK 9% x period uS
R
t
F
t
AA
t
HD.STA
t
SU.STA
t
HD.DAT
t
SU.DAT
t
SU.STO
t
DH
t
WR
“Fall Time - SDA/IO, RST” 1 uS
Fall Time - SCL/CLK 9% x period uS
Clock Low to Data Out Valid 250 nS
Start Hold Time 200 nS
Start Set-up Time 200 nS
Data In Hold Time 10 nS
Data In Set-up Time 100 nS
Stop Set-up Time 200 nS
Data Out Hold Time 20 nS
Write Cycle Time 5mS
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AT88SC0808CA
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8. Device Operations for Synchronous Protocols
8.1 Clock and Data Transitions
The SDA pin is normally pulled high with an external device. Data on the SDA pin may change
only during SCL low time periods (see Figure 8-3 on page 8). Data changes during SCL high
periods will indicate a start or stop condition as defined below.
8.1.1 Start Condition
A high-to-low transition of SDA with SCL high defines a START condition which must precede all
commands (see Figure 8-4 on page 8).
8.1.2 Stop Condition
A low-to-high transition of SDA with SCL high defines a STOP condition. After a read sequence,
the STOP condition will place the EEPROM in a standby power mode (see Figure 8-4 on page
8).
8.1.3 ACKNOWLEDGE
All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words.
The EEPROM sends a zero to acknowledge that it has received each word. This happens during the ninth clock cycle (see Figure 8-5 on page 9).
AT88SC0808CA
8.2 Memory Reset
After an interruption in communication due protocol errors, power loss or any reason, perform
"Acknowledge Polling" to properly recover from the condition. Acknowledge polling consists of
sending a start condition followed by a valid CryptoMemory command byte and determining if
the device responded with an ACKNOWLEDGE.
Figure 8-1. Bus Time for 2-Wire Serial Communications. SCL: Serial Clock, SDA: Serial Data I/O
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