ATMEL AT87C5103 User Manual

BDTIC www.BDTIC.com/ATMEL

Features

• 80C51 Compatible CPU Core High-speed Architecture

• X2 Speed Improvement Capability (6 Clocks/Machine Cycle)

• 16 MHz in Standard or X2 mode

• 256 Bytes RAM

• 256 Bytes XRAM

• 12K Bytes ROM/OTP Program Memory

• Two 16-bit Timer/Counters T0, T1

• 5 Channels Programmable Counter Array with High-speed Output, Compare/Capture,

Pulse Width Modulation and Watchdog Timer Capabilities

• SPI Interface (Master and Slave mode)

• Interrupt Structure with:

– 6 Interrupt Sources
– 4 Interrupt Priority Levels

• Power Supply: 3 - 5.5V

• Temperature Range: Industrial (-40

• Package: SSOP16, SSOP24

o

C to 85oC), Automotive (-40oC to 125oC)

Low-pin Count
8-bit
Microcontroller

Description

The AT8xC5103 is a high-performance ROM/OTP version of the 80C51 8-bit Micro­controller in 16 and 24-pin packages.

The AT8xC5103 contains a standard C51 CPU core with 12 Kbytes ROM/OTP pro­gram memory, 256 bytes of internal RAM, 256 bytes of extended internal RAM, a 5­sources 4-level interrupt system, two timer/counters and a SPI serial bus controller.

The AT8xC5103 is also dedicated for analog interfacing applications. For this, it has a
five channels Programmable Counter Array.

In addition, the AT8xC5103 implements the X2 speed improvement mechanism. The
X2 feature allows to keep the same C PU power at a divided by two oscillator
frequency.

The fully static design of the AT8xC5103 allows to reduce system power consumption
by bringing the clock frequency down to any value, even DC, without loss of data.

AT87C5103
AT83C5103

Rev. 4134D–8051–02/08

1

Block Diagram

Timer 0

INT

RAM

256x8

T0

XTAL2

XTAL1

CPU

Timer 1

Ctrl

INT0

C51

CORE

(3) (3)

Port 1

P1

P3

IB-bus

Vss

Vcc

ROM

12 K *8

CEX0-4

Xtal
Osc

(1)

Port 3

PCA

MISO

(1)

MOSI

(1)

SPSCK

(3)

SPI

SS

(1)

RST

ECI

(1)

256x8

Parallel I/O Ports

EXRAM

P4

Port 4

INT1

(3)

T1

(3)

Notes: 1. Alternate function of Port 1.

2. Alternate function of Port 3.

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4134D–8051–02/08

Pin Configurations

XTAL1

VCC

VSS

1

RST/VPP

XTAL2

P1.2/ECI/DIG2

P3.2/DIG0/INT0

P3.6/SPICK

P3.4/DIG1/T0

P1.7/CEX4/SS

P1.6/CEX3

P1.5/CEX2

P1.4/CEX1

P1.3/CEX0

2

3
4

5

6

7
8

16

15
14

13

12
11

10

9

P1.1/MOSI

P1.0/MISO

SSOP16

P1.1/MOSI
P1.0/MISO

VCC

XTAL2

P1.5/CEX2

VSS

XTAL1

P1.2/ECI/DIG2

RST/VPP

P3.1

P3.6/SPICK

1

2
3
4

5
6
7
8

16

15

14

13

9
10
11
12

P1.6/CEX3

P3.7

P3.5/T1

20

19

18

17

24

23

22

21

P3.4/DIG1/T0

P4.0

P4.1

P4.2

P1.3/CEX0

P1.4/CEX1

P3.0

P1.7/CEX4/SS

P3.3/INT1

P3.2/DIG0/INT0

SSOP24

4134D–8051–02/08

3

Pin Description

Mnemonic Type Name and Function

V

SS

V

CC

P1.0 - P1.7

I Ground: 0V reference

I Power Supply: 3.0V or 5.5V

Port 1: Port 1 is an 8-bit programmable I/O port with internal pull-up

I/O

Alternate functions for Port 1 include:

I/O MISO (P1.0): Master IN, Slave OUT of the SPI controller

I/O MOSI (P1.1): Master OUT, Slave IN of the SPI controller

DIG2 (P1.2): Programmable as Output with Push-pull

I/O

ECI: External Clock for PCA

I/O CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

I/O CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

I/O CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

I/O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

SS (P1.7): Slave select input of the SPI controller

I/O

CEX4: Capture/Compare External I/O for PCA module 3

XTAL1 I Input to the inverting oscillator amplifier

XTAL2 O Output from the inverting oscillator amplifier

RST/VPP

RST: Negative Reset input
A low on this pin for two machine cycles while the oscillator is running,

resets the device.

I

This pin will include a pull-down to reset the circuit if no external reset
level is applied.

VPP: High voltage input for OTP programming

P3.0 - P3.7 I/O Port 3: Port 3 is a 8-bit programmable I/O port with internal pull-up.

I/O P3.0: Programmable as Output with Push-pull.

I/O P3.1: Programmable as Output with Push-pull.

DIG0 (P3.2): Programmable as Output with Push-pull.

I/O

INT0: External Interrupt 0

P3.3: Programmable as Output with Push-pull.

I/O

INT1: External Interrupt 1

DIG1 (P3.4): Programmable as Output with Push-pull.

I/O

T0: Timer 0 external Input

P3.5: Programmable as Output with Push-pull.

I/O

T1: Timer 1 external Input

I/O SPICK (P3.6): Clock I/O of the SPI controller

I/O P3.7: Programmable as Output with Push-pull.

P4.0-P4.2 I/O

Port 4: Port 4 is an 3-bit I/O port with internal pull-up

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Clock

The Errata Sheet core needs only 6 clock periods per machine cycle. This feature,
called ”X2”, provides the following advantages:

• Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU
power.

• Saves power consumption while keeping the same CPU power (oscillator power
saving).

• Saves power consumption by dividing dynamic operating frequency by 2 in
operating and idle modes.

• Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the
XTAL1 signal and the main clock input of the core (phase generator). This divider may
be disabled by the software.

Description

The clock for the whole circuit and peripheral is first divided by 2 before being used by
the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1
input. In X2 Mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic
ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. The X2
bit is validated on the XTAL1 ÷ 2 rising edge to avoid glitches when switching from the
X2 to the STD mode. Figure 2 shows the mode switching waveforms.

4134D–8051–02/08

5

Figure 1. Clock CPU Generation Diagram

XTAL1

XTAL2

PD

PCON.1

1

0

÷

2

FCLK_PERIPH

Peripheral

X2

CKCON.0

CKCON0.7 CKCON0.6

PCAX2

CKCON0.5 CKCON0.4 CKCON0.3

T1X2

CKCON0.2

T0X2

CKCON0.1

IDL

PCON.0

1

0

÷

2

1

0

÷

2

1

0

÷

2

1

0

÷

2

X2

CKCON0.0

FSPI Clock

FPCA Clock

FT1 Clock

FT0 Clock

FCPU

CKCON1.7 CKCON1.6

CKCON1.5

CKCON1.4 CKCON1.3 CKCON1.2

CKCON1.1

SPIX2

CKCON1.0

Clock Symbol

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4134D–8051–02/08

Figure 2. Mode Switching Waveforms

XTAL2

XTAL1

CPU Clock

X2 Bit

X2 ModeSTD Mode STD Mode

The X2 bit in the CKCON register (See Table 1) allows switching from 12 clock cycles
per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated
(STD mode). Setting this bit activates the X2 feature (X2 Mode).

Note: In order to prevent any incorrect operation while operating in the X2 Mode, users must be

aware that all peripherals using the clock frequency as a time reference (timers, PCA,
SPI) will have their time reference divided by 2. For example, a free running timer gener­ating an interrupt every 20 ms will then generate an interrupt every 10 ms.

4134D–8051–02/08

7

Registers

Table 1. CKCON0 Register

CKCON0 (S:8Fh)
Clock Control Register

7 6 5 4 3 2 1 0

PCAX2 T1X2 T0X2 X2

Bit

Number

7 –

6 –

5 PCAX2

4 –

3 –

2 T1X2

1 T0X2

0 X2

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Programmable Counter Array clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer1 Clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

Timer0 Clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

CPU Clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all
the peripherals.
Set to select 6 clock periods per machine cycle (X2 Mode) and to enable the
individual peripherals "X2" bits.

(1)

(1)

(1)

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = XX0X X000b

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Table 2. CKCON1 Register
CKCON1 (S:AFh)
Clock Control Register

7 6 5 4 3 2 1 0

SPIX2

Bit

Number

7 –

6 –

5 –

4 –

3 –

2 –

1 –

0 SPIX2

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI clock

Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.

(1)

Note: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = XXXX XXX0b

4134D–8051–02/08

9

SFR Mapping

The Special Function Registers (SFRs) of the AT8xC5103 belong to the following
categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2

• Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1

• Power and clock control registers: CKCON0, CKCON1, PCON

• Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1

• SPI: SPCON, SPSTA, SPDAT

• PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H,
CCAP2H, CCAP3H, CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3,
CCAPM4, CL, CH, CMOD, CCON

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4134D–8051–02/08

Table 3. SFR Addresses and Reset Values

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

B

0000 0000

ACC

0000 0000

CCON

00X0 0000

PSW

0000 0000

P4

XXXX X111

IPL0

X0XX 0000

P3

1111 1111

IE0

00XX 0000

CH

0000 0000

CL

0000 0000

CMOD

00XX X000

IE1

XXXX X0XX

CCAP0H

0000 0000

CCAP0L

0000 0000

P1M2

0000 0000

CCAPM0

X000 0000

IPL1

XXXX X0XX

CCAP1H

0000 0000

CCAP1L

0000 0000

CCAPM1

X000 0000

SPCON

0001 0100

IPH1

XXXX X0XX

CCAP2H

0000 0000

CCAP2L

0000 0000

P3M2

0000 0000

CCAPM2

X000 0000

P1M1

0000 0000

SPSTA

00X0 XXXX

CCAP3H

0000 0000

CCAP3L

0000 0000

CCAPM3

X000 0000

P3M1

0000 0000

SPDAT

XXXX XXXX

CCAP4H

0000 0000

CCAP4L

0000 0000

CCAPM4

X000 0000

IPH0

X0XX 0000

CKCON1

XXXX XXX0

FFh

F7h

EFh

E7h

DF

h

D7h

CF

h

C7h

BFh

B7h

AFh

A0h

98h 9Fh

90h

88h

80h

P1

1111 1111

TCON

0000 0000

0/8 1/9 2/A 3/B 4/C 5/D 6/E 7/F

TMOD

0000 0000

SP

0000 0111

AUXR1

XXXXX0X0

TL0

0000 0000

DPL

0000 0000

TL1

0000 0000

DPH

0000 0000

TH0

0000 0000

TH1

0000 0000

CKCON0

XX0X X000b

PCON

XXX1 0000

A7h

97h

8Fh

87h

Reserved

4134D–8051–02/08

11

Ports

Port Types

The AT8xC5103 has 3 I/O ports, port 1, port 3 and port 4.

Except RST, and port 4, all port 1 and port 3 I/O port pins on the AT8xC5103 may be
software configured to one of four types on a bit-by-bit basis, as shown in Table 2 These
are: quasi-bi-directional (standard 80C51 port outputs), push-pull, open drain, and input
only. Two configuration registers for each port choose the output type for each port pin.

PxM1.y BIt PxM2.y Bit Port Output Mode

0 0 Quasi bi-directional

0 1 Push-pull

1 0 Input Only (High Impedance)

1 1 Open Drain

Quasi-Bi-directional Output Configuration

The default port output configuration for standard AT8xC5103 I/O ports is the quasi-bi­directional output that is common on the 80C51 and most of its derivatives. This output
type can be used as both an input and output without the need to reconfigure the port.
This is possible because when the port outputs a logic high, it is weakly driven, allowing
an external device to pull the pin low. When the pin is pulled low, it is driven strongly and
able to sink a fairly large current. These features are somewhat similar to an open drain
output except that there are three pull-up transistors in the quasi-bi-directional output
that serve different purposes. One of these pull-ups, called the ‘very weak’ pull-up, is
turned on whenever the port latch for the pin contains a logic 1. The very weak pull-up
sources a very small current that will pull the pin high if it is left floating. A second pull­up, called the ‘weak’ pull-up, is turned on when the port latch for the pin contains a logic
1 and the pin itself is also at a logic 1 level. This pull-up provides the primary source cur­rent for a quasi-bi-directional pin that is outputting a 1. If a pin that has a logic 1 on it is
pulled low by an external device, the weak pull-up turns off, and only the very weak pull­up remains on. In order to pull the pin low under these conditions, the external device
has to sink enough current to overpower the weak pull-up and take the voltage on the
port pin below its input threshold.

The third pull-up is referred to as the ‘strong’ pull-up. This pull-up is used to speed up
low-to-high transitions on a quasi-bi-directional port pin when the port latch changes
from a logic 0 to a logic 1. When this occurs, the strong pull-up turns on for a brief time,
two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The quasi-bi-directional port configuration is shown in Figure 3.

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Figure 3. Quasi-Bi-directional Output

2 CPU

Input

Pin

Strong

Very

Weak

N

P

P

Weak

P

Clock Delay

Port latch

Data

Data

Input

Pin

N

Port latch

Data

Data

Input

Pin

Strong

N

P

Port Latch

Data

Data

Open Drain Output Configuration

Figure 4. Open Drain Output

Push-Pull Output Configuration

Figure 5. Push-pull Output

The open-drain output configuration turns off all pull-ups and only drives the pull-down
transistor of the port driver when the port latch contains a logic 0. To be used as a logic
output, a port configured in this manner must have an external pull-up, typically a resis­tor tied to VDD. The pull-down for this mode is the same as for the quasi-bi-directional
mode. The open drain port configuration is shown in Figure 4.

The push-pull output configuration has the same pull-down structure as both the open
drain and the quasi-bi-directional output modes, but provides a continuous strong pull­up when the port latch contains a logic 1. The push-pull mode may be used when more
source current is needed from a port output. The push-pull port configuration is shown in
Figure 5.

4134D–8051–02/08

13

Input Only Configuration The input only configuration is a pure input with neither pull-up nor pull-down.

Input

Pin

Data

The input only configuration is shown in Figure 6.

Figure 6. Input Only

Ports Description

Ports P1 and P3

The inputs of each I/O port of the AT8xC5103 are TTL level Schmitt triggers with
hysteresis.

Registers Table 4. P1M1 Register

P1M1 Address (D4h)

7 6 5 4 3 2 1 0

P1M1.7 P1M1.6 P1M1.5 P1M1.4 P1M1.3 P1M1.2 P1M1.1 P1M1.0

Bit

Number

0-7 P1M1.x

Bit

Mnemonic Description

Reset Value = 0000 0000

Table 5. P1M2 Register
P1M2 Address (E2h)

7 6 5 4 3 2 1 0

P1M2.7 P1M2.6 P1M2.5 P1M2.4 P1M2.3 P1M2.2 P1M2.1 P1M2.0

Bit

Bit Number

Mnemonic Description

Port Output configuration Bit

See Table 2 for configuration definition

14

0-7 P1M2.x

Reset Value = 0000 0000

Port Output configuration bit

See Table 2 for configuration definition

4134D–8051–02/08

Table 6. P3M1 Register
P3M1 Address (D5h)

7 6 5 4 3 2 1 0

P3M1.7 P3M1.6 P3M1.5 P3M1.4 P3M1.3 P3M1.2 P3M1.1 P3M1.0

Bit Number

0-7 P3M1.x

Bit

Mnemonic Description

Port Output configuration bit

See Table 2 for configuration definition

Reset Value = 0000 0000

Table 7. P3M2 Register
P3M2 Address (E4h)

7 6 5 4 3 2 1 0

P3M2.7 P3M2.6 P3M2.5 P3M2.4 P3M2.3 P3M2.2 P3M2.1 P3M2.0

Bit Number

0-7 P3M2.x

Bit

Mnemonic Description

Port Output configuration bit

See Table 2 for configuration definition

Reset Value = 0000 0000

4134D–8051–02/08

15

Dual-data Pointer

External Data Memory

AUXR1(A2H)

DPS

DPH(83H) DPL(82H)

07

DPTR0

DPTR1

Register (DPTR)

Figure 7. Use of Dual-data Pointer

The additional data pointer can be used to speed up code execution and reduce code
size in a number of ways.

The dual DPTR structure is a way by which the device will specify the address of an
external data memory location. There are two 16-bit DPTR registers that address the
external memory, and a single bit called DPS = AUXR1/bit0 (see Table 8) that allows
the program code to switch between them (Refer to Figure 7).

Table 8. AUXR1: Auxiliary Register 1

7 6 5 4 3 2 1 0

- - - - - 0 - DPS

Bit

Number

7-3 -

2 0 always stuck at 0

1 -

0 DPS

Bit

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Clear to select DPTR0.
Set to select DPTR1.

(1)

Reset Value = XXXX X0X0

Note: 1. User software should not write 1s to reserved bits. These bits may be used in future

8051 family products to invoke new features. In that case, the reset value of the new
bit will be 0, and its active value will be 1. The value read from a reserved bit is
indeterminate.

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4134D–8051–02/08

Application

Software can take advantage of the additional data pointers to both increase speed and
reduce code size, for example, block operations (copy, compare, search...) are well
served by using one data pointer as a ’source’ pointer and the other one as a "destina­tion" pointer.

ASSEMBLY LANGUAGE

; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1
SFR. However, note that the INC instruction does not directly force the DPS bit to a par­ticular state, but simply toggles it. In simple routines, such as the block move example,
only the fact that DPS is toggled in the proper sequence matters, not its actual value. In
other words, the block move routine works the same whether DPS is “0” or “1” on entry.
Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in
the opposite state.

4134D–8051–02/08

17

Serial Port Interface

Slave 1

MISO

MOSI

SCK

SS

MISO
MOSI
SCK
SS

PORT

0
1

2
3

Slave 3

MISO

MOSI

SCK

SS

Slave 4

MISO

MOSI

SCK

SS

Slave 2

MISO

MOSI

SCK

SS

V

DD

Master

(SPI)

The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous,
serial communication between the MCU and peripheral devices, including other MCUs.

Features

Signal Description

Features of the SPI module include the following:

• Full-duplex, three-wire synchronous transfers

• Master or Slave operation

• Eight programmable Master clock rates

• Serial clock with programmable polarity and phase

• Master Mode fault error flag with MCU interrupt capability

• Write collision flag protection

Figure 8 shows a typical SPI Bus configuration using one Master controller and many
Slave peripherals. The bus is made of three wires connecting all the devices.

Figure 8. Typical SPI Bus

The Master device selects the individual Slave devices by using four pins of a parallel
port to control the four SS pins of the Slave devices.

Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the Master device and a Slave device.
The MOSI line is used to transfer data in series from the Master to the Slave. Therefore,
it is an output signal from the Master, and an input signal to a Slave. A byte (8-bit word)
is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave device and a Master device.
The MISO line is used to transfer data in series from the Slave to the Master. Therefore,
it is an output signal from the Slave, and an input signal to the Master. A byte (8-bit
word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

SPI Serial Clock (SCK) This signal is used to synchronize the data movement both in and out the devices

through their MOSI and MISO lines. It is driven by the Master for eight clock cycles
which allows to exchange one byte on the serial lines.

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Slave Select (SS) Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay

low for any message for a Slave. It is obvious that only one Master (SS high level) can
drive the network. The Master may select each Slave device by software through port
pins (Figure 8). To prevent bus conflicts on the MISO line, only one slave should be
selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in
the SPI Status register (SPSTA) to prevent multiple masters from driving MOSI and
SCK (See Error Conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general purpose if the following conditions are met:

• The device is configured as a Master and the SSDIS control bit in SPCON is set.
This kind of configuration can be found when only one Master is driving the network
and there is no way that the SS pin will be pulled low. Therefore, the MODF flag in
the SPSTA will never be set

• The Device is configured as a Slave with CPHA and SSDIS control bits set

(1)

.

(2)

. This
kind of configuration can happen when the system comprises one Master and one
Slave only. Therefore, the device should always be selected and there is no reason
that the Master uses the SS pin to select the communicating Slave device.

Baud Rate In Master Mode, the baud rate can be selected from a baud rate generator which is con-

trolled by three bits in the SPCON register: SPR2, SPR1 and SPR0. The Master clock is
chosen from one of six clock rates resulting from the division of the internal clock by 4, 8,
16, 32, 64 or 128.

Table 9 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 9. SPI Master Baud Rate Selection

SPR2:SPR1:SPR0 Clock Rate Baud Rate Divisor (BD)

000 Don’t Use No BRG

001 F

010 F

011 F

100 F

101 F

110 F

111 Don’t Use No BRG

CLK_PERIPH

CLK_PERIPH

CLK_PERIPH

CLK_PERIPH

CLK_PERIPH

CLK_PERIPH

/4 4

/8 8

/16 16

/32 32

/64 64

/128 128

4134D–8051–02/08

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = “0” because in
this mode, the SS is used to start the transmission.

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