ATMEL AT 86 RF 230 Service Manual
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ZigBee™/IEEE
Features
• Fully Integrated 2.4 GHz-band Transceiver
• -101 dBm Receiver Sensitivity
• Low Current Consumption (Typical Values)
− SLEEP = 0.1 µA
− TRX_OFF = 1.7 mA
− RX_ON = 16 mA
− BUSY_TX = 17 mA (max. PTX)
• Power Supply Range 1.8V – 3.6V
− Internal LDO Voltage Regulators
− Battery Monitor
• SPI Slave Interface
• Baseband Signal Processing Compliant with IEEE 802.15.4
− SFD Detection, Spreading/De-spreading, Framing
− 128-byte FIFO for TRX
• Integrated Crystal Oscillator, 16 MHz
• Digital RSSI Register, 5-bit Value
• Fast Power-up Time < 1 msec
• Programmable TX Output Power from -17 dBm up to 3 dBm
• Integrated LNA
• Low External Component Count
− Antenna
− Reference Crystal
− De-coupling Capacitors
• Integrated TX/RX Switch
• Integrated PLL Loop Filter
• Automatic VCO and Filter Calibration
• 32-pin Low-profile Lead-free Plastic QFN Package 5 mm x 5 mm x 0.9 mm
• Compliant to EN 300 440/328, FCC-CFR-47 Part 15
• Compliant to IEEE 802.15.4
802.15.4Transceiver
AT86RF230
Applications
• 802.15.4 Transceiver
• Transceiver for ZigBee System Solutions
Description
The AT86RF230 is a low-power 2.4 GHz transceiver specially designed for low
cost ZigBee/IEEE802.15.4 applications. The AT86RF230 is a true SPI-toantenna solution. All RF-critical components except the antenna, crystal and decoupling capacitors are integrated on-chip.
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AT86RF230
Table of contents
1.
Abbreviations ...................................................................................................................................................4
2.
General Circuit Description ..............................................................................................................................5
3.
Technical Parameters ......................................................................................................................................6
3.1.
Absolute Maximum Ratings.........................................................................................................................6
3.2.
Recommended Operating Range................................................................................................................6
3.3.
Digital Pin Specifications .............................................................................................................................6
3.4.
General RF Specifications...........................................................................................................................7
3.5.
Transmitter Specifications ...........................................................................................................................7
3.6.
Receiver Specifications ...............................................................................................................................8
3.7.
Current Consumption Specifications...........................................................................................................9
3.8.
SPI Timing Specifications............................................................................................................................9
3.9.
Crystal Parameter Specifications ..............................................................................................................10
4.
Basic Operating Modes .................................................................................................................................11
4.1.
Configuration .............................................................................................................................................11
4.2.
Basic Operating Mode Description............................................................................................................12
4.2.1. P_ON ....................................................................................................................................................12
4.2.2. SLEEP...................................................................................................................................................12
4.2.3. TRX_OFF..............................................................................................................................................12
4.2.4. PLL_ON ................................................................................................................................................12
4.2.5. RX_ON and BUSY_RX .........................................................................................................................13
4.2.6. RX_ON_NOCLK ...................................................................................................................................13
4.2.7. BUSY_TX..............................................................................................................................................13
4.3.
Basic Mode Timing ....................................................................................................................................13
4.3.1. Wake-up Procedure ..............................................................................................................................13
4.3.2. Transition from PLL_ON via BUSY_TX to RX_ON...............................................................................14
4.3.3. State Transition Timing .........................................................................................................................15
5.
Extended Operating Modes ...........................................................................................................................16
5.1.
Peer-to-peer Network Support ..................................................................................................................16
5.2.
Configuration .............................................................................................................................................18
5.3.
Extended Operation Mode Description .....................................................................................................18
5.3.1. RX_AACK_ON ......................................................................................................................................18
5.3.2. TX_ARET_ON.......................................................................................................................................18
5.3.3. RX_AACK_NOCLK ...............................................................................................................................19
6.
Functional Description ...................................................................................................................................20
6.1.
RSSI/Energy Detection .............................................................................................................................20
6.2.
Link Quality Indication ...............................................................................................................................20
6.3.
Clear Channel Assessment .......................................................................................................................20
6.4.
Voltage Regulators ....................................................................................................................................20
6.5.
Battery Monitor ..........................................................................................................................................21
6.6.
Crystal Oscillator .......................................................................................................................................22
6.7.
PLL Frequency Synthesizer ......................................................................................................................23
6.8.
Automatic Filter Tuning .............................................................................................................................24
7.
PHY to Micro-Controller Interface..................................................................................................................25
7.1.
SPI Protocol...............................................................................................................................................25
7.2.
Register Access Mode (Short Mode) ........................................................................................................26
7.3.
Frame Buffer Access Modes (Long Modes)..............................................................................................27
7.4.
Frame Receive Procedure ........................................................................................................................28
7.5.
Frame Transmit Procedure .......................................................................................................................28
7.6.
Sleep/Wake-up and Transmit Signal.........................................................................................................29
7.7.
Interrupt Logic............................................................................................................................................30
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AT86RF230
8.
Control Registers ...........................................................................................................................................31
9.
Application Circuit ..........................................................................................................................................42
10.
Pin Configuration ...........................................................................................................................................44
10.1. Pin-out Diagram.........................................................................................................................................45
10.2. Decoupling.................................................................................................................................................45
10.3. Analog Pins ...............................................................................................................................................45
10.4. RF Pins......................................................................................................................................................45
10.5. Digital Pins.................................................................................................................................................46
11.
Ordering Information ......................................................................................................................................47
12.
Soldering Information.....................................................................................................................................47
13.
Package Thermal Properties .........................................................................................................................47
14.
Package Drawing – 32QN1 ...........................................................................................................................48
15.
References.....................................................................................................................................................49
16.
Revisions .......................................................................................................................................................49
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AT86RF230
1. Abbreviations
AACK — Auto acknowledge
ACK — Acknowledge
ADC — Analog-to-digital converter
AGC — Automatic gain control
ARET — Auto retry
AVREG — Analog voltage regulator
BATMON — Battery monitor
BBP — Base-band processor
BPF — Complex band-pass filter
CCA — Clear channel assessment
CLKM — Clock main
CRC — Cyclic redundancy check
CSMA — Carrier sense multiple access
DCLK — Digital clock
DCU — Delay calibration unit
DVREG — Digital voltage regulator
ED — Energy detection
ESD — Electro static discharge
EVM — Error vector magnitude
FIFO — First in first out
FTN — Automatic filter tuning
GPIO — General purpose input output
LDO — Low-drop output
LNA — Low-noise amplifier
LO — Local oscillator
LQI — Link-quality indication
LSB — Least significant bit
MSB — Most significant bit
MSK — Minimum shift keying
O-QPSK — Offset-quadrature phase shift keying
PA — Power amplifier
PAN — Personal area network
PER — Packet error rate
PHY — Physical layer
PLL — Phase-locked loop
POR — Power-on reset
PPF — Poly-phase filter
PSDU — PHY service data unit
QFN — Quad flat no-lead package
RF — Radio frequency
RSSI — Received signal strength indicator
RX — Receiver
SFD — Start frame delimiter
SPI — Serial peripheral interface
SRAM — Static random access memory
TX — Transmitter
VCO — Voltage controlled oscillator
VREG — Voltage regulator
XOSC — Crystal oscillator
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AT86RF230
2. General Circuit Description
XTAL1
XTAL2
Digital DomainAnalog Domain
DCLK
TX BBP
RX BBPBPF
Control Logic/
Configuration
Registers
TRX Data
Buffer
DVREG
SPI
Slave
Interface
IRQ
SEL
MISO
SCLK
MOSI
CLKM
SLP_TR
RSTN
RFP
RFN
TX power
AVREG
BATMON
LNA PPF ADC
FTN
I
Q
control
PA
Frequency
Synthesis
Limiter
AGC
XOSC
TX Data
RSSI
5
Figure 2-1. Block Diagram of AT86RF230
This single-chip RF transceiver provides a complete radio interface between the antenna and the micro-controller.
It comprises the analog radio part, digital demodulation including time and frequency synchronization and data
buffering. The number of external components is minimized so that only the antenna, the crystal and four
decoupling capacitors are required. The bidirectional differential antenna pins are used in common for RX and TX,
so no external antenna switch is needed.
The transceiver block diagram is shown in Figure 2-1. The receiver path is based on a low-IF topology. The
channel filter consists of three single side-band active RC resonators forming a 2 MHz band-pass filter with a
Butterworth characteristic centered at 2 MHz. Two 1st-order high-pass filters were added to the signal path to
achieve capacitive coupling at the single side-band filter (SSBF) output to suppress DC offset and integrator
feedback at the limiter amplifier. The 3-stage limiter amplifier provides sufficient gain to overcome the DC offset of
the succeeding single channel ADC and generates a digital RSSI signal with 3 dB granularity. The low-IF signal is
sampled at 16 MHz with 1-bit resolution and applied to the digital signal processing part.
Direct VCO modulation is used to generate the transmit signal. The modulation scheme is offset-QPSK (O-QPSK)
with half-sine pulse shaping and 32-length block coding (spreading). This is equivalent to minimum shift keying
(MSK) when transforming the spreading code sequences appropriately. The modulation signal is applied to both
the VCO and the fractional-N PLL to ensure the coherent phase modulation required for demodulation as an OQPSK signal. The frequency-modulated LO signal is fed to the power amplifier.
Two on-chip low-dropout voltage regulators provide the analog and digital 1.8V supply. The SPI interface and the
control registers will retain their settings in SLEEP mode when the regulators are turned off. The RX and TX signal
processing paths are highly integrated and optimized for low power consumption.
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AT86RF230
3. Technical Parameters
3.1. Absolute Maximum Ratings
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of this specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.1.1 Storage temperature T
3.1.2 Lead temperature T
3.1.3 ESD-protection V
3.1.4 Input RF level P
3.1.5 Voltage on all pins (except
pins 13, 14, 29)
3.1.6 Voltage on pins 13, 14, 29 -0.3 2 V
stor
-50 150 °C
lead
ESD
260 °C T = 10s
2
kV
200
500
RF
+10 dBm
-0.3 Vdd+0.3
≤ 3.6
(soldering profile compliant with
IPC/JEDEC J-STD-020B)
Compl. to [2], passed 4 kV
V
Compl. to [3],
V
Compl. to [4], passed 750V
V
Table 3-1. Absolute Maximum Ratings
3.2. Recommended Operating Range
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.2.1 Operating temperature range T
3.2.2 Supply voltage V
op
dd
-40 +85 °C
1.8 3.6 V
Table 3-2. Operating Range
3.3. Digital Pin Specifications
Test Conditions (unless otherwise stated): T
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.3.1 High level input voltage VIH Vdd – 0.4
3.3.2 Low level input voltage V
3.3.3 High level output voltage V
3.3.4 Low level output voltage V
IL
OH
OL
amb
= 25°C
V
0.4 V
Vdd – 0.4
V For all output current loads
defined in register TRX_CTR_0
0.4 V For all output current loads
defined in register TRX_CTR_0
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No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.3.5 Controller clock frequency
(CLKM)
f
CLKM
0
1
2
4
8
16
MHz
MHz
MHz
MHz
MHz
MHz
Programmable in register
TRX_CTRL_0
Table 3-3. Digital Pin Specifications
The capacitive load should not be larger than 50 pF for all I/Os when using the default driver strength settings.
Generally, large load capacitances will increase the overall current consumption.
3.4. General RF Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, T
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.4.1 Frequency range f
3.4.2 Bit rate f
3.4.3 Chip rate f
3.4.4 Reference oscillator
frequency
3.4.5 Reference oscillator settling
time
3.4.6 Reference frequency
accuracy for correct
functionality
3.4.7 20 dB bandwidth B
bit
chip
f
clk
0.5 1 ms Leaving SLEEP state to clock
-60 +60 ppm
20dB
2405 2480 MHz
2.8 MHz
250 kbit/s As specified in [1]
2000 kchip/s As specified in [1]
16 MHz
amb
= 25°C, Measurement setup see Figure 9-1
available at pin CLKM
±40 ppm is required by [1]
Table 3-4: General RF Parameters
3.5. Transmitter Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, T
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.5.1 Nominal output power PTX 0 3 6 dBm Max. value
3.5.2 Output power range 20 dB 16 steps
3.5.3 Output power accuracy
3.5.4 TX Return loss 10 dB
3.5.5 EVM 8 %rms Channel number = 20
3.5.6 Harmonics
2nd harmonic
3rd harmonic
-38
-45
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amb
= 25°C, Measurement setup see Figure 9-1
(register PHY_TX_PWR)
±3
dB
100Ω differential impedance,
PTX = 3 dBm
dBm
dBm
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AT86RF230
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.5.7 Spurious emissions
30 – ≤1000 MHz
>1 – 12.75 GHz
1.8 – 1.9 GHz
5.15 – 5.3 GHz
-36
-30
-47
-47
Complies with
dBm
EN 300 440,
dBm
FCC-CFR-47 part 15,
dBm
ARIB STD-66,
dBm
RSS-210
Table 3-5. TX Parameters
3.6. Receiver Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, f = 2.45 GHz, T
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.6.1 Receiver sensitivity -101 dBm
3.6.2 Return loss 10 dB
3.6.3 Noise figure NF 6 dB
3.6.4 Maximum RX input level 10 dBm
3.6.5 Adjacent channel rejection
-5 MHz
3.6.6 Adjacent channel rejection
+5 MHz
3.6.7 Alternate adjacent channel
rejection -10 MHz
3.6.8 Alternate adjacent channel
rejection +10 MHz
3.6.9 Spurious emissions
LO leakage
30 – 1000 MHz
1 – 12.75 GHz
3.6.10 TX/RX carrier frequency
offset
3.6.11 3rd-order intercept point IIP3 -9 dB At maximum gain
3.6.12 2nd-order intercept point IIP2 24 dB At maximum gain
3.6.13 RSSI accuracy absolute -5 5 dB Tolerance within gain step
3.6.14 RSSI dynamic range 84 dB
3.6.15 RSSI resolution 3 dB
3.6.16 Minimum RSSI value 0 PRF < -91 dBm
3.6.17 Maximum RSSI value 28 PRF > -10 dBm
34 dBm
36 dBm
52 dBm
53 dBm
-75
-300 300 kHz Sensitivity loss < 2 dB
amb
= 25°C, Measurement setup see Figure 9-1
AWGN channel, PER≤1%,
PSDU length of 20 octets
100Ω differential impedance
PER ≤ 1%, PSDU length of
20 octets
PER ≤ 1%, PSDU length of
20 octets, PRF = -82 dBm
PER ≤ 1%, PSDU length of
20 octets, PRF = -82 dBm
PER ≤ 1%, PSDU length of
20 octets, PRF = -82 dBm
PER ≤ 1%, PSDU length of
20 octets, PRF = -82 dBm
-57
-47
dBm
dBm
dBm
Offset freq. interf. 1 = 5 MHz
Offset freq. interf. 2 = 10 MHz
Offset freq. interf. 1 = 60 MHz
Offset freq. interf. 2 = 62 MHz
Table 3-6. RX Parameters
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3.7. Current Consumption Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, T
Figure 9-1
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.7.1 Supply current transmit mode I
3.7.2 Supply current receive mode I
3.7.3 Supply current TRX_OFF
mode
3.7.4 Supply current SLEEP mode I
BUSY_TX
17
RX_ON
16 mA State: RX_ON
I
TRX_OFF
SLEEP
0.1
amb
= 25°C, CLKM = OFF, Measurement setup see
mA
15
13
10
mA
mA
mA
PTX = 3 dBm
PTX = 1 dBm
PTX = -3 dBm
PTX = -17 dBm
(the current consumption will be
reduced by approx. 2 mA at
Vdd = 1.8V for each output
power level)
1.7 mA State: TRX_OFF
State: SLEEP
µA
Table 3-7. Current Consumption
3.8. SPI Timing Specifications
Test Conditions (unless otherwise stated): Vdd = 3V, T
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.8.1 SCLK frequency
8 MHz
(synchronous)
3.8.2 SCLK frequency
7.5 MHz
(asynchronous)
3.8.3
SEL low to MISO active
t1 180 ns
3.8.4 SCLK to MISO out t2 48 ns data hold time
3.8.5 MOSI setup time t3 10 ns
3.8.6 MOSI hold time t4 10 ns
3.8.7 LSB last byte to MSB next
t5 250 ns
byte
3.8.8
SEL high to MISO tristate
t6 10 ns
3.8.9 SLP_TR pulse width t7 65 ns
Table 3-8. SPI Timing Parameters (see Figure 7-2)
amb
= 25°C
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3.9. Crystal Parameter Specifications
No Parameter Symbol Min Typ Max Unit Conditions/Notes
3.9.1 Crystal frequency f0 16 MHz
3.9.2 Load capacitance CL 8 14 pF
3.9.3 Static capacitance C0 7 pF
3.9.4 Series resistance R1 100
Table 3-9. Crystal Parameter Specifications
Ω
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4. Basic Operating Modes
This section summarizes all features that are needed to provide the basic functionality of a transceiver system,
such as receiving and transmitting frames, and powering down. These basic operating modes are sufficient for
ZigBee applications and are shown in Figure 4-1.
BUSY_RX
(Receive Mode)
CLKM=ON
Start
Frame
RX_ON_NOCLK
(Rx Listen Mode)
CLKM=OFF
P_ON
(Power-on after VDD)
XOSC=ON
Pull=ON
FORCE_TRX_OFF
(all modes except SLEEP)
6
Frame
Start
Frame
End
S
P
L
RX_ON
(Rx Listen Mode)
CLKM=ON
1
=
R
T
0
_
=
R
T
_
P
L
S
T
R
X
_
O
F
F
1
N
O
TRX_OFF
(Clock Mode)
F
F
O
_
X
R
T
8
XOSC=ON
Pull=OFF
RX_ON
PLL_ON
12
_
X
R
R
T
_
P
L
S
2
57
T
R
X
_
O
F
9
SLEEP
(Sleep Mode)
XOSC=OFF
Pull=OFF
0
=
P
L
S
P
F
3
1
=
R
T
_
13
RST=0
(all modes except P_ON)
L
L
_
O
N
4
PLL_ON
(PLL Mode)
Legend:
Blue: SPI Write to Register TRX_STATE (0x02)
Red: Control signals via IC Pin
Green: Event
Figure 4-1. Basic Operating Modes State Diagram
Frame
11
End
10
TX_START
SLP_TR=1
BUSY_TX
(Transmit Mode)
4.1. Configuration
The operating modes are controlled by two signal pins and the SPI access to register 0x02 (TRX_STATE). The
successful state change can be confirmed by reading the transceiver state from register 0x01 (TRX_STATUS).
The pin SLP_TR is used to enter SLEEP mode where current consumption is minimal (leakage current only) and to
wake-up the transceiver.
The pin
P_ON mode.
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RST
provides a reset of all registers and forces the transceiver into TRX_OFF mode, if the IC is not in the
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AT86RF230
The state change commands FORCE_TRX_OFF and TRX_OFF both lead to a transition into TRX_OFF state. If
the transceiver is in the BUSY_RX or BUSY_TX state, the command FORCE_TRX_OFF interrupts the active
receiving or transmitting process, and forces an immediate transition. On the other hand, a TRX_OFF command is
stored until a frame currently being received or transmitted is finished. After the end of the frame, the transition to
TRX_OFF is performed.
4.2. Basic Operating Mode Description
4.2.1. P_ON
When the external supply voltage (VDD) is first supplied to the transceiver IC, the system is in the P_ON (Poweron) mode. In this mode, the crystal oscillator is activated and the master clock for the controller is provided at the
CLKM pin after a delay of 128µs to ensure a steady state of the crystal oscillator.
All digital inputs have pull-up or pull-down resistors (see Table 10-3). This is necessary to support controllers where
GPIO signals are undefined after reset. The input pull-up and pull-down resistors are disabled when the transceiver
leaves the P_ON state.
A valid SPI write access to the register TRX_STATE with the values TRX_OFF or FORCE_TRX_OFF is necessary
to leave the P_ON state.
Prior to leaving P_ON, the controller must set the pins to the default operating values: SLP_TR = 0 and
An on-chip power-on-reset sets the all register to its default values. A dedicated reset signal from the controller at
the pin
RST
is not necessary, but recommended for HW/SW synchronization reasons.
1RST =
.
4.2.2. SLEEP
In SLEEP mode, the entire transceiver IC is disabled. No circuitry is running. The current consumption in this mode
is leakage current only. This mode can only be entered from state TRX_OFF, when the pin SLP_TR is set to “1”.
There is no way to switch the transceiver to SLEEP mode via SPI register access.
Leaving this state is possible in two ways:
Setting the SLP_TR pin to “0” returns the transceiver to the TRX_OFF mode without resetting any registers. Using
0RST =
resets the SPI and configuration registers to their default values and forces the IC into the TRX_OFF
mode.
4.2.3. TRX_OFF
The TRX_OFF mode provides the master clock for the controller in synchronous operation mode, allowing the
software to run without the need for the radio to be powered on. The pins SLP_TR and
control.
In this mode, the SPI interface and crystal oscillator are active. The voltage regulator is enabled and provides 1.8V
to the digital core for have access to the frame data buffers.
The transition from P_ON to TRX_OFF mode is described in section 4.2.1.
RST
are enabled for mode
4.2.4. PLL_ON
Entering the PLL_ON mode from TRX_OFF will first enable the analog voltage regulator. After the voltage regulator
has settled, the PLL frequency synthesizer is enabled. When the PLL has settled at the receive frequency, a
successful PLL lock is indicated by an interrupt request at the IRQ pin.
During PLL_ON mode, the command RX_ON via register 0x02 (TRX_STATE) sets the transceiver to RX_ON
mode, even if the PLL is not yet settled.
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AT86RF230
4.2.5. RX_ON and BUSY_RX
The RX_ON mode enables the analog and digital receiver blocks and the PLL frequency synthesizer. The
transition from TRX_OFF mode to RX_ON mode is started by setting the TRX_STATE to RX_ON via a SPI write
access to register 0x02 (TRX_STATE).
The receive mode is internally divided into RX_ON mode and BUSY_RX mode. There is no difference between the
modes with respect to the analog radio part. During RX_ON mode, only the preamble detection of the digital signal
processing is running. When a preamble is detected, the digital receiver is turned on, switching to the BUSY_RX
mode.
SLP_TR = 1 is only evaluated in RX_ON mode. When receiving a frame in BUSY_RX mode, the SLP_TR pin has
no effect.
4.2.6. RX_ON_NOCLK
If the radio is listening for an incoming frame and the controller is not running an application, the controller can be
powered down to decrease the total system power consumption. This special power-down scenario for controllers
running in synchronous mode is supported by the AT86RF230 using the state RX_ON_NOCLK.
This state can only be entered by setting SLP_TR = 1 while the IC is in the RX_ON mode. The CLKM pin will then
be disabled 35 clock cycles after the rising edge at the SLP_TR pin. This will enable the controller to complete its
power-down sequence. The reception of a frame is signalized to the controller by a RX_START IRQ (see Figure
7-13). The clock CLKM is turned on once again and the transceiver enters the BUSY_RX state.
The end of the transaction is signaled to the controller by an TRX_END interrupt. After the transaction has been
completed, the transceiver will enter the RX_ON state. The transceiver will only re-enter the RX_ON_NOCLK state
when the SLP_TR has been reset to “0”, and afterwards set to “1” again.
If the transceiver is in the RX_ON_NOCLK state, and the SLP_TR pin is reset to “0”, it will enter the RX _ON state,
and it will again start to supply the micro-controller with the clock signal.
4.2.7. BUSY_TX
Transmitting can only be started from PLL_ON mode. There are two ways to start transmitting: using pin
SLP_TR = 1 or SPI command TX_START in register 0x02 (TRX_STATE). Either of these will cause the IC to enter
BUSY_TX mode.
During the transition to BUSY_TX mode, the PLL frequency shifts 1.5 MHz to enable the different LO frequencies
needed between receive and transmit modes. Transmission of the first data chip of the preamble is delayed by
16 µs to allow PLL settling and PA ramping.
When the end of the frame has been transmitted, the IC will automatically turn off the power amplifier and transition
from the BUSY_TX mode to the PLL_ON mode. The PLL settles to the receiver LO frequency (-1.5 MHz frequency
step).
If the frame transmission was initiated by setting the pin SLP_TR to “1”, a new transmission will only be started
when the pin SLP_TR has been reset to “0” and afterwards to set to “1” again.
4.3. Basic Mode Timing
The following paragraphs depict the method of switching from one mode to another.
4.3.1. Wake-up Procedure
The wake-up procedure from SLEEP mode is shown in Figure 4-2.
Deasserting the pin SLP_TR enables the crystal oscillator. After approximately 0.3 - 0.5 ms, the internal clock
signal is available. After 128 µs the clock signal is delivered at the CLKM pin providing the master clock to the
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micro-controller. An additional 256 µs timer ensures that frequency stability is sufficient to drive filter tuning (FTN)
and the PLL. After band-gap voltage and digital voltage regulator settling, the transceiver enters the TRX_OFF
state and waits for further commands.
Signals/Events
Active Blocks
Command
Pin
0 600500 700
XOSC
SLP_TR=0
P_ON
XOSC
VDD on
~400
XOSC delivers
clock
µµµµ
Timer 128 s
CLKM_CTRL
CLKM delivers
clock
TRX_OFF
µµµµµµµµ
RST=0
800 900 1000 1100
Clock
stable
FTN BG DVREG AVREG
TRX_OFFState PLL_ON
PLL_ON,
RX_ON
16
PLLTimer 256 sTimer 128 s
µµµµ
s
RX_ON
Typical block settling time, stays on
Block active
waiting for SPI commands
RX_ONSLEEP
Time [µs]
IRQ
PLL locked
Time [µs]
Figure 4-2. Wake-up Procedure from SLEEP Mode and P_ON Mode to RX_ON Mode (PLL locked)
Forcing PLL_ON mode or RX_ON mode initiates a ramp-up sequence of the analog voltage regulator followed by a
16 µs timer. This timer makes sure that the analog 1.8V supply is stabilized before enabling PLL circuitry. RX_ON
mode can be forced any time during PLL_ON mode regardless of the PLL lock signal.
When the wake-up sequence is started from P_ON mode (VDD first applied to the IC) the state machine will stop
after the 128 µs timer to wait for a valid TRX_OFF command from the micro-controller. The default CLKM
frequency value in P_ON mode is 1 MHz. At this rate, an SPI access requires approximately 38 µs. The SPI
programming in synchronous mode can be speeded up by setting the frequency of the clock output at pin CLKM in
register 0x03 (TRX_CTRL_0) to the maximum value allowed.
If a chip reset with
0RST =
is generated, the sequence starts with filter tuning (FTN) as indicated in Figure 4-2.
4.3.2. Transition from PLL_ON via BUSY_TX to RX_ON
0 10 16
BUSY_TXPLL_ON
State
Active Blocks
Command
Pin
TX
PLL settling to Tx frequency
SLP_TR=0
START
_
µµµµ
Timer 14 2
PLL
s
Figure 4-3. Switching from TX to RX
The time scale in Figure 4-3 is relative to TX frame start.
PA
ramp
µµµµ
s
Typical block settling time, stays on
Block active
waiting for SPI commands
Transmitting frame
x
PLL_ON
RX_ON
PLL settling to Rx frequency
Timer 32
PLL
RX_ON
x+32
Time [µs]
s
µµµµ
Time [µs]
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4.3.3. State Transition Timing
The transition numbers correspond to Figure 4-1 and do not include SPI access time if not otherwise stated. See
measurement setup in Figure 9-1.
No Transition
1
P_ON → TRX_OFF
2
SLEEP → TRX_OFF
3
TRX_OFF → SLEEP
4
TRX_OFF → PLL_ON
5
PLL_ON → TRX_OFF
6
TRX_OFF → RX_ON
7
RX_ON → TRX_OFF
8
PLL_ON → RX_ON
9
RX_ON → PLL_ON
10
PLL_ON → BUSY_TX
11
BUSY_TX → PLL_ON
12
All modes → TRX_OFF
13
0RST = → TRX_OFF
Time [µµµµs]
(typical)
1880 Internal power-on reset, including 1000 µs for controller access,
880 Depends on external block capacitor at VDEC1 (1 µF nom) and
35 35 cycles of 1 MHz clock assumed.
180 Depends on external block capacitor at VDEC2 (1 µF nom).
1
180
1
1
1
16 Asserting SLP_TR pin
32
1 Using TRX_CMD FORCE_TRX_OFF (see register 0x02), not
120 Depends on external block capacitor at VDEC1 (1 µF nom), not
Comments
depends on external block capacitor at VDEC1 (1 µF nom) and
crystal oscillator setup (CL = 10 pf)
crystal oscillator setup (CL = 10 pf)
valid for SLEEP mode
valid for P_ON mode
Table 4-1. State Transition Timing
The state transition timing is calculated based on the timing of the single blocks shown in Figure 4-2. The worst
case values include maximum operating temperature, minimum supply voltage, and device parameter variations.
Block
XOSC 500 1000 Depends on crystal Q factor and load capacitor.
DVREG 60 1000 Depends on external block capacitor at VDEC1
AVREG 60 1000 Depends on external block capacitor at VDEC2
PLL, initial 100 150
PLL, RX → TX
PLL, TX → RX
Time [
(typical)
µµµµ
s]
Time [
µµµµ
s]
(worst case)
16
32
Comments
(CB3 = 1 µF nom., 10 µF worst case).
(CB1 = 1 µF nom., 10 µF worst case).
Table 4-2. Block Timing
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