ATMEL AT 86 RF 210 Service Manual

www.DataSheet4U.com

Features

•

850–930 MHz Output Frequency

•

Rx Current: 14.5 mA

•

Low Sleep Mode Current: 1 uA

•

DSSS Processing and BPSK Modulation/Demodulation

•

Battery Voltage Monitoring Circuitry

•

4 mW (6 dBm) Min. Transmit Power @ Vdd = 1.8V

•

Serial Peripheral Interface (SPI) Control

•

Power Supply Voltage Operating Range: 1.8V to 3.6V

•

Low External Component Count

•

48QFN Package

Applications

•

Low Band IEEE 802.15.4/ZigBee™-based Systems

•

Industrial, Commercial, Home Lighting Control, Security, and HVAC

•

Inventory Management

•

Health Monitoring

•

Wireless PC Peripherals such as Mouse, Keyboard, and Joystick

•

Consumer Electronics Remote Controls and Toys

Description

The Atmel AT86RF210 Z-Link™ Transceiver is a fully integated, low-cost ZigBee
transceiver cap able of transmitting and receiving B PSK modulated digital data over a
frequency range of 868 MHz and 902–928 MHz using a minimum number of external
components. It combines excellent RF performance with low cost, small size and low
current consumpt ion . The AT86RF210 includes a c r ystal st abilized Fractional-N s yn­thesizer, BPSK transmitter and receiver, and full Direct Sequence Sp read Spectrum
Signal (DSSS) processing, including spreading and despreading. The device is fully
compatable with IEEE 802.15.4 and ZigBee standards. It includes internal voltage
regulation and battery monitoring circuitr y and requires a minimum number of external
support components.

™

AT86RF210
Z-Link

™

Transceiver

868/902–928 MHz
Direct Sequence
Spread Spectrum
BPSK Transceiver

Preliminary

Figure 1. Block D iagram

Rx In

Sw Out

Ant In

Sw In

Tx Out

Low Noise

Amp

T/R Switch

Power Amp

I/Q Mixer

IF Amp

X

Polyphase

Filter

Synthesizer

Modulator

Demodulator

Despreader

Spreader

Data In

SPI Bus

Data Out

SDO

SDI
SCLK

SEL

5033AS–WIRE–10/03

Figure 1. Functional Block Diagram

SUB

LNAIN

LNAVSS

RSWOUT

VSS

ANT

VSS

TSWIN

VSS

PA OUT

VSS

TR

SW

PA

Regulator

LNAOUT

LNA

PA

GND

FSK

TUNE LOGIC

Fine

Atten

BPSKO

OK

MOD

VDDA

VSSA

/2

with

Buffers

FROM TXD

Spreader

VCO
Fcx2

Cap

Array

VDDD

VSSD

Reg Filter

Lim/PPF DC DIST

Image

P
P
F
M
U
X
1

Reject

Filter

1.200 MHz

bandwidth

Control

PPF

AUTOCAL

Circuit

P
P
F
M
U
X
2

DC DIST/BG/PTAT with

main BandGAP

/N-M

SDMOD

Tune W ord

Charge

Pump

PRGM

DIV

Coarse

Lock/Lock

Detect

Phase

Detector

VDD

DBLR

RSSI

IQ-Limiter Strip

1.2 MHz

Low

Voltage

Detect

Clock

Distribution

Xstal Osc

S
T
A
T
U
S

TEST

POR

Despreader

BPSK

Demod

Mode
Logic

Serial

Configruation

Register

RXD

CCA

START

TXD

NC

CHP_RDY

RESET_

RX

TX

CLK

SEL

SCL
SDO

PAREG

VCOREG

VCO

NC

NC

VCO
VSS

VCO

TUNE

CPVCO

CPOUT

XTALGND

XTAL1

XTAL2

SDI

Table 1. Absolute Maximum Ratings*

Storage Temperature ..............................................−65 to +150

Maximum Input Voltage...........................................VDD + 0.5V

Maximum Operating Voltage (VDD ) ................................... 4,5

*NOTE: Stresses beyond those listed in this table may cause per-

manent damage to the device. This is a stress rating
only; functional operation of the device at these or any
other co ndit ions beyond thos e indic ate d in the op era­tion al sec t io ns of the specification is not implied.
Exposure to the absolute maximum rating conditions for
extended periods may affect device reliability.

Table 2. Operating Conditions

Symbol Parameter Min Typ Max Unit

TAMB Operating temperature −40 85 °C
VSUPPLY Voltage supply range 1.8 2.7 3.6 V
HUMIDITY Humidity 10 90 %

Note: Unit operation is guaranteed by design when operating within these ranges.

2

AT86RF210

5033AS–WIRE–10/03

AT86RF210

Table 3. DC Characteristics

Symbol Parameter Min Typ Max Unit

IDDRX Supply current, receive mode 14.5 mA
IDDTX Supply current, transmit mode VDD = 3.3V 60 mA
IDDSleep Supply current, sleep mode 1 uA
VPOR Power-on reset voltage 1.5 V
VIH Digita l i nput voltage high 0.7*VDD V
VIL Digital i nput voltage low 0.3*VDD V
VOH Digital output voltage high 0.7*VDD V
VOL Digital output voltage low 0.3*VDD V

Table 4. Receiver AC Characteristics

Symbol Parameter Min Typ Max Unit

FLO Local oscillator opera ting range, external

inductor
ZRF Port impedance antenna input 50 Ohm
Rx Sens Sensitiv i ty, PER = 1% 4 0 kB/s, BW = 600 kHz

BPSK modulation
Rx NF Receiver noise figure 6.0 dB
Rx P1dB Receiver input 1dB compression point LNA

gain max setting
Rx IP3 Input IP3 −30 dBm
Rx LO Leakage Receiver LO leakage (all possible paths) −80 dBm
Pin Maximum input signal; LNA gain min setting −20 dBm
EDthresh Default energy detection threshold

(programmable)
Ttx/rx Turnaround time, trans mit to receive 100 usec
Trx/tx Turnaround time, receive to transmit 100 usec
RJAMadj Receiver relative jamming resistance adjacent

channel (desired signal = −89 dBm)
RJAMalt Receiv er r elativ e jam ming res istanc e alternate

channel (desired signal = −89 dBm)
IFCF IF center frequency 1.2 MHz

850 930 MHz

−95 dBm

−40 dBm

−84 dBm

0dB

30 dB

IFBW IF bandwidth 600 KHz
Imreg IF image rejection −35 dB
RX IFS/N RX IF SNR (600 KHz BW) Min input signal =

−100 dBm
Rx DR Receiver max data rate 40 Kb/s
RSSI GN RSSI Gai n 1.0 uA/dB
RSSI RG RSSI RANGE −105 −30 dBm

5033AS–WIRE–10/03

10 dB

3