ATMEL AT83SND1C, AT89C51SND1C, AT80C51SND1C User Manual

查询AT80C51SND1C-7HTIL供应商

1. Features

• MPEG I/II-Layer 3 Hardwired Decoder

– Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control

using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – CRC Error and MPEG Frame Synchronization Indicators

• Programmable Audio Output for Interfacing with Common Audio DAC

– PCM Format Compatible –I2S Format Compatible

• 8-bit MCU C51 Core Based (F

• 2304 Bytes of Internal RAM

• 64K Bytes of Code Memory

– AT89C51SND1C: Flash (100K Erase/Write Cycles) – AT83SND1C: ROM

• 4K Bytes of Boot Flash Memory (AT89C51SND1C)

– ISP: Download from USB (standard) or UART (option)

• External Code Memory

– AT80C51SND1C: ROMless

• USB Rev 1.1 Controller

– Full Speed Data Transmission

• Built-in PLL

– MP3 Audio Clocks –USB Clock

• MultiMedia Card

• Atmel DataFlash

• IDE/ATAPI Interface

• 2 Channels 10-bit ADC, 8 kHz (8-true bit)

– Battery V ol tage Monitoring – Voice Recording Controlled by Software

• Up to 44 Bits of General-purpose I/Os

– 4-bit Interrupt Keyboard Port for a 4 x n Matrix –SmartMedia® Software Interface

• 2 Standard 16-bit Timers/Counters

• Hardware Watchdog Timer

• Standard Full Duplex UART with Baud Rate Generator

• Two Wire Master and Slave Modes Controller

• SPI Master and Slave Modes Controller

• Power Management

– Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode

• Operating Conditions:

–3V, ±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°C to +85 °C

• Packages

– TQFP80, BGA81, PLCC84 (Development Board) –Dice

Interface Compatibility

SPI Interface Compatibility

= 20 MHz)

MAX

Single-Chip Flash Microcontroller with MP3 Decoder and Human Interface

AT83SND1C AT89C51SND1C AT80C51SND1C

Rev. 4109H–8051–01/05

AT8xC51SND1C

2. Description The AT8xC51SND1C a re fully in tegrated sta nd-alone har dwired MPEG I/II-Layer 3

decoder with a C51 microcontroller core handling data flow and MP3-player control. The AT89C51SND1C includes 64K Bytes of Flash memory and allows In-System Pro-

gramming through an embedded 4K Bytes of Boot Flash memory. The AT83SND1C includes 64K Bytes of ROM memory. The AT80C51SND1C does not include any code memory. The AT8xC51SND1C include 2304 Bytes of RAM memory. The AT8xC51SND1C provides the necessary features for human interface like timers,

keyboard port, serial or parallel interface (USB, TWI, SPI, IDE), ADC input, I and all external memory interface (NAND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).

3. Typical Applications

•MP3-Player

• PDA, Camera, Mobile Phone MP3

• Car Audio/Multimedia MP3

• Home Audio/Multimedia MP3

4. Block Diagram

Figure 1. AT8xC51SND1C Block Diagram

INT0 INT1 MOSIMISO

Interrupt

Handler Unit

VSSVDD

RAM

2304 Bytes

UVSSUVDD

AVSSAVDD

Flash ROM

64 KBytes

Flash Boot

4 KBytes

AIN1:0

AREF

10-bit A to D

Converter

S output,

SCK

RXDTXD

33 33444411

UART

and

BRG

T1T0

Timers 0/1

Watchdog

SPI/DataFlash

Controller

SCL SDA

TWI

Controller

C51 (X2 Core)

Clock and PLL

Unit

FILT X2X1

RST

MP3 Decoder

Unit

ISP

ALE

Audio Interface

8-Bit Internal Bus

I2S/PCM

DSELDCLK SCLKDOUT

USB

Controller

D+ D-

MCLK

MMC

Interface

MDAT

MCMD

Keyboard

Interface

KIN3:0

I/O

Ports

IDE

Interface

P0-P5

1 Alternate function of Port 1 3 Alternate function of Port 3 4 Alternate function of Port 4

4109H–8051–01/05

5. Pin Description

0 1 2

5.1 Pinouts

Figure 1. AT8xC51SND1C 80-pin QFP Package

ALE

/PSEN2/NC

ISP

P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3

P1.4 P1.5

P1.6/SCL

P1.7/SDA

VDD

PVDD

FILT

PVSS

VSS

X2 X1

TST

UVDD

UVSS

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

P0.3/AD3

P0.4/AD4

P0.5/AD5

VSS

VDD

717069

P0.6/AD6

P5.1

P5.0

P0.0/AD0

P0.1/AD1

P0.2/AD2

AT89C51SND1C-RO (FLASH)

AT83SND1C-RO (ROM)

AT80C51SND1C-RO (ROMLESS)

AT8xC51SND1C

P0.7/AD7

P4.3/SS

P4.2/SCK

P4.1/MOSI

P4.0/MISO

P2.0/A8

P2.1/A9

P4.7

P4.6

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P4.5 P4.4 P2.2/A1 P2.3/A1 P2.4/A1 P2.5/A1 P2.6/A1 P2.7/A1 VSS VDD MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS VDD

4109H–8051–01/05

21222324252627

D-

D+

VSS

VDD

P3.0/RXD

Notes: 1. ISP pin is only available in AT89C51SND1C product.

Do not connect this pin on AT83SND1C product.

2. PSEN pin is only available in AT80C51SND1C product.

302932

P3.4/T0

P3.3/INT1

P3.5/T1

P3.1/TXD

P3.2/INT0

P3.6/WR

34353637383940

AVSS

AVDD

P3.7/RD

P5.3

P5.2

AIN1

AIN0

AREFP

AREFN

AT8xC51SND1C

Figure 2. AT8xC51SND1C 81-pin BGA Package

P4.6

P4.4

P2.5/

A13

P2.4/

A12

VDD

RST

DSEL

DCLK

89765432

P2.0/

P4.7

P2.2/

P2.6/

A14

P2.3/

A11

MCMD

SCLK

VSS

P4.0/

MISO SCK AD2

P4.1/

MOSI

P2.1/

A9A10

P4.5

VSS

MCLK

DOUT

AIN1

P4.2/

P4.3/

P0.6

P0.7/

AD7 AD5

P2.7/

A15

MDAT

P5.3

AVSS

VDD

P0.1/

VSS

P0.5/

AVDD

P3.7/

AIN0

P0.2/

P0.4/

AD4 AD0AD1

P5.1

P1.6/

SCL SDA

FILT

P3.4/

P3.5/

P3.3/

INT1

P0.3/

AD3A8

P0.0/

P1.0/ KIN0

P1.7/

PVDD

UVSS

VDD

P3.1/

TXD

P5.0

ISP

PSEN

P1.3/ KIN3

P1.5

PVSS

TST

D-

ALE

P1.1

P1.2/ KIN2

P1.4

VDD

VSS

UVDD

VDD

P5.2

AREFP

AREFN

P3.6/

P3.2/

INT0

P3.0/

RXD

Notes: 1. ISP pin is only available in AT89C51SND1C product.

Do not connect this pin on AT83SND1C and AT80C51SND1C product.

2. PSEN

pin is only available in AT80C51SND1C product.

VSS

D+

4109H–8051–01/05

Figure 3. AT8xC51SND1C 84-pin PLCC Package

AT8xC51SND1C

ALE

ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3

P1.4 P1.5

P1.6/SCL

P1.7/SDA

VDD

PAVDD

FILT

PAVSS

VSS

TST

UVDD

UVSS

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

3334353637

P5.1

P0.3/AD3

P0.4/AD4

P0.5/AD5

VSS

VDD

P0.2/AD2

P0.1/AD1

P5.0

P0.0/AD0

432

P0.6/AD6

84838281807978

AT89C51SND1C-SR (FLASH)

3839404142

444546474849505152

P4.3/SS

P0.7/AD7

P4.2/SCK

P2.0/A8

P4.0/MISO

P2.1/A9

P4.7

P4.6

74 73

P4.5

7271P4.4

P2.2/A10

P2.3/A11

P2.4/A12

P2.5/A13

P2.6/A14

P2.7/A15

VSS

VDD MCLK

MDAT

MCMD

61 60

RST

SCLK

DSEL

DCLK

DOUT

VSS

VDD

P4.1/MOSI

D+

D-

VSS

VDD

P3.4/T0

P3.5/T1

P3.0/RXD

P3.1/TXD

P3.3/INT1

P3.2/INT0

P3.6/WR

P3.7/RD

AVSS

AVDD

AREFP

AIN1

AIN0

AREFN

P5.2

P5.3

4109H–8051–01/05

AT8xC51SND1C

5.2 Signals All the AT8xC51SND1C signals are detailed by functionality in Table 3 to Table 16.

Table 3. Ports Signal Description

Signal

Name Type Description

Port 0

P0.7:0 I/O

P1.7:0 I/O

P2.7:0 I/O

P3.7:0 I/O

P4.7:0 I/O

P0 is an 8-bit open-drain bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high impedance inputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to V

Port 1

P1 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 2

P2 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 3

P3 is an 8-bit bidirectional I/O port with internal pull-ups.

Port 4

P4 is an 8-bit bidirectional I/O port with internal pull-ups.

Alternate

Function

AD7:0

or VSS.

KIN3:0

SCL SDA

A15:8

RXD TXD

INT0 INT1

T0 T1

MISO MOSI

SCK

P5.3:0 I/O

Port 5

P5 is a 4-bit bidirectional I/O port with internal pull-ups.

Table 4. Cloc k Si gna l Desc r ipt ion

Signal

Name Type Description

Input to the on-chip inverting oscillator amplifier

X1 I

X2 O

FILT I

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1 is the clock source for internal timing.

Output of the on-chip inverting oscillator amplifier

To use the internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected.

PLL Low Pass Filter input

FILT receives the RC network of the PLL low pass filter.

Alternate

Function

4109H–8051–01/05

Table 5. Timer 0 and Timer 1 Signal Description

AT8xC51SND1C

Signal

Name Type Description

Timer 0 Gate Input

serves as external run control for timer 0, when selected by

INT0 GATE0 bit in TCON register.

INT0

INT1

T0 I

T1 I

External Interrupt 0

input sets IE0 in the TCON register. If bit IT0 in this register is set,

INT0 bit IE0 is set by a falling edge on INT0 by a low level on INT0

Timer 1 Gate Input

serves as external run control for timer 1, when selected by

INT1 GATE1 bit in TCON register.

External Interrupt 1

INT1

input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1 by a low level on INT1

Timer 0 External Clock Input

When timer 0 operates as a counter, a falling edge on the T0 pin increments the count.

Timer 1 External Clock Input

When timer 1 operates as a counter, a falling edge on the T1 pin increments the count.

Table 6. Audio Interface Signal Description

Alternate

Function

P3.2

. If bit IT0 is cleared, bit IE0 is set

P3.3

. If bit IT1 is cleared, bit IE1 is set

P3.4

P3.5

Signal

Name Type Description

DCLK O DAC Data Bit Clock -

DOUT O DAC Audio Data -

DSEL O

SCLK O

DAC Channel Select Signal

DSEL is the sample rate clock output.

DAC System Clock

SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL).

Table 7. USB Controller Signal Description

Signal

Name Type Description

D+ I/O

D- I/O USB Negative Data Upstream Port -

USB Positive Data Upstream Port

This pin requires an external 1.5 KΩ pull-up to V operation.

for full speed

Alternate

Function

Alternate

Function

4109H–8051–01/05

AT8xC51SND1C

Table 8. MutiMediaCard Interface Signal Description

Signal

Name Type Description

MCLK O

MCMD I/O

MDAT I/O

MMC Clock output

Data or command clock transfer.

MMC Command line

Bidirectional command channel used for card initialization and data transfer commands. To avoid any parasitic current consumption, unused MCMD input must be polarized to V

MMC Data line

Bidirectional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to V

Table 9. UART Signal Description

Signal

Name Type Description

Receive Serial Data

RXD I/O

TXD O

RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3.

Transmit Serial Data

TXD outputs the shift clock in serial I/O mode 0 and transmits data in serial I/O modes 1, 2 and 3.

or VSS.

Alternate

Function

or VSS.

Alternate

Function

P3.0

P3.1

Table 10. SPI Controller Signal Description

Signal

Name Type Description

MISO I/O

MOSI I/O

SCK I/O

SPI Master Input Slave Output Data Line

When in master mode, MISO receives data from the slave peripheral. When in slave mode, MISO outputs data to the master controller.

SPI Master Output Slave Input Data Line

When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller.

SPI Clock Line

When in master mode, SCK outputs clock to the slave peripheral. When in slave mode, SCK receives clock from the master controller.

SPI Slave Select Line

When in controlled slave mode, SS

Table 11. TWI Controller Signal Description

Signal

Name Type Description

TWI Serial Clock

SCL I/O

When TWI controller is in master mode, SCL outputs the serial clock to the slave peripherals. When TWI controller is in slave mode, SCL receives clock from the master controller.

enables the slave mode.

Alternate

Function

P4.0

P4.1

P4.2

P4.3

Alternate

Function

P1.6

SDA I/O

TWI Serial Data

SDA is the bidirectional Two Wire data line.

P1.7

4109H–8051–01/05

Table 12. A/D Converter Signal Description

AT8xC51SND1C

Signal

Name Type Description

AIN1:0 I A/D Converter Analog Inputs -

AREFP I Analog Positive Voltage Reference Input -

AREFN I

Analog Negative Voltage Reference Input

This pin is internally connected to AVSS.

Table 13. Keypad Interface Signal Description

Signal

Name Type Description

KIN3:0 I

Keypad Input Lines

Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt.

Table 14. External Access Signal Description

Signal

Name Type Description

Address Lines

A15:8 I/O

Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface.

Alternate

Function

Alternate

Function

P1.3:0

Alternate

Function

P2.7:0

AD7:0 I/O

ALE O

PSEN

ISP

(1)(2)

Address/Data Lines

Multiplexed lower address and data lines for the external memory or the IDE interface.

Address Latch Enable Output

ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus.

Program Store Enable Output (AT80C51SND1C Only)

I/O

This signal is active low during external code fetch or external code read (MOVC instruction).

ISP Enable Input (AT89C51SND1C Only)

I/O

This signal must be held to GND through a pull-down resistor at the falling reset to force execution of the internal bootloader.

Read Signal

Read signal asserted during external data memory read operation.

Write Signal

Write signal asserted during external data memory write operation.

External Access Enable (Dice Only)

EA must be externally held low to enable the device to fetch code from external program memory locations 0000h to FFFFh.

Notes: 1. For ROM/Flash Dice product versions: pad EA must be connected to VCC.

2. For ROMl ess Dice product versions: pad EA

must be connected to VSS.

P0.7:0

P3.7

P3.6

4109H–8051–01/05

AT8xC51SND1C

Table 15. System Signal Description

Signal

Name Type Description

Reset Input

Holding this pin high for 64 oscillator periods while the oscillator is running resets the device. The Port pins are driven to their reset conditions when a voltage lower than V

RST I

TST

oscillator is running. This pin has an internal pull-down resistor which allows the device to be reset by connecting a capacitor between this pin and V Asserting RST when the chip is in Idle mode or Power-Down mode returns the chip to normal operation.

Test Input

Tes t mode entry signal. This pin must be set to V

Table 16. Power Signal Description

Signal

Name Type Description

VDD PWR

VSS GND

AVDD PWR

Digital Supply Voltage

Connect these pins to +3V supply voltage.

Circuit Ground

Connect these pins to ground.

Analog Supply Voltage

Connect this pin to +3V supply voltage.

is applied, whether or not the

Alternate

Function

Alternate

Function

AVSS GND

PVDD PWR

PVSS GND

UVDD PWR

UVSS GND

Analog Ground

Connect this pin to ground.

PLL Supply voltage

Connect this pin to +3V supply voltage.

PLL Circuit Ground

Connect this pin to ground.

USB Supply Voltage

Connect this pin to +3V supply voltage.

USB Ground

Connect this pin to ground.

4109H–8051–01/05

AT8xC51SND1C

VSS

VDD

5.17 Internal Pin Structure

Table 18. Detailed Internal Pin Structure

(1)

Circuit

VDD

TST

Watchdog Output

VDD VDD

VSS

Latch Output

2 osc

periods

Type Pins

Input TST

Input/Output RST

RST

VDD

(2)

Input/Output

P1 P2

(3)

P3 P4

P53:0

VDD

Input/Output

VSS

VDD

MCMD

MDAT

ISP

PSEN

ALE

SCLK

VSS

D+

Output

Input/Output

DCLK

DOUT

DSEL MCLK

D+ D-

D-

Notes: 1. For information on resistors value, input/output levels, and drive capability, refer to

the Section “DC Characteristics”, page 184.

2. When the Two Wire controller is enabled, P

, P2, and P3 transistors are disabled

allowing pseudo open-drain structure.

3. In Port 2, P1 transistor is continuously driven when outputting a high level bit address (A15:8).

4109H–8051–01/05

AT8xC51SND1C

6. Clock Controller The AT8xC51SND1C clock controller is based on an on-chip osci llator feeding an on-

chip Phase Lock Loop (PLL). All internal clocks to the peripherals and CPU core are generated by this controller.

6.1 Oscillator The AT8xC51SND1C X1 and X2 pins are the input and the output of a single -stage on-

chip inverter (see Figure 4) that can be configured with off-chip components such as a Pierce oscillator (see Figure 5). Value of capacitors and crystal characteristics are detailed in the Section “DC Characteristics”, page 163.

The oscillator outputs three different clocks: a clock for the PLL, a clock for the CPU core, and a clock for the per ipherals as shown in Figu re 4. These clocks are either enabled or disabled, de pendin g on th e power red uctio n mode as detailed in the sec tion “Power Management” on page 48. The peripheral clock is used to generate the Timer 0, Timer 1, MMC, ADC, SPI, and Port sampling clocks.

Figure 4. Oscillator Block Diagram and Symbol

CKCON.0

CPU

0 1

Peripheral Clock

CPU Core Clock

IDL

PCON.0

Oscillator Clock

OSC

CLOCK

Oscillator Clock Symbol

PCON.1

PER

CLOCK

Peripheral Clock Symbol

÷ 2

CLOCK

CPU Core Clock Symbol

Figure 5. Crystal Connection

VSS

6.2 X2 Feature Unlike standard C51 products that require 12 oscillator clock periods per machine cycle,

the AT8xC51SND1C need only 6 oscillator clock periods per machine cycle. This feature called the “X2 feature” can be enabled using the X2 bit and allows the AT8x C51SND1C to operate in 6 or 12 oscillator cloc k periods per machine cycle. As shown in Figure 4, both CPU and peripheral clocks are affected by this feature. Figure 6 shows the X2 mode switching waveforms. After reset the standard mode is activated. In standard mode the CPU and peripheral clock frequency is the oscillator frequency divided by 2 while in X2 mode, it is the oscillator frequency.

(1)

in CKCON (see Table 5)

Note: 1. The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see

Table 12 on page 24). Using the AT89C51SND1C (Flash Version) the system can boot either in standard or X2 mode depending on the X2B value. Using AT83SND1C (ROM Version) the system always boots in standard mode. X2B bit can be changed to X2 mode later by software.

4109H–8051–01/05

Figure 6. Mode Switching Waveforms

X1 ÷ 2

X2 Bit

Clock

AT8xC51SND1C

STD Mode STD Mode

Note: 1. In order to prevent any incorrect operation while operating in X2 mode, user must be

aware that all peripherals using clock frequency as time reference (timers, etc.) will have their time reference divided by 2. For example, a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms.

X2 Mode

(1)

6.3 PLL

6.3.1 PLL Description The AT8xC51SND1C PLL is us ed to generate internal hi gh frequency clo ck (the PLL

Clock) synchronized with an ex ternal low-frequency (the O scillator Clock). The P LL clock provides the MP3 decoder, the audi o interface, and the USB interface cl ocks. Figure 7 shows the internal structure of the PLL.

The PFLD block is the Phase Frequency Comparator and Lock Detector. This block makes the comparison between the reference clock coming from the N divider and the reverse clock coming from the R divider and generates some pulses on the Up or Down signal dependin g on the edge posi tion of the r everse c lock. The P LLEN bit in PLLCO N register is used to enab le the c lock gene ratio n. When the PLL is l ocked, th e bit PL OCK in PLLCON register (see Table 6) is set.

The CHP block is the Charge Pump that generates the voltage reference for the VCO by injecting or extracting charges from the exter nal filte r connected on PFILT pin (see Figure 8) . Value of the filter components are detailed in the Section “DC Characteristics”.

4109H–8051–01/05

The VCO block is the Voltage Controlled Oscillator controlled by the voltage V duced by the charge pump. It generates a square wave signal: the PLL clock.

Figure 7. PLL Block Diagram and Symbol

PFILT

R divider

R9:0

CHP

Vref

VCO

PLL

CLOCK

PLL Clock Symbol

OSC

CLOCK

N divider

N6:0

PLLclk

PLLCON.1

PLLEN

PFLD

Down

PLOCK

PLLCON.0

OSCclk R 1+()

-----------------------------------------------=

N1+

ref

PLL Cloc

pro-

AT8xC51SND1C

Figure 8. PLL Filter Connection

FILT

VSS

6.3.2 PLL Programming The PLL is progra mmed u sing the flo w sho wn in Figure 9. As s oon as c lock g enera tion is enabled, the user must wait until the lo ck indic ator is set to ens ure the cl ock output is stable. The PLL clock fr equenc y will dep end on MP 3 deco der cloc k and au dio int erfac e clock frequencies.

Figure 9. PLL Programming Flow

PLL

Programming

Configure Dividers

N6:0 = xxxxxxb

R9:0 = xxxxxxxxxxb

Enable PLL

PLLRES = 0

PLLEN = 1

PLL Locked?

PLOCK = 1?

4109H–8051–01/05

6.4 Registers Table 5. CKCON Register

CKCON (S:8Fh) – Clock Control Register

76543210

TWIX2 WDX2 - SIX2 - T1X2 T0X2 X2

AT8xC51SND1C

Bit

Number

7TWIX2

6WDX2

4SIX2

2T1X2

1T0X2

0X2

Bit

Mnemonic Description

Two-Wire Clock Control Bit

Set to select the oscillator clock divided by 2 as TWI clock input (X2 independent). Clear to select the peripheral clock as TWI clock input (X2 dependent).

Watchdog Clock Control Bit

Set to select the oscillator clock divided by 2 as watchdog clock input (X2 independent). Clear to select the peripheral clock as watchdog clock input (X2 dependent).

Reserved

The values read from this bit is indeterminate. Do not set this bit.

Enhanced UART Clock (Mode 0 and 2) Control Bit

Set to select the oscillator clock divided by 2 as UART clock input (X2 independent). Clear to select the peripheral clock as UART clock input (X2 dependent)..

Reserved

The values read from this bit is indeterminate. Do not set this bit.

Timer 1 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 1 clock input (X2 independent). Clear to select the peripheral clock as timer 1 clock input (X2 dependent).

Timer 0 Clock Control Bit

Set to select the oscillator clock divided by 2 as timer 0 clock input (X2 independent). Clear to select the peripheral clock as timer 0 clock input (X2 dependent).

System Clock Control Bit

= F

PER

OSC

Clear to select 12 clock periods per ma chine cycle (STD m ode, F

/2).

OSC

Set to select 6 clock periods per machine cycle (X2 mode, F

CPU

= F

CPU

PER

4109H–8051–01/05

Reset Value = 0000 000Xb (AT89C51SND1C) or 0000 0000b (AT83SND1C) Table 6. PLLCON Register

PLLCON (S:E9h) – PLL Control Register

76543210

R1 R0 - - PLLRES - PLLEN PLOCK

Bit

Number

7 - 6 R1:0

5 - 4 -

3 PLLRES

Bit

Mnemonic Description

PLL Least Significant Bits R Divider

2 LSB of the 10-bit R divider.

Reserved

The values read from these bits are always 0. Do not set these bits.

PLL Reset Bit

Set this bit to r e set the PLL. Clear this bit to free the PLL and allow enabling.

AT8xC51SND1C

Bit

Number

1 PLLEN

0PLOCK

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

PLL Enable Bit

Set to enable the PLL. Clear to disable the PLL.

PLL Lock Indicator

Set by hardware when PLL is locked. Clear by hardware when PLL is unlocked.

Reset Value = 0000 1000b Table 7. PLLNDIV Register

PLLNDIV (S:EEh) – PLL N Divider Register

76543210

- N6N5N4N3N2N1N0

Bit

Number

6 - 0 N6:0

Bit

Mnemonic Description

Reserved

The value read from this bit is always 0. Do not set this bit.

PLL N Divider

7 - bit N divider.

Reset Value = 0000 0000b

Table 8. PLLRDIV Register PLLRDIV (S:EFh) – PLL R Divider Register

76543210

R9 R8 R7 R6 R5 R4 R3 R2

Bit

Number

7 - 0 R9:2

Bit

Mnemonic Description

PLL Most Significant Bits R Divider

8 MSB of the 10-bit R divider.

Reset Value = 0000 0000b

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AT8xC51SND1C

7. Program/Code

Memory

The AT8xC51SND1C execute up to 64K Bytes of program/code memory. Figure 10 shows the split of internal and external program/code memory spaces depending on the product.

The AT83SND1C pr odu ct prov id es the i ntern al program/code memor y i n ROM memory while the AT89C51SND1C product provides it in Flash memory. These 2 products do not allow external code memory executio n. External code memory execution is achieved using the AT80C51SND1C product which does not provide any internal program/code memory.

The Flash memory increa ses EP ROM and ROM func tional ity by in-cir cui t electric al erasure and programming. The high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V charge pump. Thus, the AT89C51SND1C can be programmed using only one voltage and allows In-application software programming. Hardware programming mode is also available using common programming tools. See the application note ‘Programming T89C51x and AT89C51x with Device Programmers’.

The AT89C51SND1C implements an additional 4K Bytes of on-chip boot Flash memory provided in Fla sh memor y. Thi s bo ot memo ry is deli vered p rogr ammed with a stand ard boot loader so ftware allowi ng In-System Programm ing (ISP). It also con tains som e Application Prog rammin g Interface r outines named API ro utines allo wing In Appl icatio n Programming (IAP) by using user’s own boot loader.

Figure 10. Program/Code Memory Organization

voltage, made possible by the internal

FFFFh

0000h

AT80C51SND1C

64K Bytes

External Code

FFFFh

0000h

64K Bytes

Code ROM

AT83SND1C

FFFFh

F000h

0000h

AT89C51SND1C

64K Bytes

Code Flash

FFFFh

F000h

4K Bytes

Boot Flash

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AT8xC51SND1C

7.1 ROMLESS Memory

Architecture

As shown in Figure 11 the AT80C51SND1C external memory is composed of one space detailed in the following paragraph.

Figure 11. AT80C51SND1C Memory Architecture

FFFFh

64K Bytes

Use

External Memory

0000h

7.1.1 User Space This space is composed of a 64K By tes co de (Fla sh, EE PROM, EP ROM…) me mory . It contains the user’s application code.

7.1.2 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as the bus control signals (PSEN

, and ALE).

Figure 12 s hows the structure of the external address bus. P0 carries address A7:0 while P2 carries address A15:8. Data D7:0 is multiplexed with A7:0 on P0. Table 12 describes the external memory interface signals.

Figure 12. External Code Memory Interface Structure

AT80C51SND1C

AD7:0

A15:8

Latch

A7:0

ALE

Table 2. External Code Memory Interface Signals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

Flash

EPROM

A15:8

A7:0

D7:0 OEPSEN

Alternate Function

P2.7:0

P0.7:0

Program Store Enable Output (AT80C51SND1C Only)

PSEN

This signal is active low during external code fetch or external code read (MOVC instruction).

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7.2.1 External Bus Cycles This section describes the bus cycles th e A T8 0C5 1SN D1C e xe cu tes to f etc h c od e (se e

Figure 13) in the external program/code memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator

clock periods in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode see section “Clock “.

For simplicity, the accompanying figure depicts the bus cycle waveforms in idealized form and does not provide precise timing information.

For bus cycling parameters refer to the ‘AC-DC parameters’ section. Figure 13. External Code Fetch Waveforms

CPU Clock

ALE

PSEN

7.3 ROM Memory

Architecture

D7:0

PCL

PCHPCH

As shown in Figure 14 the AT83SND1C ROM memory is composed of one space detailed in the following paragraph.

PCLD7:0 D7:0

PCH

Figure 14. AT83SND1C Memory Architecture

FFFFh

64K Bytes

ROM Memory

0000h

User

7.3.1 User Space This space is composed of a 64K Bytes ROM memory programmed during the manufacturing process. It contains the user’s application code.

7.4 Flash Memory

Architecture

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As shown in Figure 15 the AT89C51 SND1C Flas h memor y is compos ed of four spac es detailed in the following paragraphs.

AT8xC51SND1C

Figure 15. AT89C51SND1C Memory Architecture

0000h

Hardware Security

FFFFh

64K Bytes

Flash Memory

Extra Row

User

FFFFh

F000h

4K Bytes

Flash Memory

Boo

7.4.1 User Space This space is composed of a 64K Bytes Flash memory organized in 512 pages of 128 Bytes. It contains the user’s application code.

This space can be read or written by both software and hardware modes.

7.4.2 Boot Space This space is composed of a 4K B ytes F l ash memory. It contains t he b oot lo ader f or InSystem Programming and the routines for In Application Programming.

This space can only be read or wr itt en by hardwa re mode using a par all el progr am min g tool.

7.4.3 Hardware Security Space This space is composed of one Byte: the Hardware Security Byte (HSB see Table 12) divided in 2 separ ate n ibble s. The MSN conta ins the X2 mo de con figur ation bit an d the Boot Loader Jump Bit as detailed in Section “Boot Memory Execution”, page 21 and can be written by software while the LS N co nta ins the l oc k system lev el to pro tec t the memory content against piracy as detailed in Section “Hardware Security System”, page 21 and can only be written by hardware.

7.4.4 Extra Row Space This space is composed of 2 Bytes:

• The Software Boot Vector (SBV, see Table 13).

This Byte is used by the software boot loader to build the boot address.

• The Software Security Byte (SSB, see Table 14).

This Byte is used to lock the execution of some boot loader commands.

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7.5 Hardware Security

System

7.7 Boot Memory

Execution

The AT89C51SND1C implem ents three lock bits LB2:0 in the LSN of HSB ( see Table 12) providing three lev els of secur ity for us er’s p rogr am as descr ibed in Tabl e 12 while the A T83SND1C is always set in read disabled mode.

Level 0 is the level of an erased part and does not enable any security feature. Level 1 locks the hardware programming of both user and boot memories. Level 2 locks also hardware verifying of both user and boot memories Level 3 locks also the external execution.

Table 6. Lock Bit Features

Level LB2

0 U U U Enable Enable Enable Enable Enable 1 U U P Enable Enable Enable Disable Enable 2 U P X Enable Enable Disable Disable Enable

(3)

Notes: 1. U means unprogrammed, P means programmed and X means don’t care (pro-

(2)

LB1 LB0

P X X Enable Dis able Disable Disable Enable

grammed or unprogrammed).

2. LB2 is not implemented in the AT8xC51SND1C products.

3. AT89C51SND1C products are delivered with third level programmed to ensure that the code programmed by software using ISP or user’s boot loader is secured from any hardware piracy.

(1)

Internal

Execution

External

Execution

Hardware

Verifying

Hardware

Programming

Software

Programming

As internal C51 code space is limited to 64K Bytes, some mechanisms are implemented to allow boot memory to be mapped in the code space for ex ecution at addre sses from F000h to FFFFh. The boot memory is enabled by setting the ENBOOT bit in AUXR1 (see Figure 10). The three ways to set this bit are detailed in the following sections.

7.7.1 Software Boot Mapping The software way to set ENBOOT consists in writing to AUXR1 from the user’s software. This enables boot loader or API routines execution.

7.7.2 Hardware Condition

Boot Mapping

The hardware condition is based on the ISP

pin. When driving this pin to low level, the chip reset sets ENBOOT and for ce s the res et vector to F000 h ins te ad of 00 00h i n order to execute the boot loader software.

As shown in Figure 16 the hardware condition always allows in-system recovery when user’s memory has been corrupted.

7.7.3 Programmed Condition Boot Mapping

The programmed con dition is based on the Boot Loader Ju mp Bit (BLJB) in HSB. As shown in Figure 16 when this bit is programmed (by hardware or software programming mode), the chip reset set ENBOOT and forces the reset vec tor to F000h instead of 0000h, in order to execute the boot loader software.

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AT8xC51SND1C

Figure 16. Hardware Boot Process Algorithm

RESET

Hard Cond?

ISP = L?

HardwareSoftware

7.8 Preventing Flash Corruption

Process Process

Standard Init

ENBOOT = 0

PC = 0000h

FCON = F0h

User’s

Application

Prog Cond?

BLJB = P?

Prog Cond Init

ENBOOT = 1

PC = F000h

FCON = F0h

Atmel’s

Boot Loader

Hard Cond Init

ENBOOT = 1

PC = F000h FCON = 00h

The software process (boot loader) is detailed in the “Boot Loader Datasheet” Document.

See Section “Reset Recommendation to Prevent Flash Corruption”, page 49.

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7.9 Registers Table 10. AUXR1 Register

AUXR1 (S:A2h) – Auxiliary Register 1

76543210

- - ENBOOT - GF3 0 - DPS

AT8xC51SND1C

Bit

Number

7 - 6 -

5 ENBOOT

3GF3

1-Reserved for Data Pointer Extension.

0DPS

Bit

Mnemonic Description

Reserved

The value read from these bits are indeterminate. Do not set these bits.

Enable Boot Flash

Set this bit to map the boot Flash in the code space between at addresses F000h

to FFFFh. Clear this bit to disable boot Flash.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

General Flag

This bit is a general-purpose user flag.

Always Zero

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3 flag.

Data Pointer Select Bit

Set to select second data pointer: DPTR1. Clear to select first data pointer: DPTR0.

Reset Value = XXXX 00X0b

Note: 1. ENBOOT bit is only ava il abl e in AT89C51SND1C product.

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AT8xC51SND1C

7.11 Hardware Bytes Table 12. HSB Byte – Hardware Security Byte

76543210

X2B BLJB - - - LB2 LB1 LB0

Bit

Number

7X2B

6BLJB

5 - 4 -

2 - 0 LB2:0

Bit

Mnemonic Description

X2 Bit

(1)

Program this bit to start in X2 mode. Unprogram (erase) this bit to start in standard mode.

Boot Loader Jump Bit

Program this bit to execute the boot loader at address F000h on next reset.

(2)

Unprogram (erase) this bit to execute user’s application at address 0000h on next reset.

Reserved

The value read from these bits is always unprogrammed. Do not program these bits.

Reserved

The value read from this bit is always unprogrammed. Do not program this bit.

Hardware Lock Bits

Refer to for bits description.

Reset Value = XXUU UXXX, UUUU UUUU after an hardware full chip erase.

Note: 1. X2B initializes the X2 bit in CKCON during the reset phase.

2. In order to ensure boot loader activation at first power-up, AT89C51SND1C products are delivered with BLJB programmed.

3. Bits 0 to 3 (LSN) can only be programmed by hardware mode.

Table 13. SBV Byte – Software Boot Vector

76543210

ADD15 ADD14 ADD13 ADD12 ADD11 ADD10 ADD9 ADD8

Bit

Number

7 - 0 ADD15:8

Bit

Mnemonic Description

MSB of the user’s boot loader 16-bi t address location

Refer to the boot loader datasheet for usage information (boot loader dependent)

Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.

Table 14. SSB Byte – Software Security Byte

76543210

SSB7SSB6SSB5SSB4SSB3SSB2SSB1SSB0

Bit

Number

7 - 0 SSB7:0

Bit

Mnemonic Description

Software Security Byte Data

Refer to the boot loader datasheet for usage information (boot loader dependent)

Reset Value = XXXX XXXX, UUUU UUUU after an hardware full chip erase.

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AT8xC51SND1C

8. Data Memory The AT8xC51SND1C provides data memory access in 2 different spaces:

1. The internal space mapped in three separate segments: – The lower 128 Bytes RAM segment – The upper 128 Bytes RAM segment – The expanded 2048 Bytes RAM segment

2. The external space.

A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information on this segment, refer to the Section “Special Function Registers”, page 32.

Figure 17 shows the internal and external data memory spaces organization.

Figure 17. Internal and External Data Memory Organization

FFFFh

64K Bytes

External XRAM

7FFh FFh

00h

2K Bytes

Internal ERAM

EXTRAM = 0

80h 80h 7Fh

00h

Upper

128 Bytes

Internal RAM

Indirect Addressing

Lower

128 Bytes

Internal RAM

Direct or Indirect

Addressing

FFh

Direct Addressing

Special

Function

Registers

0800h

0000h

EXTRAM = 1

8.1 Internal Space

8.1.1 Lower 128 Bytes RAM The lower 128 Bytes of RAM (see Fi gure 18) are accessible from address 00h to 7Fh

using direct or indirect address ing modes. T he lowest 32 Bytes are grouped in to 4 banks of 8 regis ters (R0 to R7 ). 2 bits RS0 and RS1 in PSW re gister (see Table 8) select which bank is in use accord ing to Table 2. T his al lows m ore eff icient us e of cod e space, since register instructions are shorter than instructions that use direct addressing, and can be used for context switching in interrupt service routines.

Table 2. Register Bank Selection

RS1 RS0 Description

0 0 Register bank 0 from 00h to 07h

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0 1 Register bank 1 from 08h to 0Fh 1 0 Register bank 2 from 10h to 17h 1 1 Register bank 3 from 18h to 1Fh

The next 16 Bytes above the register banks form a block of bit-addressable memory space. The C51 instruction set includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these instructions. The bit addresses in this area are 00h to 7Fh.

AT8xC51SND1C

Figure 18. Lower 128 Bytes Internal RAM Organization

7Fh

30h

20h 18h 10h 08h 00h

2Fh

Bit-Addressable Space (Bit Addresses 0-7Fh)

1Fh

17h

4 Banks of 8 Registers

0Fh

R0-R7

07h

8.2.1 Upper 128 Bytes RAM The upper 128 Bytes of RAM are accessible from address 80h to FFh using only indirect addressing mode.

8.2.2 Expanded RAM The on-chip 2K Bytes of expa nded RAM (E RAM ) are acces s ible fr om a ddr ess 0 000h to 07FFh using i ndirect ad dressing mode thro ugh MOVX in structio ns. In this a ddress range, EXTRAM bit in AUXR register (see Table 9) is used to select the ERAM (default) or the XRAM. As shown in Figure 17 when EXTRAM = 0, the ERAM is selected and when EXTRAM = 1, the XRAM is selected (see Section “External Space”).

The ERAM memo ry can be resiz ed using XRS1: 0 bits in AUXR re gister to dynam ically increase external access to the XRAM space. Table 3 details the selected ERAM size and address range.

Table 3. ERAM Size Selection

XRS1 XRS0 ER AM Size Add ress

0 0 256 Bytes 0 to 00FFh 0 1 512 Bytes 0 to 01FFh 1 0 1K Byte 0 to 03FFh 1 1 2K Bytes 0 to 07FFh

Note: Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and must then be initialized properly.

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AT8xC51SND1C

8.4 External Space

8.4.1 Memory Interface The external memory interface comprises the external bus (port 0 and port 2) as well as

the bus control signals (RD Figure 19 s hows the structure of the external address bus. P0 carries address A7:0

while P2 carri es addre ss A15:8. Data D7:0 is multi plexed with A7:0 on P0. Table 5 describes the external memory interface signals.

Figure 19. External Data Memory Interface Structure

, WR, and ALE).

AT8xC51SND1C

AD7:0

A15:8

Latch

A7:0

ALE

Table 5. External Data Memory Interface Signals

Signal

Name Type Description

A15:8 O

AD7:0 I/O

ALE O

Address Lines

Upper address lines for the external bus.

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

Address Latch Enable

ALE signals indicates that valid address information are available on lines AD7:0.

Read

Read signal output to external data memory.

RAM

PERIPHERAL

A15:8

A7:0

D7:0 OERD

Alternate Function

P2.7:0

P0.7:0

P3.7

Write signal output to external memory.

P3.6

Write

8.5.1 Page Access Mode The AT8xC51SND1C impl ement a fea ture call ed Page A ccess tha t disables the outpu t

of DPH on P2 wh en execut ing MO VX @DP TR instru ction. P age Ac cess is enable by setting the DPHDIS bit in AUXR register.

Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it if used in interrupt service routine. Page Access allows external access above 00FFh address with out generating DP H on P2. Thus ERAM is accessed u sing MOVX @Ri or MOVX @DPTR with DPTR < 0100h, < 0200h, < 0400h or < 0800h depending on the XRS1:0 bits value. The n XRAM is a ccessed us ing MOVX @ DPTR with DPTR ≥ 0800h regardless of XRS1:0 bits valu e while ke eping P2 fo r general I/O usage.

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AT8xC51SND1C

8.5.2 External Bus Cycles This section describes the bus cycles the AT8xC51SND1C executes to read (see

Figure 20), and write data (see Figure 21) in the external data memory. External memory cycle takes 6 CPU clock periods. This is equivalent to 12 oscillator clock period in standard mode or 6 oscillator clock periods in X2 mode. For further information on X2 mode, refer to the Section “X2 Feature”, page 12.

Slow peripherals can be acc essed b y stretc hing th e read and write cycles . This is done using the M0 bit in AUXR reg ister. S etting t his bi t changes the widt h of the RD

and WR

signals from 3 to 15 CPU clock periods. For simplicity, Figure 20 and Figure 21 depict the bus cycle waveforms in idealized form

and do not provide precis e timing in forma tion. For bus cycl e timing p aramet ers refe r to the Section “AC Characteri stics”.

Figure 20. External Data Read Waveforms

CPU Clock

ALE

(1)

Notes: 1. RD signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 outputs SFR content instead of DPH.

DPL or Ri D7:0

DPH or P2

(2),(3)

Figure 21. External Data Write Waveforms

CPU Clock

ALE

(1)

Notes: 1. WR signal may be stretched using M0 bit in AUXR register.

2. When executing MOVX @Ri instruction, P2 outputs SFR content.

3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode),

P2 outputs SFR content instead of DPH.

DPL or Ri D7:0

DPH or P2

(2),(3)

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AT8xC51SND1C

8.6 Dual Data Pointer

8.6.1 Description The AT 8xC51S ND1C impl ement a s econd da ta point er for spe eding up code execu tion

and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 ar e seen by the CPU as DPTR and a re access ed using t he SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 10) is us ed to selec t whether DPTR is th e data poin ter 0 or the data pointer 1 (see Figure 22).

Figure 22. Dual Data Pointer Implementation

DPL0 DPL1

DPTR0

DPTR1

DPH0 DPH1

0 1

DPS

0 1

DPL

AUXR1.0

DPH

DPTR

8.6.2 Application Software can take advantage of the additional data pointers to both increase speed and reduce code size, for example, block operations (copy, compare, search …) are well served by using one data poi nter as a “so urce” p ointer and the other one as a “des tination” pointer.

Below is an example of block move implementation using the 2 pointers and coded in assembler. T he latest C compi ler also takes ad vantage of this fe ature by provid ing enhanced algorithm libraries.

The INC instruction is a short (2 Bytes) and fast (6 CPU clocks) way to manipulate the DPS bit in the AUXR 1 reg ister. H owever , note that th e INC i nstruc tion do es no t direc tly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move exa mple, o nly the f act that DP S is tog gled i n the pr oper s equenc e matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry.

4109H–8051–01/05

; ASCII block move using dual data pointers ; Modifies DPTR0, DPTR1, A and PSW ; Ends when encountering NULL character ; Note: DPS exits opposite of entry state unless an extra INC AUXR1 is added

AUXR1 EQU 0A2h

move: mov DPTR,#SOURCE ; address of SOURCE

inc AUXR1 ; switch data pointers mov DPTR,#DEST ; address of DEST

mv_loop: inc AUXR1 ; switch data pointers

movx A,@DPTR ; get a Byte from SOURCE inc DPTR ; increment SOURCE address inc AUXR1 ; switch data pointers movx @DPTR,A ; write the Byte to DEST inc DPTR ; increment DEST address jnz mv_loop ; check for NULL terminator

end_move:

AT8xC51SND1C

8.7 Registers Table 8. PSW Register

PSW (S:8Eh) – Program Status Word Register

76543210

CY A C F0 RS1 RS0 OV F1 P

Bit

Number

7CY

6AC

5F0User Definable Flag 0

4 - 3 RS1:0

2OV

1F1User Definable Flag 1

Bit

Mnemonic Description

Carry Flag

Carry out from bit 1 of ALU operands.

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

Refer to Table 2 for bits description.

Overflow Flag

Overflow set by arithmetic operations.

Parity Bit

Set when ACC contains an odd number of 1’s. Cleared when ACC contains an even number of 1’s.

Reset Value = 0000 0000b

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