ATMEL AT83C51SND1C, AT89C51SND1C User Manual

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Features

• MPEG I/II-Layer 3 Hardwired Decoder

– Stand-alone MP3 Decoder – 48, 44.1, 32, 24, 22.05, 16 kHz Sampling Frequency – Separated Digital Volume Control on Left and Right Channels (Software Control

Using 31 Steps) – Bass, Medium, and Treble Control (31 Steps) – Bass Boost Sound Effect – Ancillary Data Extraction – “CRC Error” and “MPEG Frame Synchronization” Indicators

• Programmable Audio Output for Interfacing With Common Audio DAC

– PCM Format Compatible

–I

S Format Compatible

• 8-bit MCU C51 Core Based (F

• 2304 Bytes of Internal RAM

• 64K Bytes of Code Memory

– Flash: AT89C51SND1C, ROM: AT83C51SND1C

• 4K Bytes of Boot Flash Memory (AT89C51SND1C)

– ISP: Download from USB or UART to Any External Memor y Cards

• USB Rev 1.1 Controller

– “Full Speed” Data Transmission

• Built-in PLL

– MP3 Audio Clocks –USBClock

• MultiMedia Card™ Interface Compatibility

• Atmel DataFlash

• IDE/ATAPI Interface

•2 Channels 10-bit ADC, 8 kHz (8-True Bit)

– Battery Voltage Monitoring – Voice Recording Controlled by Software

• Up to 44 bits of General-purpose I/Os:

– 4-bit Interrupt Keyboard Port for a 4 x n Mat rix – SmartMedia™ Software Interface

• Standard Two 16-bit Timers/Counters

• Hardware Watchdog Timer

• Standard Full Duplex UART with Baud Rate Generator

• Two Wire Interface (TWI) Master and Slave Modes Controller

• SPI Master and Slave Modes Controller

• Power Management

– Power-on Reset – Software Programmable MCU Clock – Idle Mode, Power-down Mode

• Operating Conditions:

–3V,±10%, 25 mA Typical Operating at 25°C – Temperature Range: -40°Cto+85°C

• Packages

– TQFP80, PLCC84 (Development Board) –Dice

SPI Interface Compatibility

=20MHz)

MAX

Single-Chip Microcontroller with M P3 Decoder and Man-Machine Interface

AT83C51SND1C AT89C51SND1C

Preliminary

Summary

Description

The AT8 xC 5 1SND1C are full y integrated stand-alone hardwired MPEG I/II-L ay e r 3 decoders with a C51 microcontroller co re han dling data flow and MP3-player control.

The AT89C51SND1C includes 64K B y tes of Flash memory and al lows In-System Programming through an embedded 4K By tes of Boot Flash Memory.

Rev. 4106F–8051–10/02

The AT83C51SND1C includes 64K Byte s of ROM memory. The AT8xC51SND1C includes 2304 Byt es of RAM memory. The AT8xC51SND1C provides all necessary features for man m achine interface like

timers, keyboard port, serial or parallel interf ace (USB, TWI, SPI, IDE), ADC input, I output, and all external memory interface (NA ND or NOR Flash, SmartMedia, MultiMedia, DataFlash cards).

Typical Applications • MP3 Player

• PDA, C amera, Mobile Phone MP3

• Car Audio/Multimedia MP3

• Home Audio/Multimedia MP3

AT8xC51SND1C

4106F–8051–10/02

Pin Descriptions

AT8xC51SND1C

Figure 1. AT8xC51SND1C, 80-pin TQF P P ac ka ge

ALE

ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3

P1.4 P1.5

P1.6/SCL

P1.7/SDA

FILT

PVSS

VSS

X2 X1

TST

UVSS

P0.0/AD0

P5.0

P5.1

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

21222324252627

P0.1/AD1

P0.2/AD2

P0.3/AD3

P0.4/AD4

P0.5/AD5

VSS

717069

P0.6/AD6

P0.7/AD7

P4.3/SS

AT89C51SND1C-RO (Flash)

AT83C51SND1C-RO (ROM)

302932

P2.0/A8

P4.0/MISO

P2.1/A9

P4.7

P4.6

P4.2/SCK

P4.1/MOSI

34353637383940

60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41

P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS

MCLK MDAT MCMD RST SCLK DSEL DCLK DOUT VSS

4106F–8051–10/02

D+

D-

VSS

INT0

INT1

P3.4/T0

P3.1/TXD

P3.0/R XD

P3.2/

P3.5/T1

P3.3/

AVSS

P3.7/RD

P3.6/WR

AIN0

AREFP

AREFN

P5.3

P5.2

AIN1

Figure 2. AT8xC51SND1C 84-pin PLCC Package

(1)

ALE

ISP P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3

P1.4 P1.5

P1.6/SCL

P1.7/SDA

FILT

PAVSS

VSS

TST

UVSS

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

3334353637

P5.1

P0.0/AD0

P5.0

P0.3/AD3

P0.4/AD4

P0.5/AD5

VSS

P0.2/AD2

P0.1/AD1

432

AT89C51SND1C-SR (Flash)

3839404142

P0.6/AD6

P0.7/AD7

P4.3/SS

P4.2/SCK

84838281807978

444546474849505152

P2.0/A8

P4.1/MOSI

P4.0/MISO

P2.1/A9

P4.7

P4.6

74 73

P4.5

7271P4.4

P2.2/A10

P2.3/A11 P2.4/A12

69 68

P2.5/A13

P2.6/A14

P2.7/A15

VSS

MCLK

MDAT

MCMD

RST

SCLK

DSEL

DCLK

DOUT

VSS

D+

D-

VSS

P3.4/T0

P3.5/T1

P3.3/IN T 1

P3.2/IN T 0

P3.1/TXD

P3.0/RXD

AVSS

P3.7/RD

P3.6/WR

AREFP

AIN1

AIN0

AREFN

P5.3

P5.2

Note: 1. Only samples for development board.

Pin Descriptions All AT8xC51SND1C signals are detailed by funct ionality in Table 1 through Table 14.

Table 1. P ort s Signal Des cription

Signal

Name Type Description

Port 0

P0 isan8-bit open-drainbi-directionalI/O port. Port0 pins thathave 1s

P0.7:0 I/O

P1.7:0 I/O

writtento them float andcan be usedas high impedanceinputs. To avoid any parasitic current consumption, floating P0 inputs must be polarized to

Port 1

P1 is an 8-bit bi-directionalI/O portwith internal pull-ups.

or VSS.

Alternate Function

AD7:0

KIN3:0

SCL SDA

AT8xC51SND1C

4106F–8051–10/02

Table 1. P ort s Signal Des cription (Continue d)

Signal

Name Type Description

AT8xC51SND1C

Alternate Function

P2.7:0 I/O

P3.7:0 I/O

P4.7:0 I/O

P5.3:0 I/O

Port 2

P2 is an 8-bit bi-directionalI/O portwith internal pull-ups.

Port 3

P3 is an 8-bit bi-directionalI/O portwith internal pull-ups.

Port 4

P4 is an 8-bit bi-directionalI/O portwith internal pull-ups.

Port 5

P5 is a 4-bit bi-directionalI/O port with internal pull-ups.

Table 2. Clock Signal Description

Signal

Name Type Description

Input to the on-chip inverting oscillator amplifier

X1 I

To usethe internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, its output is connected to this pin. X1is the clocksource for internal timing.

A15:8

RXD TXD

INT0 INT1

T0 T1

MISO MOSI

SCK

Alternate Function

X2 O

FILT I

Output of the on-chip inverting oscillator amplifier

To usethe internal oscillator, a crystal/resonator circuit is connected to this pin. If an external oscillator is used, leave X2 unconnected.

PLL low pass filter input

FILT receives the RC network ofthe PLL lowpass filter.

Table 3. Timer 0 and Timer 1 Signal Description

Signal

Name Type Description

Timer 0 Gate Input

INT0

serves asexternal run control for timer0,when selected by

GATE0 bitin TCON register.

INT0

INT1

External Interrupt 0

INT0

input sets IE0 in the TCON register. If bit IT0 in this register is set, bitIE0issetbyafallingedgeonINT0 by a low level on INT0

Timer 1 Gate Input

INT1

serves asexternal run control for timer1,when selected by GATE1 bitin TCON register.

External Interrupt 1

INT1

input sets IE1 in the TCON register. If bit IT1 in this register is set, bitIE1issetbyafallingedgeonINT1 by a low level on INT1

Alternate Function

P3.2

.IfbitIT0iscleared,bitIE0isset

P3.3

.IfbitIT1iscleared,bitIE1isset

4106F–8051–10/02

Table 3. Timer 0 and Timer 1 Signal Description (Continued)

Signal

Name Type Description

Alternate Function

T0 I

T1 I

Timer 0 External Clock Input

When Timer 0 operates as a counter, a falling edge on the T0 pin increments the count.

Timer 1 External Clock Input

When Timer 1 operates as a counter, a falling edge on the T1 pin increments the count.

Table 4. A udio Interface Signal Description

Signal

Name Type Description

DCLK O DAC Data Bit Clock -

DOUT O DACAudio Data -

DSEL O

SCLK O

DAC Channel Select Signal

DSEL is the sample rate clock output.

DAC System Clock

SCLK is the oversampling clock synchronized to the digital audio data (DOUT) and the channel selection signal (DSEL).

Table 5. USB Controller Signal Description

Signal

Name Type Description

P3.4

P3.5

Alternate Function

USB Positive Data Upstream Port

D+ I/O

D- I/O USB Negative Data Upstream Port -

This pin requires an external 1.5 kΩ pull-up to operation.

for full speed

Table 6. MutiMediaCard Interface Signal Description

Signal

Name Type Description

MCLK O

MCMD I/O

MDAT I/O

MMC Clock output

Data orcommandclock transfer.

MMC Command line

bi-directional command channel used for card initialization and data transfer commands. To avoid any parasiticcurrentconsumption, unusedMCMD input must be polarized to

MMC Data line

bi-directional data channel. To avoid any parasitic current consumption, unused MDAT input must be polarized to

or VSS.

Alternate Function

AT8xC51SND1C

4106F–8051–10/02

Table 7. UART S ignal Desc ription

Signal

Name Type Description

Receive SerialData

RXD I/O

TXD O

RXD sends and receives data in serial I/O mode 0 and receives data in serial I/O modes 1, 2 and 3.

TransmitSerialData

TXD outputs theshift clock in serial I/Omode 0 and transmits datain serial I/O modes 1, 2 and 3.

Table 8. S P I Controller Sign al Description

Signal

Name Type Description

SPI Master Input Slave Output Data Line

MISO I/O

MOSI I/O

When in master mode, MISO receives data from the slave peripheral. When inslave mode,MISO outputs datato the master controller.

SPI Master OutputSlave Input Data Line

When in master mode, MOSI outputs data to the slave peripheral. When in slave mode, MOSI receives data from the master controller.

AT8xC51SND1C

Alternate Function

P3.0

P3.1

Alternate Function

P4.0

P4.1

SCK I/O

SPI Clock Line

Whenin mastermode, SCKoutputsclockto theslaveperipheral.When in slave mode, SCK receives clock from the master controller.

SPI Slave Select Line

When in controlled slave mode, SS

enables the slave mode.

Table 9. TWI Controller Signal Description

Signal

Name Type Description

TWISerialClock

SCL I/O

SDA I/O

When TWIcontrollerisin master mode, SCL outputsthe serial clock to the slaveperipherals. When TWIcontroller isin slavemode, SCL receives clockfrom the master controller.

TWISerialData

SDA is the bi-directional TWI data line.

Table 10. A/D Converter Signal Description

Signal

Name Type Description

AIN1:0 I A/D Converter Analog Inputs -

AREFP I Analog Positive Voltage ReferenceInput -

P4.2

P4.3

Alternate Function

P1.6

P1.7

Alternate Function

4106F–8051–10/02

AREFN I

Analog Negative Voltage Reference Input

This pinis internallyconnected to AV SS.

Table 11. Keypad Interface Signal Description

Signal

Name Type Description

Alternate Function

KIN3:0 I

Keypad InputLines

Holding oneofthese pinshigh orlow for 24 oscillator periods triggers a keypad interrupt.

Table 12. External Access Signal Description

Signal

Name Type Description

A15:8 I/O

AD7:0 I/O

ALE O

ISP

Address Lines

Upper address lines for the external bus. Multiplexedhigher addressand datalinesfor the IDEinterface.

Address/Data Lines

Multiplexedlower addressand datalines forthe external memoryor the IDE interface.

AddressLatch Enable Output

ALE signals the start of an external bus cycle and indicates that valid address information is available on lines A7:0. An external latch is used to demultiplex the address from address/data bus.

ISP Enable Input

I/O

This signal mustbe heldtoGND through a pull-down resistoratthe falling reset to force execution of the internal bootloader.

Read Signal

Read signal asserted during external data memory read operation.

Write Signal

Write signal asserted during external data memory write operation.

P1.3:0

Alternate Function

P2.7:0

P0.7:0

P3.7

P3.6

Table 13. System Signal Description

Signal

Name Type Description

Reset Input

Holding thispin highfor 64 oscillator periods while the oscillator is running resetsthe device. The Port pins are drivento theirreset conditions when a voltage lowerthan V

RST I

TST I

oscillator is running. Thispin has aninternalpull-downresistor which allows the device tobe resetbyconnecting a capacitor between thispin and AssertingRSTwhenthechipisinIdlemodeorPower-downmode returns the chip to normal operation.

Test Input

T est mode entry signal. This pin must be set to

is applied,whetheror not the

Alternate Function

AT8xC51SND1C

4106F–8051–10/02

Table 14. Power S ignal Des cri ption

Signal

Name Type Description

AT8xC51SND1C

Alternate Function

VSS GND

AVSS GND

PVSS GND

UVSS GND

PWR

Digital SupplyVoltage

Connectt hese pins to+3Vsupplyvoltage.

Circuit Ground

Connectthese pins to ground.

Analog Supply Voltage

Connectthis pin to +3V supply voltage.

Analog Ground

Connectthis pin to ground.

PLL Supply voltage

Connectthis pin to +3V supply voltage.

PLL Circuit Ground

Connectthis pin to ground.

USB Supply Voltage

Connectthis pin to +3V supply voltage.

USB Ground

Connectthis pin to ground.

4106F–8051–10/02

Internal P in Structure

Table 15. Detailed Internal Pin Structure

Circuit

(1)

Type Pins

Watchdog Output

Latch Output

2osc

periods

TST

VSS

VDDV

VSS

Input

Input/Output RST

RST

Input/Output

TST

(2)

(3)

P3 P4

P53:0

MCMD

MDAT

ISP

VSS

D+ D-

Output

Input/Output

ALE SCLK DCLK

DOUT DSEL MCLK

D+

D-

Notes: 1. For information on resistors value, input/output levels, and drive capability, refer t o the Section “DC Characteristics”,

page 24.

2. When the TWI controller is enabled, P

3. In Port 2, P

transistor is continuously driven when outputting a high level bit address (A15:8).

,andP3transistorsare disabled allowing pseudo open-drain structure.

1,P2

AT8xC51SND1C

4106F–8051–10/02

Block Diagram

Figure 3. AT8xC51S ND1C Block Diagram

INT0 INT1 MOSIMISO

VSSV

UVSSUV

AT8xC51SND1C

SCK

AVSSAV

AREF

AIN1:0

RXDTXD

33 33444411

T1T0

SCL SDA

Interrupt

Handler Unit

RAM

2304 Bytes

C51 (X2 C ORE)

MP3 Decoder

Clock and PLL

Unit

FILT X2X1

RST

ISP

Note: 1 Alternate functionof Port 1

3 Alternatefunctionof Port3 4 Alternate function of Port4

Unit

ALE

Flash

ROM

64K Bytes

Flash Boot

4K Bytes

AudioInterface

10-bit A-to-D

Converter

10-bitADC

8-BIT INTERNAL BUS

I2S/PCM

DSELDCLK SCLKDOUT

UART

and

BRG

USB

Controller

D+ D-

Timers 0/1

Watchdog

Interface

MCLK

MMC

MDAT

SPI/DataFlash

Controller

Keyboard

Interface

MCMD

KIN3:0

TWI

Controller

I/O

Ports

IDE

Interface

P0-P5

4106F–8051–10/02

Application Information

Figure 4. AT8xC51S ND1C Typical Application with On-board Atmel DataFlash and TWI LCD

LCD

Battery

Ref.

P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3

FILT

P1.6/SCL

P1.7/SDA

AT8xC51SND1C

AIN1

AIN0

VREFP

VREFN

RST

MCLK MDAT

MCMD

D+

D-

USB PORT

UVSS

MMC1

MMC2

PVSS

P4.2/SCK

P4n

DataFlash Memories

P4.0/SI

P4.1/SO

DOUT

DCLK

DSEL

SCLK

P1.4

P1.5

VSS

AVSS

Audio DAC

Figure 5. AT8xC51S ND1C Typical Application with On-board Atmel DataFlash and LCD

LCD

Battery

Ref.

P1.3

P0.4

P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3

FILT

P0.5

P0.6

P0.7

P1.6/SCL

P1.7/SDA

AIN1

AIN0

VREFP

VREFN

AT8xC51SND1C

RST

MCLK MDAT

MCMD

D+

D-

UVSS

USB PORT

MMC1

MMC2

PVSS

AT8xC51SND1C

P4.2/SCK

P4.n

DataFlash

Memories

DOUT

DCLK

DSEL

SCLK

P1.4

P4.0/SI

P4.1/SO

P1.5

VSS

AVSS

Audio DAC

4106F–8051–10/02

Figure 6. AT8xC51S ND1C Typical Application with On-board SSFDC Flash

LCD

Battery

Ref.

P4.2

P4.4

P4.5

P4.6

P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P1.3/KIN3 P0.0 P0.1 P0.2 P0.3

FILT

P4.0

P4.1

P4.7

AIN1

AT8xC51SND1C

AIN0

VREFP

VREFN

AT8xC51SND1C

RST

MCLK MDAT

MCMD

D+

D-

UVSS

USB PORT

MMC1

MMC2

PVSS

SSFDC Memories

or SmartMedia Cards

P3.6/WR

P3.7/RD

SmartMedia

DOUT

DCLK

DSEL

SCLK

Figure 7. AT8xC51S ND1C Typical Application with IDE CD-RO M Drive

LCD

Battery

Ref.

P4.2

P4.4

P4.5

P4.6

P4.0

P1.0/KIN0 P1.1/KIN1 P1.2/KIN2 P0.0 P0.1 P0.2 P0.3

FILT

P4.1

P4.7

P1.6/SCL

P1.7/SDA

AIN1

AIN0

VREFP

AT8xC51SND1C

P3.4

P3.5

Audio DAC

VREFN

VSS

AVSS

RST

MCLK MDAT

MCMD

D+

D-

UVSS

USB PORT

MMC1

MMC2

4106F–8051–10/02

PVSS

IDE CD-ROM

P3.6/WR

P3.7/RD

DOUT

DCLK

DSEL

SCLK

P3.4

P3.5

VSS

AVSS

Audio DAC

Address Sp aces The AT8xC51SND1C derivatives implement four different address spaces:

• Program/Code Memory

• Boot Memory

• Data Memory

• Special Function Registers (SFRs)

Code Memory The AT89C51SND1C and AT83C51SND1C implement 64K Bytes of on-chip pro-

gram/code memory. The AT83C51SND1 C product provides the internal p rogram/code memory in ROM technology while the AT89C51SND1C product provides i t in Flash technology.

The Flash memory increases ROM functionality by enabling in-circuit ele ctrical erasure and programming. Thanks to the internal charge pump, the high voltage needed for programming or erasing Flash cells is generated on-chip using the standard V Thus, the AT89C51SND1C can be programmed using only one voltage and allows in application software programming commonly known as IAP. Hardware programming mode is also available using specific programm ing tools.

Boot Memory The AT89C51SND1C implements 4K Bytes of on-chip boot me mory prov ided in Flash

technology. This bo ot memory is delivered p ro grammed with a standard bootloader software allowing In-system Programming comm only known as ISP. It also contains some Application Programming Int erf aces routines commonly known as API allowing user to develop his own bootloader.

voltage.

Data Memory The AT8xC51SND1 derivatives implement 2304 B ytes of on-chip data R AM. T his mem-

ory is divided in two s eparate areas:

• 256 Bytes of on-chip RAM memory (standard C51 memory).

• 2048 Bytes of on-chip expanded RAM memory (E RAM accessible via MOVX instructions).

AT8xC51SND1C

4106F–8051–10/02

AT8xC51SND1C

Special Function Registers

The Special Function Registers (SFRs) of the AT8xC51SND1 derivatives fall into the categories detailed in Table 16 through Table 32. The relative addres ses of these S FRs are provided together with their reset values in Table 33. In this table, the bit-addressable registers are identified by Note 1.

Table 16. C51CoreSFRs

MnemonicAddName 765 43210

ACC E0h Accumulator – – – – – – – – BF0hBRegister ––––––––

PSW D0h

SP 81h Stack Pointer – – – – – – – –

DPL 82h

DPH 83h

ProgramStatus Word

Data PointerLow byte

Data PointerHigh byte

CY AC F0 RS1 RS0 OV F1 P

––––––––

Table 17. System Managem ent SFRs

MnemonicAddName 765 43210

PCON 87h Power Control SMOD1 SMOD0 – – GF1 GF0 PD IDL AUXR 8Eh Auxiliary Register 0 – EXT16 M0 DPHDIS XRS1 XRS0 EXTRAM AO AUXR1 A2h Auxiliary Register 1 – – ENBOOT – GF3 0 – DPS NVERS FBh Version Number NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0

Table 18. PLL and System Clock SFRs

MnemonicAddName 765 43210

CKCON 8Fh Clock Control – – – – – – – X2 PLLCON E9h PLL Control R1 R0 – – PLLRES – PLLEN PLOCK PLLNDIV EEh PLL N Divider – N6 N5 N4 N3 N2 N1 N0 PLLRDIVEFhPLLRDivider R9R8R7R6R5R4R3R2

4106F–8051–10/02

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